1 /* 2 * QEMU ETRAX System Emulator 3 * 4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/sysbus.h" 28 #include "chardev/char-fe.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 32 #define D(x) 33 34 #define RW_TR_CTRL (0x00 / 4) 35 #define RW_TR_DMA_EN (0x04 / 4) 36 #define RW_REC_CTRL (0x08 / 4) 37 #define RW_DOUT (0x1c / 4) 38 #define RS_STAT_DIN (0x20 / 4) 39 #define R_STAT_DIN (0x24 / 4) 40 #define RW_INTR_MASK (0x2c / 4) 41 #define RW_ACK_INTR (0x30 / 4) 42 #define R_INTR (0x34 / 4) 43 #define R_MASKED_INTR (0x38 / 4) 44 #define R_MAX (0x3c / 4) 45 46 #define STAT_DAV 16 47 #define STAT_TR_IDLE 22 48 #define STAT_TR_RDY 24 49 50 #define TYPE_ETRAX_FS_SERIAL "etraxfs,serial" 51 #define ETRAX_SERIAL(obj) \ 52 OBJECT_CHECK(ETRAXSerial, (obj), TYPE_ETRAX_FS_SERIAL) 53 54 typedef struct ETRAXSerial { 55 SysBusDevice parent_obj; 56 57 MemoryRegion mmio; 58 CharBackend chr; 59 qemu_irq irq; 60 61 int pending_tx; 62 63 uint8_t rx_fifo[16]; 64 unsigned int rx_fifo_pos; 65 unsigned int rx_fifo_len; 66 67 /* Control registers. */ 68 uint32_t regs[R_MAX]; 69 } ETRAXSerial; 70 71 static void ser_update_irq(ETRAXSerial *s) 72 { 73 74 if (s->rx_fifo_len) { 75 s->regs[R_INTR] |= 8; 76 } else { 77 s->regs[R_INTR] &= ~8; 78 } 79 80 s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK]; 81 qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]); 82 } 83 84 static uint64_t 85 ser_read(void *opaque, hwaddr addr, unsigned int size) 86 { 87 ETRAXSerial *s = opaque; 88 uint32_t r = 0; 89 90 addr >>= 2; 91 switch (addr) 92 { 93 case R_STAT_DIN: 94 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15]; 95 if (s->rx_fifo_len) { 96 r |= 1 << STAT_DAV; 97 } 98 r |= 1 << STAT_TR_RDY; 99 r |= 1 << STAT_TR_IDLE; 100 break; 101 case RS_STAT_DIN: 102 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15]; 103 if (s->rx_fifo_len) { 104 r |= 1 << STAT_DAV; 105 s->rx_fifo_len--; 106 } 107 r |= 1 << STAT_TR_RDY; 108 r |= 1 << STAT_TR_IDLE; 109 break; 110 default: 111 r = s->regs[addr]; 112 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r)); 113 break; 114 } 115 return r; 116 } 117 118 static void 119 ser_write(void *opaque, hwaddr addr, 120 uint64_t val64, unsigned int size) 121 { 122 ETRAXSerial *s = opaque; 123 uint32_t value = val64; 124 unsigned char ch = val64; 125 126 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value)); 127 addr >>= 2; 128 switch (addr) 129 { 130 case RW_DOUT: 131 /* XXX this blocks entire thread. Rewrite to use 132 * qemu_chr_fe_write and background I/O callbacks */ 133 qemu_chr_fe_write_all(&s->chr, &ch, 1); 134 s->regs[R_INTR] |= 3; 135 s->pending_tx = 1; 136 s->regs[addr] = value; 137 break; 138 case RW_ACK_INTR: 139 if (s->pending_tx) { 140 value &= ~1; 141 s->pending_tx = 0; 142 D(qemu_log("fixedup value=%x r_intr=%x\n", 143 value, s->regs[R_INTR])); 144 } 145 s->regs[addr] = value; 146 s->regs[R_INTR] &= ~value; 147 D(printf("r_intr=%x\n", s->regs[R_INTR])); 148 break; 149 default: 150 s->regs[addr] = value; 151 break; 152 } 153 ser_update_irq(s); 154 } 155 156 static const MemoryRegionOps ser_ops = { 157 .read = ser_read, 158 .write = ser_write, 159 .endianness = DEVICE_NATIVE_ENDIAN, 160 .valid = { 161 .min_access_size = 4, 162 .max_access_size = 4 163 } 164 }; 165 166 static Property etraxfs_ser_properties[] = { 167 DEFINE_PROP_CHR("chardev", ETRAXSerial, chr), 168 DEFINE_PROP_END_OF_LIST(), 169 }; 170 171 static void serial_receive(void *opaque, const uint8_t *buf, int size) 172 { 173 ETRAXSerial *s = opaque; 174 int i; 175 176 /* Got a byte. */ 177 if (s->rx_fifo_len >= 16) { 178 D(qemu_log("WARNING: UART dropped char.\n")); 179 return; 180 } 181 182 for (i = 0; i < size; i++) { 183 s->rx_fifo[s->rx_fifo_pos] = buf[i]; 184 s->rx_fifo_pos++; 185 s->rx_fifo_pos &= 15; 186 s->rx_fifo_len++; 187 } 188 189 ser_update_irq(s); 190 } 191 192 static int serial_can_receive(void *opaque) 193 { 194 ETRAXSerial *s = opaque; 195 196 /* Is the receiver enabled? */ 197 if (!(s->regs[RW_REC_CTRL] & (1 << 3))) { 198 return 0; 199 } 200 201 return sizeof(s->rx_fifo) - s->rx_fifo_len; 202 } 203 204 static void serial_event(void *opaque, int event) 205 { 206 207 } 208 209 static void etraxfs_ser_reset(DeviceState *d) 210 { 211 ETRAXSerial *s = ETRAX_SERIAL(d); 212 213 /* transmitter begins ready and idle. */ 214 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY); 215 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE); 216 217 s->regs[RW_REC_CTRL] = 0x10000; 218 219 } 220 221 static void etraxfs_ser_init(Object *obj) 222 { 223 ETRAXSerial *s = ETRAX_SERIAL(obj); 224 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 225 226 sysbus_init_irq(dev, &s->irq); 227 memory_region_init_io(&s->mmio, obj, &ser_ops, s, 228 "etraxfs-serial", R_MAX * 4); 229 sysbus_init_mmio(dev, &s->mmio); 230 } 231 232 static void etraxfs_ser_realize(DeviceState *dev, Error **errp) 233 { 234 ETRAXSerial *s = ETRAX_SERIAL(dev); 235 236 qemu_chr_fe_set_handlers(&s->chr, 237 serial_can_receive, serial_receive, 238 serial_event, NULL, s, NULL, true); 239 } 240 241 static void etraxfs_ser_class_init(ObjectClass *klass, void *data) 242 { 243 DeviceClass *dc = DEVICE_CLASS(klass); 244 245 dc->reset = etraxfs_ser_reset; 246 dc->props = etraxfs_ser_properties; 247 dc->realize = etraxfs_ser_realize; 248 } 249 250 static const TypeInfo etraxfs_ser_info = { 251 .name = TYPE_ETRAX_FS_SERIAL, 252 .parent = TYPE_SYS_BUS_DEVICE, 253 .instance_size = sizeof(ETRAXSerial), 254 .instance_init = etraxfs_ser_init, 255 .class_init = etraxfs_ser_class_init, 256 }; 257 258 static void etraxfs_serial_register_types(void) 259 { 260 type_register_static(&etraxfs_ser_info); 261 } 262 263 type_init(etraxfs_serial_register_types) 264