1 /* 2 * QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/irq.h" 28 #include "hw/sysbus.h" 29 #include "migration/vmstate.h" 30 #include "qemu/module.h" 31 #include "hw/char/escc.h" 32 #include "ui/console.h" 33 #include "trace.h" 34 35 /* 36 * Chipset docs: 37 * "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual", 38 * http://www.zilog.com/docs/serial/scc_escc_um.pdf 39 * 40 * On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001 41 * (Slave I/O), also produced as NCR89C105. See 42 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt 43 * 44 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips, 45 * mouse and keyboard ports don't implement all functions and they are 46 * only asynchronous. There is no DMA. 47 * 48 * Z85C30 is also used on PowerMacs. There are some small differences 49 * between Sparc version (sunzilog) and PowerMac (pmac): 50 * Offset between control and data registers 51 * There is some kind of lockup bug, but we can ignore it 52 * CTS is inverted 53 * DMA on pmac using DBDMA chip 54 * pmac can do IRDA and faster rates, sunzilog can only do 38400 55 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz 56 */ 57 58 /* 59 * Modifications: 60 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented 61 * serial mouse queue. 62 * Implemented serial mouse protocol. 63 * 64 * 2010-May-23 Artyom Tarasenko: Reworked IUS logic 65 */ 66 67 #define CHN_C(s) ((s)->chn == escc_chn_b ? 'b' : 'a') 68 69 #define SERIAL_CTRL 0 70 #define SERIAL_DATA 1 71 72 #define W_CMD 0 73 #define CMD_PTR_MASK 0x07 74 #define CMD_CMD_MASK 0x38 75 #define CMD_HI 0x08 76 #define CMD_CLR_TXINT 0x28 77 #define CMD_CLR_IUS 0x38 78 #define W_INTR 1 79 #define INTR_INTALL 0x01 80 #define INTR_TXINT 0x02 81 #define INTR_RXMODEMSK 0x18 82 #define INTR_RXINT1ST 0x08 83 #define INTR_RXINTALL 0x10 84 #define W_IVEC 2 85 #define W_RXCTRL 3 86 #define RXCTRL_RXEN 0x01 87 #define W_TXCTRL1 4 88 #define TXCTRL1_PAREN 0x01 89 #define TXCTRL1_PAREV 0x02 90 #define TXCTRL1_1STOP 0x04 91 #define TXCTRL1_1HSTOP 0x08 92 #define TXCTRL1_2STOP 0x0c 93 #define TXCTRL1_STPMSK 0x0c 94 #define TXCTRL1_CLK1X 0x00 95 #define TXCTRL1_CLK16X 0x40 96 #define TXCTRL1_CLK32X 0x80 97 #define TXCTRL1_CLK64X 0xc0 98 #define TXCTRL1_CLKMSK 0xc0 99 #define W_TXCTRL2 5 100 #define TXCTRL2_TXEN 0x08 101 #define TXCTRL2_BITMSK 0x60 102 #define TXCTRL2_5BITS 0x00 103 #define TXCTRL2_7BITS 0x20 104 #define TXCTRL2_6BITS 0x40 105 #define TXCTRL2_8BITS 0x60 106 #define W_SYNC1 6 107 #define W_SYNC2 7 108 #define W_TXBUF 8 109 #define W_MINTR 9 110 #define MINTR_STATUSHI 0x10 111 #define MINTR_RST_MASK 0xc0 112 #define MINTR_RST_B 0x40 113 #define MINTR_RST_A 0x80 114 #define MINTR_RST_ALL 0xc0 115 #define W_MISC1 10 116 #define W_CLOCK 11 117 #define CLOCK_TRXC 0x08 118 #define W_BRGLO 12 119 #define W_BRGHI 13 120 #define W_MISC2 14 121 #define MISC2_PLLDIS 0x30 122 #define W_EXTINT 15 123 #define EXTINT_DCD 0x08 124 #define EXTINT_SYNCINT 0x10 125 #define EXTINT_CTSINT 0x20 126 #define EXTINT_TXUNDRN 0x40 127 #define EXTINT_BRKINT 0x80 128 129 #define R_STATUS 0 130 #define STATUS_RXAV 0x01 131 #define STATUS_ZERO 0x02 132 #define STATUS_TXEMPTY 0x04 133 #define STATUS_DCD 0x08 134 #define STATUS_SYNC 0x10 135 #define STATUS_CTS 0x20 136 #define STATUS_TXUNDRN 0x40 137 #define STATUS_BRK 0x80 138 #define R_SPEC 1 139 #define SPEC_ALLSENT 0x01 140 #define SPEC_BITS8 0x06 141 #define R_IVEC 2 142 #define IVEC_TXINTB 0x00 143 #define IVEC_LONOINT 0x06 144 #define IVEC_LORXINTA 0x0c 145 #define IVEC_LORXINTB 0x04 146 #define IVEC_LOTXINTA 0x08 147 #define IVEC_HINOINT 0x60 148 #define IVEC_HIRXINTA 0x30 149 #define IVEC_HIRXINTB 0x20 150 #define IVEC_HITXINTA 0x10 151 #define R_INTR 3 152 #define INTR_EXTINTB 0x01 153 #define INTR_TXINTB 0x02 154 #define INTR_RXINTB 0x04 155 #define INTR_EXTINTA 0x08 156 #define INTR_TXINTA 0x10 157 #define INTR_RXINTA 0x20 158 #define R_IPEN 4 159 #define R_TXCTRL1 5 160 #define R_TXCTRL2 6 161 #define R_BC 7 162 #define R_RXBUF 8 163 #define R_RXCTRL 9 164 #define R_MISC 10 165 #define R_MISC1 11 166 #define R_BRGLO 12 167 #define R_BRGHI 13 168 #define R_MISC1I 14 169 #define R_EXTINT 15 170 171 static void handle_kbd_command(ESCCChannelState *s, int val); 172 static int serial_can_receive(void *opaque); 173 static void serial_receive_byte(ESCCChannelState *s, int ch); 174 175 static void clear_queue(void *opaque) 176 { 177 ESCCChannelState *s = opaque; 178 ESCCSERIOQueue *q = &s->queue; 179 q->rptr = q->wptr = q->count = 0; 180 } 181 182 static void put_queue(void *opaque, int b) 183 { 184 ESCCChannelState *s = opaque; 185 ESCCSERIOQueue *q = &s->queue; 186 187 trace_escc_put_queue(CHN_C(s), b); 188 if (q->count >= ESCC_SERIO_QUEUE_SIZE) { 189 return; 190 } 191 q->data[q->wptr] = b; 192 if (++q->wptr == ESCC_SERIO_QUEUE_SIZE) { 193 q->wptr = 0; 194 } 195 q->count++; 196 serial_receive_byte(s, 0); 197 } 198 199 static uint32_t get_queue(void *opaque) 200 { 201 ESCCChannelState *s = opaque; 202 ESCCSERIOQueue *q = &s->queue; 203 int val; 204 205 if (q->count == 0) { 206 return 0; 207 } else { 208 val = q->data[q->rptr]; 209 if (++q->rptr == ESCC_SERIO_QUEUE_SIZE) { 210 q->rptr = 0; 211 } 212 q->count--; 213 } 214 trace_escc_get_queue(CHN_C(s), val); 215 if (q->count > 0) 216 serial_receive_byte(s, 0); 217 return val; 218 } 219 220 static int escc_update_irq_chn(ESCCChannelState *s) 221 { 222 if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint == 1)) || 223 // tx ints enabled, pending 224 ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) || 225 ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) && 226 s->rxint == 1) || // rx ints enabled, pending 227 ((s->wregs[W_EXTINT] & EXTINT_BRKINT) && 228 (s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p 229 return 1; 230 } 231 return 0; 232 } 233 234 static void escc_update_irq(ESCCChannelState *s) 235 { 236 int irq; 237 238 irq = escc_update_irq_chn(s); 239 irq |= escc_update_irq_chn(s->otherchn); 240 241 trace_escc_update_irq(irq); 242 qemu_set_irq(s->irq, irq); 243 } 244 245 static void escc_reset_chn(ESCCChannelState *s) 246 { 247 int i; 248 249 s->reg = 0; 250 for (i = 0; i < ESCC_SERIAL_REGS; i++) { 251 s->rregs[i] = 0; 252 s->wregs[i] = 0; 253 } 254 s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no parity 255 s->wregs[W_MINTR] = MINTR_RST_ALL; 256 s->wregs[W_CLOCK] = CLOCK_TRXC; // Synch mode tx clock = TRxC 257 s->wregs[W_MISC2] = MISC2_PLLDIS; // PLL disabled 258 s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | 259 EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts 260 if (s->disabled) 261 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | 262 STATUS_CTS | STATUS_TXUNDRN; 263 else 264 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN; 265 s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT; 266 267 s->rx = s->tx = 0; 268 s->rxint = s->txint = 0; 269 s->rxint_under_svc = s->txint_under_svc = 0; 270 s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0; 271 clear_queue(s); 272 } 273 274 static void escc_reset(DeviceState *d) 275 { 276 ESCCState *s = ESCC(d); 277 278 escc_reset_chn(&s->chn[0]); 279 escc_reset_chn(&s->chn[1]); 280 } 281 282 static inline void set_rxint(ESCCChannelState *s) 283 { 284 s->rxint = 1; 285 /* XXX: missing daisy chainnig: escc_chn_b rx should have a lower priority 286 than chn_a rx/tx/special_condition service*/ 287 s->rxint_under_svc = 1; 288 if (s->chn == escc_chn_a) { 289 s->rregs[R_INTR] |= INTR_RXINTA; 290 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 291 s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA; 292 else 293 s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA; 294 } else { 295 s->otherchn->rregs[R_INTR] |= INTR_RXINTB; 296 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 297 s->rregs[R_IVEC] = IVEC_HIRXINTB; 298 else 299 s->rregs[R_IVEC] = IVEC_LORXINTB; 300 } 301 escc_update_irq(s); 302 } 303 304 static inline void set_txint(ESCCChannelState *s) 305 { 306 s->txint = 1; 307 if (!s->rxint_under_svc) { 308 s->txint_under_svc = 1; 309 if (s->chn == escc_chn_a) { 310 if (s->wregs[W_INTR] & INTR_TXINT) { 311 s->rregs[R_INTR] |= INTR_TXINTA; 312 } 313 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 314 s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA; 315 else 316 s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA; 317 } else { 318 s->rregs[R_IVEC] = IVEC_TXINTB; 319 if (s->wregs[W_INTR] & INTR_TXINT) { 320 s->otherchn->rregs[R_INTR] |= INTR_TXINTB; 321 } 322 } 323 escc_update_irq(s); 324 } 325 } 326 327 static inline void clr_rxint(ESCCChannelState *s) 328 { 329 s->rxint = 0; 330 s->rxint_under_svc = 0; 331 if (s->chn == escc_chn_a) { 332 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 333 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; 334 else 335 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; 336 s->rregs[R_INTR] &= ~INTR_RXINTA; 337 } else { 338 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 339 s->rregs[R_IVEC] = IVEC_HINOINT; 340 else 341 s->rregs[R_IVEC] = IVEC_LONOINT; 342 s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB; 343 } 344 if (s->txint) 345 set_txint(s); 346 escc_update_irq(s); 347 } 348 349 static inline void clr_txint(ESCCChannelState *s) 350 { 351 s->txint = 0; 352 s->txint_under_svc = 0; 353 if (s->chn == escc_chn_a) { 354 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 355 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; 356 else 357 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; 358 s->rregs[R_INTR] &= ~INTR_TXINTA; 359 } else { 360 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; 361 if (s->wregs[W_MINTR] & MINTR_STATUSHI) 362 s->rregs[R_IVEC] = IVEC_HINOINT; 363 else 364 s->rregs[R_IVEC] = IVEC_LONOINT; 365 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; 366 } 367 if (s->rxint) 368 set_rxint(s); 369 escc_update_irq(s); 370 } 371 372 static void escc_update_parameters(ESCCChannelState *s) 373 { 374 int speed, parity, data_bits, stop_bits; 375 QEMUSerialSetParams ssp; 376 377 if (!qemu_chr_fe_backend_connected(&s->chr) || s->type != escc_serial) 378 return; 379 380 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) { 381 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) 382 parity = 'E'; 383 else 384 parity = 'O'; 385 } else { 386 parity = 'N'; 387 } 388 if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP) 389 stop_bits = 2; 390 else 391 stop_bits = 1; 392 switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) { 393 case TXCTRL2_5BITS: 394 data_bits = 5; 395 break; 396 case TXCTRL2_7BITS: 397 data_bits = 7; 398 break; 399 case TXCTRL2_6BITS: 400 data_bits = 6; 401 break; 402 default: 403 case TXCTRL2_8BITS: 404 data_bits = 8; 405 break; 406 } 407 speed = s->clock / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2); 408 switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) { 409 case TXCTRL1_CLK1X: 410 break; 411 case TXCTRL1_CLK16X: 412 speed /= 16; 413 break; 414 case TXCTRL1_CLK32X: 415 speed /= 32; 416 break; 417 default: 418 case TXCTRL1_CLK64X: 419 speed /= 64; 420 break; 421 } 422 ssp.speed = speed; 423 ssp.parity = parity; 424 ssp.data_bits = data_bits; 425 ssp.stop_bits = stop_bits; 426 trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits); 427 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 428 } 429 430 static void escc_mem_write(void *opaque, hwaddr addr, 431 uint64_t val, unsigned size) 432 { 433 ESCCState *serial = opaque; 434 ESCCChannelState *s; 435 uint32_t saddr; 436 int newreg, channel; 437 438 val &= 0xff; 439 saddr = (addr >> serial->it_shift) & 1; 440 channel = (addr >> (serial->it_shift + 1)) & 1; 441 s = &serial->chn[channel]; 442 switch (saddr) { 443 case SERIAL_CTRL: 444 trace_escc_mem_writeb_ctrl(CHN_C(s), s->reg, val & 0xff); 445 newreg = 0; 446 switch (s->reg) { 447 case W_CMD: 448 newreg = val & CMD_PTR_MASK; 449 val &= CMD_CMD_MASK; 450 switch (val) { 451 case CMD_HI: 452 newreg |= CMD_HI; 453 break; 454 case CMD_CLR_TXINT: 455 clr_txint(s); 456 break; 457 case CMD_CLR_IUS: 458 if (s->rxint_under_svc) { 459 s->rxint_under_svc = 0; 460 if (s->txint) { 461 set_txint(s); 462 } 463 } else if (s->txint_under_svc) { 464 s->txint_under_svc = 0; 465 } 466 escc_update_irq(s); 467 break; 468 default: 469 break; 470 } 471 break; 472 case W_INTR ... W_RXCTRL: 473 case W_SYNC1 ... W_TXBUF: 474 case W_MISC1 ... W_CLOCK: 475 case W_MISC2 ... W_EXTINT: 476 s->wregs[s->reg] = val; 477 break; 478 case W_TXCTRL1: 479 case W_TXCTRL2: 480 s->wregs[s->reg] = val; 481 escc_update_parameters(s); 482 break; 483 case W_BRGLO: 484 case W_BRGHI: 485 s->wregs[s->reg] = val; 486 s->rregs[s->reg] = val; 487 escc_update_parameters(s); 488 break; 489 case W_MINTR: 490 switch (val & MINTR_RST_MASK) { 491 case 0: 492 default: 493 break; 494 case MINTR_RST_B: 495 escc_reset_chn(&serial->chn[0]); 496 return; 497 case MINTR_RST_A: 498 escc_reset_chn(&serial->chn[1]); 499 return; 500 case MINTR_RST_ALL: 501 escc_reset(DEVICE(serial)); 502 return; 503 } 504 break; 505 default: 506 break; 507 } 508 if (s->reg == 0) 509 s->reg = newreg; 510 else 511 s->reg = 0; 512 break; 513 case SERIAL_DATA: 514 trace_escc_mem_writeb_data(CHN_C(s), val); 515 /* 516 * Lower the irq when data is written to the Tx buffer and no other 517 * interrupts are currently pending. The irq will be raised again once 518 * the Tx buffer becomes empty below. 519 */ 520 s->txint = 0; 521 escc_update_irq(s); 522 s->tx = val; 523 if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled 524 if (qemu_chr_fe_backend_connected(&s->chr)) { 525 /* XXX this blocks entire thread. Rewrite to use 526 * qemu_chr_fe_write and background I/O callbacks */ 527 qemu_chr_fe_write_all(&s->chr, &s->tx, 1); 528 } else if (s->type == escc_kbd && !s->disabled) { 529 handle_kbd_command(s, val); 530 } 531 } 532 s->rregs[R_STATUS] |= STATUS_TXEMPTY; // Tx buffer empty 533 s->rregs[R_SPEC] |= SPEC_ALLSENT; // All sent 534 set_txint(s); 535 break; 536 default: 537 break; 538 } 539 } 540 541 static uint64_t escc_mem_read(void *opaque, hwaddr addr, 542 unsigned size) 543 { 544 ESCCState *serial = opaque; 545 ESCCChannelState *s; 546 uint32_t saddr; 547 uint32_t ret; 548 int channel; 549 550 saddr = (addr >> serial->it_shift) & 1; 551 channel = (addr >> (serial->it_shift + 1)) & 1; 552 s = &serial->chn[channel]; 553 switch (saddr) { 554 case SERIAL_CTRL: 555 trace_escc_mem_readb_ctrl(CHN_C(s), s->reg, s->rregs[s->reg]); 556 ret = s->rregs[s->reg]; 557 s->reg = 0; 558 return ret; 559 case SERIAL_DATA: 560 s->rregs[R_STATUS] &= ~STATUS_RXAV; 561 clr_rxint(s); 562 if (s->type == escc_kbd || s->type == escc_mouse) { 563 ret = get_queue(s); 564 } else { 565 ret = s->rx; 566 } 567 trace_escc_mem_readb_data(CHN_C(s), ret); 568 qemu_chr_fe_accept_input(&s->chr); 569 return ret; 570 default: 571 break; 572 } 573 return 0; 574 } 575 576 static const MemoryRegionOps escc_mem_ops = { 577 .read = escc_mem_read, 578 .write = escc_mem_write, 579 .endianness = DEVICE_NATIVE_ENDIAN, 580 .valid = { 581 .min_access_size = 1, 582 .max_access_size = 1, 583 }, 584 }; 585 586 static int serial_can_receive(void *opaque) 587 { 588 ESCCChannelState *s = opaque; 589 int ret; 590 591 if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) // Rx not enabled 592 || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV)) 593 // char already available 594 ret = 0; 595 else 596 ret = 1; 597 return ret; 598 } 599 600 static void serial_receive_byte(ESCCChannelState *s, int ch) 601 { 602 trace_escc_serial_receive_byte(CHN_C(s), ch); 603 s->rregs[R_STATUS] |= STATUS_RXAV; 604 s->rx = ch; 605 set_rxint(s); 606 } 607 608 static void serial_receive_break(ESCCChannelState *s) 609 { 610 s->rregs[R_STATUS] |= STATUS_BRK; 611 escc_update_irq(s); 612 } 613 614 static void serial_receive1(void *opaque, const uint8_t *buf, int size) 615 { 616 ESCCChannelState *s = opaque; 617 serial_receive_byte(s, buf[0]); 618 } 619 620 static void serial_event(void *opaque, int event) 621 { 622 ESCCChannelState *s = opaque; 623 if (event == CHR_EVENT_BREAK) 624 serial_receive_break(s); 625 } 626 627 static const VMStateDescription vmstate_escc_chn = { 628 .name ="escc_chn", 629 .version_id = 2, 630 .minimum_version_id = 1, 631 .fields = (VMStateField[]) { 632 VMSTATE_UINT32(vmstate_dummy, ESCCChannelState), 633 VMSTATE_UINT32(reg, ESCCChannelState), 634 VMSTATE_UINT32(rxint, ESCCChannelState), 635 VMSTATE_UINT32(txint, ESCCChannelState), 636 VMSTATE_UINT32(rxint_under_svc, ESCCChannelState), 637 VMSTATE_UINT32(txint_under_svc, ESCCChannelState), 638 VMSTATE_UINT8(rx, ESCCChannelState), 639 VMSTATE_UINT8(tx, ESCCChannelState), 640 VMSTATE_BUFFER(wregs, ESCCChannelState), 641 VMSTATE_BUFFER(rregs, ESCCChannelState), 642 VMSTATE_END_OF_LIST() 643 } 644 }; 645 646 static const VMStateDescription vmstate_escc = { 647 .name ="escc", 648 .version_id = 2, 649 .minimum_version_id = 1, 650 .fields = (VMStateField[]) { 651 VMSTATE_STRUCT_ARRAY(chn, ESCCState, 2, 2, vmstate_escc_chn, 652 ESCCChannelState), 653 VMSTATE_END_OF_LIST() 654 } 655 }; 656 657 static void sunkbd_handle_event(DeviceState *dev, QemuConsole *src, 658 InputEvent *evt) 659 { 660 ESCCChannelState *s = (ESCCChannelState *)dev; 661 int qcode, keycode; 662 InputKeyEvent *key; 663 664 assert(evt->type == INPUT_EVENT_KIND_KEY); 665 key = evt->u.key.data; 666 qcode = qemu_input_key_value_to_qcode(key->key); 667 trace_escc_sunkbd_event_in(qcode, QKeyCode_str(qcode), 668 key->down); 669 670 if (qcode == Q_KEY_CODE_CAPS_LOCK) { 671 if (key->down) { 672 s->caps_lock_mode ^= 1; 673 if (s->caps_lock_mode == 2) { 674 return; /* Drop second press */ 675 } 676 } else { 677 s->caps_lock_mode ^= 2; 678 if (s->caps_lock_mode == 3) { 679 return; /* Drop first release */ 680 } 681 } 682 } 683 684 if (qcode == Q_KEY_CODE_NUM_LOCK) { 685 if (key->down) { 686 s->num_lock_mode ^= 1; 687 if (s->num_lock_mode == 2) { 688 return; /* Drop second press */ 689 } 690 } else { 691 s->num_lock_mode ^= 2; 692 if (s->num_lock_mode == 3) { 693 return; /* Drop first release */ 694 } 695 } 696 } 697 698 if (qcode > qemu_input_map_qcode_to_sun_len) { 699 return; 700 } 701 702 keycode = qemu_input_map_qcode_to_sun[qcode]; 703 if (!key->down) { 704 keycode |= 0x80; 705 } 706 trace_escc_sunkbd_event_out(keycode); 707 put_queue(s, keycode); 708 } 709 710 static QemuInputHandler sunkbd_handler = { 711 .name = "sun keyboard", 712 .mask = INPUT_EVENT_MASK_KEY, 713 .event = sunkbd_handle_event, 714 }; 715 716 static void handle_kbd_command(ESCCChannelState *s, int val) 717 { 718 trace_escc_kbd_command(val); 719 if (s->led_mode) { // Ignore led byte 720 s->led_mode = 0; 721 return; 722 } 723 switch (val) { 724 case 1: // Reset, return type code 725 clear_queue(s); 726 put_queue(s, 0xff); 727 put_queue(s, 4); // Type 4 728 put_queue(s, 0x7f); 729 break; 730 case 0xe: // Set leds 731 s->led_mode = 1; 732 break; 733 case 7: // Query layout 734 case 0xf: 735 clear_queue(s); 736 put_queue(s, 0xfe); 737 put_queue(s, 0x21); /* en-us layout */ 738 break; 739 default: 740 break; 741 } 742 } 743 744 static void sunmouse_event(void *opaque, 745 int dx, int dy, int dz, int buttons_state) 746 { 747 ESCCChannelState *s = opaque; 748 int ch; 749 750 trace_escc_sunmouse_event(dx, dy, buttons_state); 751 ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */ 752 753 if (buttons_state & MOUSE_EVENT_LBUTTON) 754 ch ^= 0x4; 755 if (buttons_state & MOUSE_EVENT_MBUTTON) 756 ch ^= 0x2; 757 if (buttons_state & MOUSE_EVENT_RBUTTON) 758 ch ^= 0x1; 759 760 put_queue(s, ch); 761 762 ch = dx; 763 764 if (ch > 127) 765 ch = 127; 766 else if (ch < -127) 767 ch = -127; 768 769 put_queue(s, ch & 0xff); 770 771 ch = -dy; 772 773 if (ch > 127) 774 ch = 127; 775 else if (ch < -127) 776 ch = -127; 777 778 put_queue(s, ch & 0xff); 779 780 // MSC protocol specify two extra motion bytes 781 782 put_queue(s, 0); 783 put_queue(s, 0); 784 } 785 786 static void escc_init1(Object *obj) 787 { 788 ESCCState *s = ESCC(obj); 789 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 790 unsigned int i; 791 792 for (i = 0; i < 2; i++) { 793 sysbus_init_irq(dev, &s->chn[i].irq); 794 s->chn[i].chn = 1 - i; 795 } 796 s->chn[0].otherchn = &s->chn[1]; 797 s->chn[1].otherchn = &s->chn[0]; 798 799 sysbus_init_mmio(dev, &s->mmio); 800 } 801 802 static void escc_realize(DeviceState *dev, Error **errp) 803 { 804 ESCCState *s = ESCC(dev); 805 unsigned int i; 806 807 s->chn[0].disabled = s->disabled; 808 s->chn[1].disabled = s->disabled; 809 810 memory_region_init_io(&s->mmio, OBJECT(dev), &escc_mem_ops, s, "escc", 811 ESCC_SIZE << s->it_shift); 812 813 for (i = 0; i < 2; i++) { 814 if (qemu_chr_fe_backend_connected(&s->chn[i].chr)) { 815 s->chn[i].clock = s->frequency / 2; 816 qemu_chr_fe_set_handlers(&s->chn[i].chr, serial_can_receive, 817 serial_receive1, serial_event, NULL, 818 &s->chn[i], NULL, true); 819 } 820 } 821 822 if (s->chn[0].type == escc_mouse) { 823 qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, 824 "QEMU Sun Mouse"); 825 } 826 if (s->chn[1].type == escc_kbd) { 827 s->chn[1].hs = qemu_input_handler_register((DeviceState *)(&s->chn[1]), 828 &sunkbd_handler); 829 } 830 } 831 832 static Property escc_properties[] = { 833 DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0), 834 DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0), 835 DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0), 836 DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0), 837 DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0), 838 DEFINE_PROP_CHR("chrB", ESCCState, chn[0].chr), 839 DEFINE_PROP_CHR("chrA", ESCCState, chn[1].chr), 840 DEFINE_PROP_END_OF_LIST(), 841 }; 842 843 static void escc_class_init(ObjectClass *klass, void *data) 844 { 845 DeviceClass *dc = DEVICE_CLASS(klass); 846 847 dc->reset = escc_reset; 848 dc->realize = escc_realize; 849 dc->vmsd = &vmstate_escc; 850 dc->props = escc_properties; 851 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 852 } 853 854 static const TypeInfo escc_info = { 855 .name = TYPE_ESCC, 856 .parent = TYPE_SYS_BUS_DEVICE, 857 .instance_size = sizeof(ESCCState), 858 .instance_init = escc_init1, 859 .class_init = escc_class_init, 860 }; 861 862 static void escc_register_types(void) 863 { 864 type_register_static(&escc_info); 865 } 866 867 type_init(escc_register_types) 868