1 /* 2 * QEMU model of the Canon DIGIC UART block. 3 * 4 * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com> 5 * 6 * This model is based on reverse engineering efforts 7 * made by CHDK (http://chdk.wikia.com) and 8 * Magic Lantern (http://www.magiclantern.fm) projects 9 * contributors. 10 * 11 * See "Serial terminal" docs here: 12 * http://magiclantern.wikia.com/wiki/Register_Map#Misc_Registers 13 * 14 * The QEMU model of the Milkymist UART block by Michael Walle 15 * is used as a template. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License as published by 19 * the Free Software Foundation; either version 2 of the License, or 20 * (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 */ 28 29 #include "qemu/osdep.h" 30 #include "hw/hw.h" 31 #include "hw/sysbus.h" 32 #include "sysemu/char.h" 33 #include "qemu/log.h" 34 35 #include "hw/char/digic-uart.h" 36 37 enum { 38 ST_RX_RDY = (1 << 0), 39 ST_TX_RDY = (1 << 1), 40 }; 41 42 static uint64_t digic_uart_read(void *opaque, hwaddr addr, 43 unsigned size) 44 { 45 DigicUartState *s = opaque; 46 uint64_t ret = 0; 47 48 addr >>= 2; 49 50 switch (addr) { 51 case R_RX: 52 s->reg_st &= ~(ST_RX_RDY); 53 ret = s->reg_rx; 54 break; 55 56 case R_ST: 57 ret = s->reg_st; 58 break; 59 60 default: 61 qemu_log_mask(LOG_UNIMP, 62 "digic-uart: read access to unknown register 0x" 63 TARGET_FMT_plx, addr << 2); 64 } 65 66 return ret; 67 } 68 69 static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value, 70 unsigned size) 71 { 72 DigicUartState *s = opaque; 73 unsigned char ch = value; 74 75 addr >>= 2; 76 77 switch (addr) { 78 case R_TX: 79 /* XXX this blocks entire thread. Rewrite to use 80 * qemu_chr_fe_write and background I/O callbacks */ 81 qemu_chr_fe_write_all(&s->chr, &ch, 1); 82 break; 83 84 case R_ST: 85 /* 86 * Ignore write to R_ST. 87 * 88 * The point is that this register is actively used 89 * during receiving and transmitting symbols, 90 * but we don't know the function of most of bits. 91 * 92 * Ignoring writes to R_ST is only a simplification 93 * of the model. It has no perceptible side effects 94 * for existing guests. 95 */ 96 break; 97 98 default: 99 qemu_log_mask(LOG_UNIMP, 100 "digic-uart: write access to unknown register 0x" 101 TARGET_FMT_plx, addr << 2); 102 } 103 } 104 105 static const MemoryRegionOps uart_mmio_ops = { 106 .read = digic_uart_read, 107 .write = digic_uart_write, 108 .valid = { 109 .min_access_size = 4, 110 .max_access_size = 4, 111 }, 112 .endianness = DEVICE_NATIVE_ENDIAN, 113 }; 114 115 static int uart_can_rx(void *opaque) 116 { 117 DigicUartState *s = opaque; 118 119 return !(s->reg_st & ST_RX_RDY); 120 } 121 122 static void uart_rx(void *opaque, const uint8_t *buf, int size) 123 { 124 DigicUartState *s = opaque; 125 126 assert(uart_can_rx(opaque)); 127 128 s->reg_st |= ST_RX_RDY; 129 s->reg_rx = *buf; 130 } 131 132 static void uart_event(void *opaque, int event) 133 { 134 } 135 136 static void digic_uart_reset(DeviceState *d) 137 { 138 DigicUartState *s = DIGIC_UART(d); 139 140 s->reg_rx = 0; 141 s->reg_st = ST_TX_RDY; 142 } 143 144 static void digic_uart_realize(DeviceState *dev, Error **errp) 145 { 146 DigicUartState *s = DIGIC_UART(dev); 147 148 qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, 149 uart_event, s, NULL, true); 150 } 151 152 static void digic_uart_init(Object *obj) 153 { 154 DigicUartState *s = DIGIC_UART(obj); 155 156 memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s, 157 TYPE_DIGIC_UART, 0x18); 158 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->regs_region); 159 } 160 161 static const VMStateDescription vmstate_digic_uart = { 162 .name = "digic-uart", 163 .version_id = 1, 164 .minimum_version_id = 1, 165 .fields = (VMStateField[]) { 166 VMSTATE_UINT32(reg_rx, DigicUartState), 167 VMSTATE_UINT32(reg_st, DigicUartState), 168 VMSTATE_END_OF_LIST() 169 } 170 }; 171 172 static Property digic_uart_properties[] = { 173 DEFINE_PROP_CHR("chardev", DigicUartState, chr), 174 DEFINE_PROP_END_OF_LIST(), 175 }; 176 177 static void digic_uart_class_init(ObjectClass *klass, void *data) 178 { 179 DeviceClass *dc = DEVICE_CLASS(klass); 180 181 dc->realize = digic_uart_realize; 182 dc->reset = digic_uart_reset; 183 dc->vmsd = &vmstate_digic_uart; 184 dc->props = digic_uart_properties; 185 } 186 187 static const TypeInfo digic_uart_info = { 188 .name = TYPE_DIGIC_UART, 189 .parent = TYPE_SYS_BUS_DEVICE, 190 .instance_size = sizeof(DigicUartState), 191 .instance_init = digic_uart_init, 192 .class_init = digic_uart_class_init, 193 }; 194 195 static void digic_uart_register_types(void) 196 { 197 type_register_static(&digic_uart_info); 198 } 199 200 type_init(digic_uart_register_types) 201