xref: /openbmc/qemu/hw/char/digic-uart.c (revision 500eb6db)
1 /*
2  * QEMU model of the Canon DIGIC UART block.
3  *
4  * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
5  *
6  * This model is based on reverse engineering efforts
7  * made by CHDK (http://chdk.wikia.com) and
8  * Magic Lantern (http://www.magiclantern.fm) projects
9  * contributors.
10  *
11  * See "Serial terminal" docs here:
12  *   http://magiclantern.wikia.com/wiki/Register_Map#Misc_Registers
13  *
14  * The QEMU model of the Milkymist UART block by Michael Walle
15  * is used as a template.
16  *
17  * This program is free software; you can redistribute it and/or modify
18  * it under the terms of the GNU General Public License as published by
19  * the Free Software Foundation; either version 2 of the License, or
20  * (at your option) any later version.
21  *
22  * This program is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25  * GNU General Public License for more details.
26  *
27  */
28 
29 #include "qemu/osdep.h"
30 #include "hw/hw.h"
31 #include "hw/sysbus.h"
32 #include "chardev/char-fe.h"
33 #include "qemu/log.h"
34 #include "qemu/module.h"
35 
36 #include "hw/char/digic-uart.h"
37 
38 enum {
39     ST_RX_RDY = (1 << 0),
40     ST_TX_RDY = (1 << 1),
41 };
42 
43 static uint64_t digic_uart_read(void *opaque, hwaddr addr,
44                                 unsigned size)
45 {
46     DigicUartState *s = opaque;
47     uint64_t ret = 0;
48 
49     addr >>= 2;
50 
51     switch (addr) {
52     case R_RX:
53         s->reg_st &= ~(ST_RX_RDY);
54         ret = s->reg_rx;
55         break;
56 
57     case R_ST:
58         ret = s->reg_st;
59         break;
60 
61     default:
62         qemu_log_mask(LOG_UNIMP,
63                       "digic-uart: read access to unknown register 0x"
64                       TARGET_FMT_plx "\n", addr << 2);
65     }
66 
67     return ret;
68 }
69 
70 static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,
71                              unsigned size)
72 {
73     DigicUartState *s = opaque;
74     unsigned char ch = value;
75 
76     addr >>= 2;
77 
78     switch (addr) {
79     case R_TX:
80         /* XXX this blocks entire thread. Rewrite to use
81          * qemu_chr_fe_write and background I/O callbacks */
82         qemu_chr_fe_write_all(&s->chr, &ch, 1);
83         break;
84 
85     case R_ST:
86         /*
87          * Ignore write to R_ST.
88          *
89          * The point is that this register is actively used
90          * during receiving and transmitting symbols,
91          * but we don't know the function of most of bits.
92          *
93          * Ignoring writes to R_ST is only a simplification
94          * of the model. It has no perceptible side effects
95          * for existing guests.
96          */
97         break;
98 
99     default:
100         qemu_log_mask(LOG_UNIMP,
101                       "digic-uart: write access to unknown register 0x"
102                       TARGET_FMT_plx "\n", addr << 2);
103     }
104 }
105 
106 static const MemoryRegionOps uart_mmio_ops = {
107     .read = digic_uart_read,
108     .write = digic_uart_write,
109     .valid = {
110         .min_access_size = 4,
111         .max_access_size = 4,
112     },
113     .endianness = DEVICE_NATIVE_ENDIAN,
114 };
115 
116 static int uart_can_rx(void *opaque)
117 {
118     DigicUartState *s = opaque;
119 
120     return !(s->reg_st & ST_RX_RDY);
121 }
122 
123 static void uart_rx(void *opaque, const uint8_t *buf, int size)
124 {
125     DigicUartState *s = opaque;
126 
127     assert(uart_can_rx(opaque));
128 
129     s->reg_st |= ST_RX_RDY;
130     s->reg_rx = *buf;
131 }
132 
133 static void uart_event(void *opaque, int event)
134 {
135 }
136 
137 static void digic_uart_reset(DeviceState *d)
138 {
139     DigicUartState *s = DIGIC_UART(d);
140 
141     s->reg_rx = 0;
142     s->reg_st = ST_TX_RDY;
143 }
144 
145 static void digic_uart_realize(DeviceState *dev, Error **errp)
146 {
147     DigicUartState *s = DIGIC_UART(dev);
148 
149     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
150                              uart_event, NULL, s, NULL, true);
151 }
152 
153 static void digic_uart_init(Object *obj)
154 {
155     DigicUartState *s = DIGIC_UART(obj);
156 
157     memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
158                           TYPE_DIGIC_UART, 0x18);
159     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->regs_region);
160 }
161 
162 static const VMStateDescription vmstate_digic_uart = {
163     .name = "digic-uart",
164     .version_id = 1,
165     .minimum_version_id = 1,
166     .fields = (VMStateField[]) {
167         VMSTATE_UINT32(reg_rx, DigicUartState),
168         VMSTATE_UINT32(reg_st, DigicUartState),
169         VMSTATE_END_OF_LIST()
170     }
171 };
172 
173 static Property digic_uart_properties[] = {
174     DEFINE_PROP_CHR("chardev", DigicUartState, chr),
175     DEFINE_PROP_END_OF_LIST(),
176 };
177 
178 static void digic_uart_class_init(ObjectClass *klass, void *data)
179 {
180     DeviceClass *dc = DEVICE_CLASS(klass);
181 
182     dc->realize = digic_uart_realize;
183     dc->reset = digic_uart_reset;
184     dc->vmsd = &vmstate_digic_uart;
185     dc->props = digic_uart_properties;
186 }
187 
188 static const TypeInfo digic_uart_info = {
189     .name = TYPE_DIGIC_UART,
190     .parent = TYPE_SYS_BUS_DEVICE,
191     .instance_size = sizeof(DigicUartState),
192     .instance_init = digic_uart_init,
193     .class_init = digic_uart_class_init,
194 };
195 
196 static void digic_uart_register_types(void)
197 {
198     type_register_static(&digic_uart_info);
199 }
200 
201 type_init(digic_uart_register_types)
202