xref: /openbmc/qemu/hw/char/debugcon.c (revision a68694cd)
1 /*
2  * QEMU Bochs-style debug console ("port E9") emulation
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  * Copyright (c) 2008 Citrix Systems, Inc.
6  * Copyright (c) Intel Corporation; author: H. Peter Anvin
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  */
26 
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qemu/module.h"
30 #include "chardev/char-fe.h"
31 #include "hw/isa/isa.h"
32 #include "hw/qdev-properties.h"
33 #include "qom/object.h"
34 
35 #define TYPE_ISA_DEBUGCON_DEVICE "isa-debugcon"
36 typedef struct ISADebugconState ISADebugconState;
37 DECLARE_INSTANCE_CHECKER(ISADebugconState, ISA_DEBUGCON_DEVICE,
38                          TYPE_ISA_DEBUGCON_DEVICE)
39 
40 //#define DEBUG_DEBUGCON
41 
42 typedef struct DebugconState {
43     MemoryRegion io;
44     CharBackend chr;
45     uint32_t readback;
46 } DebugconState;
47 
48 struct ISADebugconState {
49     ISADevice parent_obj;
50 
51     uint32_t iobase;
52     DebugconState state;
53 };
54 
55 static void debugcon_ioport_write(void *opaque, hwaddr addr, uint64_t val,
56                                   unsigned width)
57 {
58     DebugconState *s = opaque;
59     unsigned char ch = val;
60 
61 #ifdef DEBUG_DEBUGCON
62     printf(" [debugcon: write addr=0x%04" HWADDR_PRIx " val=0x%02" PRIx64 "]\n", addr, val);
63 #endif
64 
65     /* XXX this blocks entire thread. Rewrite to use
66      * qemu_chr_fe_write and background I/O callbacks */
67     qemu_chr_fe_write_all(&s->chr, &ch, 1);
68 }
69 
70 
71 static uint64_t debugcon_ioport_read(void *opaque, hwaddr addr, unsigned width)
72 {
73     DebugconState *s = opaque;
74 
75 #ifdef DEBUG_DEBUGCON
76     printf("debugcon: read addr=0x%04" HWADDR_PRIx "\n", addr);
77 #endif
78 
79     return s->readback;
80 }
81 
82 static const MemoryRegionOps debugcon_ops = {
83     .read = debugcon_ioport_read,
84     .write = debugcon_ioport_write,
85     .valid.min_access_size = 1,
86     .valid.max_access_size = 1,
87     .endianness = DEVICE_LITTLE_ENDIAN,
88 };
89 
90 static void debugcon_realize_core(DebugconState *s, Error **errp)
91 {
92     if (!qemu_chr_fe_backend_connected(&s->chr)) {
93         error_setg(errp, "Can't create debugcon device, empty char device");
94         return;
95     }
96 
97     qemu_chr_fe_set_handlers(&s->chr, NULL, NULL, NULL, NULL, s, NULL, true);
98 }
99 
100 static void debugcon_isa_realizefn(DeviceState *dev, Error **errp)
101 {
102     ISADevice *d = ISA_DEVICE(dev);
103     ISADebugconState *isa = ISA_DEBUGCON_DEVICE(dev);
104     DebugconState *s = &isa->state;
105     Error *err = NULL;
106 
107     debugcon_realize_core(s, &err);
108     if (err != NULL) {
109         error_propagate(errp, err);
110         return;
111     }
112     memory_region_init_io(&s->io, OBJECT(dev), &debugcon_ops, s,
113                           TYPE_ISA_DEBUGCON_DEVICE, 1);
114     memory_region_add_subregion(isa_address_space_io(d),
115                                 isa->iobase, &s->io);
116 }
117 
118 static Property debugcon_isa_properties[] = {
119     DEFINE_PROP_UINT32("iobase", ISADebugconState, iobase, 0xe9),
120     DEFINE_PROP_CHR("chardev",  ISADebugconState, state.chr),
121     DEFINE_PROP_UINT32("readback", ISADebugconState, state.readback, 0xe9),
122     DEFINE_PROP_END_OF_LIST(),
123 };
124 
125 static void debugcon_isa_class_initfn(ObjectClass *klass, void *data)
126 {
127     DeviceClass *dc = DEVICE_CLASS(klass);
128 
129     dc->realize = debugcon_isa_realizefn;
130     device_class_set_props(dc, debugcon_isa_properties);
131     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
132 }
133 
134 static const TypeInfo debugcon_isa_info = {
135     .name          = TYPE_ISA_DEBUGCON_DEVICE,
136     .parent        = TYPE_ISA_DEVICE,
137     .instance_size = sizeof(ISADebugconState),
138     .class_init    = debugcon_isa_class_initfn,
139 };
140 
141 static void debugcon_register_types(void)
142 {
143     type_register_static(&debugcon_isa_info);
144 }
145 
146 type_init(debugcon_register_types)
147