1 /* 2 * ARM CMSDK APB UART emulation 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the "APB UART" which is part of the Cortex-M 13 * System Design Kit (CMSDK) and documented in the Cortex-M System 14 * Design Kit Technical Reference Manual (ARM DDI0479C): 15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qemu/module.h" 21 #include "qapi/error.h" 22 #include "trace.h" 23 #include "hw/sysbus.h" 24 #include "hw/registerfields.h" 25 #include "chardev/char-fe.h" 26 #include "chardev/char-serial.h" 27 #include "hw/char/cmsdk-apb-uart.h" 28 #include "hw/irq.h" 29 30 REG32(DATA, 0) 31 REG32(STATE, 4) 32 FIELD(STATE, TXFULL, 0, 1) 33 FIELD(STATE, RXFULL, 1, 1) 34 FIELD(STATE, TXOVERRUN, 2, 1) 35 FIELD(STATE, RXOVERRUN, 3, 1) 36 REG32(CTRL, 8) 37 FIELD(CTRL, TX_EN, 0, 1) 38 FIELD(CTRL, RX_EN, 1, 1) 39 FIELD(CTRL, TX_INTEN, 2, 1) 40 FIELD(CTRL, RX_INTEN, 3, 1) 41 FIELD(CTRL, TXO_INTEN, 4, 1) 42 FIELD(CTRL, RXO_INTEN, 5, 1) 43 FIELD(CTRL, HSTEST, 6, 1) 44 REG32(INTSTATUS, 0xc) 45 FIELD(INTSTATUS, TX, 0, 1) 46 FIELD(INTSTATUS, RX, 1, 1) 47 FIELD(INTSTATUS, TXO, 2, 1) 48 FIELD(INTSTATUS, RXO, 3, 1) 49 REG32(BAUDDIV, 0x10) 50 REG32(PID4, 0xFD0) 51 REG32(PID5, 0xFD4) 52 REG32(PID6, 0xFD8) 53 REG32(PID7, 0xFDC) 54 REG32(PID0, 0xFE0) 55 REG32(PID1, 0xFE4) 56 REG32(PID2, 0xFE8) 57 REG32(PID3, 0xFEC) 58 REG32(CID0, 0xFF0) 59 REG32(CID1, 0xFF4) 60 REG32(CID2, 0xFF8) 61 REG32(CID3, 0xFFC) 62 63 /* PID/CID values */ 64 static const int uart_id[] = { 65 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 66 0x21, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ 67 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 68 }; 69 70 static bool uart_baudrate_ok(CMSDKAPBUART *s) 71 { 72 /* The minimum permitted bauddiv setting is 16, so we just ignore 73 * settings below that (usually this means the device has just 74 * been reset and not yet programmed). 75 */ 76 return s->bauddiv >= 16 && s->bauddiv <= s->pclk_frq; 77 } 78 79 static void uart_update_parameters(CMSDKAPBUART *s) 80 { 81 QEMUSerialSetParams ssp; 82 83 /* This UART is always 8N1 but the baud rate is programmable. */ 84 if (!uart_baudrate_ok(s)) { 85 return; 86 } 87 88 ssp.data_bits = 8; 89 ssp.parity = 'N'; 90 ssp.stop_bits = 1; 91 ssp.speed = s->pclk_frq / s->bauddiv; 92 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 93 trace_cmsdk_apb_uart_set_params(ssp.speed); 94 } 95 96 static void cmsdk_apb_uart_update(CMSDKAPBUART *s) 97 { 98 /* update outbound irqs, including handling the way the rxo and txo 99 * interrupt status bits are just logical AND of the overrun bit in 100 * STATE and the overrun interrupt enable bit in CTRL. 101 */ 102 uint32_t omask = (R_INTSTATUS_RXO_MASK | R_INTSTATUS_TXO_MASK); 103 s->intstatus &= ~omask; 104 s->intstatus |= (s->state & (s->ctrl >> 2) & omask); 105 106 qemu_set_irq(s->txint, !!(s->intstatus & R_INTSTATUS_TX_MASK)); 107 qemu_set_irq(s->rxint, !!(s->intstatus & R_INTSTATUS_RX_MASK)); 108 qemu_set_irq(s->txovrint, !!(s->intstatus & R_INTSTATUS_TXO_MASK)); 109 qemu_set_irq(s->rxovrint, !!(s->intstatus & R_INTSTATUS_RXO_MASK)); 110 qemu_set_irq(s->uartint, !!(s->intstatus)); 111 } 112 113 static int uart_can_receive(void *opaque) 114 { 115 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 116 117 /* We can take a char if RX is enabled and the buffer is empty */ 118 if (s->ctrl & R_CTRL_RX_EN_MASK && !(s->state & R_STATE_RXFULL_MASK)) { 119 return 1; 120 } 121 return 0; 122 } 123 124 static void uart_receive(void *opaque, const uint8_t *buf, int size) 125 { 126 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 127 128 trace_cmsdk_apb_uart_receive(*buf); 129 130 /* In fact uart_can_receive() ensures that we can't be 131 * called unless RX is enabled and the buffer is empty, 132 * but we include this logic as documentation of what the 133 * hardware does if a character arrives in these circumstances. 134 */ 135 if (!(s->ctrl & R_CTRL_RX_EN_MASK)) { 136 /* Just drop the character on the floor */ 137 return; 138 } 139 140 if (s->state & R_STATE_RXFULL_MASK) { 141 s->state |= R_STATE_RXOVERRUN_MASK; 142 } 143 144 s->rxbuf = *buf; 145 s->state |= R_STATE_RXFULL_MASK; 146 if (s->ctrl & R_CTRL_RX_INTEN_MASK) { 147 s->intstatus |= R_INTSTATUS_RX_MASK; 148 } 149 cmsdk_apb_uart_update(s); 150 } 151 152 static uint64_t uart_read(void *opaque, hwaddr offset, unsigned size) 153 { 154 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 155 uint64_t r; 156 157 switch (offset) { 158 case A_DATA: 159 r = s->rxbuf; 160 s->state &= ~R_STATE_RXFULL_MASK; 161 cmsdk_apb_uart_update(s); 162 qemu_chr_fe_accept_input(&s->chr); 163 break; 164 case A_STATE: 165 r = s->state; 166 break; 167 case A_CTRL: 168 r = s->ctrl; 169 break; 170 case A_INTSTATUS: 171 r = s->intstatus; 172 break; 173 case A_BAUDDIV: 174 r = s->bauddiv; 175 break; 176 case A_PID4 ... A_CID3: 177 r = uart_id[(offset - A_PID4) / 4]; 178 break; 179 default: 180 qemu_log_mask(LOG_GUEST_ERROR, 181 "CMSDK APB UART read: bad offset %x\n", (int) offset); 182 r = 0; 183 break; 184 } 185 trace_cmsdk_apb_uart_read(offset, r, size); 186 return r; 187 } 188 189 /* Try to send tx data, and arrange to be called back later if 190 * we can't (ie the char backend is busy/blocking). 191 */ 192 static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque) 193 { 194 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 195 int ret; 196 197 s->watch_tag = 0; 198 199 if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK)) { 200 return FALSE; 201 } 202 203 ret = qemu_chr_fe_write(&s->chr, &s->txbuf, 1); 204 if (ret <= 0) { 205 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 206 uart_transmit, s); 207 if (!s->watch_tag) { 208 /* Most common reason to be here is "no chardev backend": 209 * just insta-drain the buffer, so the serial output 210 * goes into a void, rather than blocking the guest. 211 */ 212 goto buffer_drained; 213 } 214 /* Transmit pending */ 215 trace_cmsdk_apb_uart_tx_pending(); 216 return FALSE; 217 } 218 219 buffer_drained: 220 /* Character successfully sent */ 221 trace_cmsdk_apb_uart_tx(s->txbuf); 222 s->state &= ~R_STATE_TXFULL_MASK; 223 /* Going from TXFULL set to clear triggers the tx interrupt */ 224 if (s->ctrl & R_CTRL_TX_INTEN_MASK) { 225 s->intstatus |= R_INTSTATUS_TX_MASK; 226 } 227 cmsdk_apb_uart_update(s); 228 return FALSE; 229 } 230 231 static void uart_cancel_transmit(CMSDKAPBUART *s) 232 { 233 if (s->watch_tag) { 234 g_source_remove(s->watch_tag); 235 s->watch_tag = 0; 236 } 237 } 238 239 static void uart_write(void *opaque, hwaddr offset, uint64_t value, 240 unsigned size) 241 { 242 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 243 244 trace_cmsdk_apb_uart_write(offset, value, size); 245 246 switch (offset) { 247 case A_DATA: 248 s->txbuf = value; 249 if (s->state & R_STATE_TXFULL_MASK) { 250 /* Buffer already full -- note the overrun and let the 251 * existing pending transmit callback handle the new char. 252 */ 253 s->state |= R_STATE_TXOVERRUN_MASK; 254 cmsdk_apb_uart_update(s); 255 } else { 256 s->state |= R_STATE_TXFULL_MASK; 257 uart_transmit(NULL, G_IO_OUT, s); 258 } 259 break; 260 case A_STATE: 261 /* Bits 0 and 1 are read only; bits 2 and 3 are W1C */ 262 s->state &= ~(value & 263 (R_STATE_TXOVERRUN_MASK | R_STATE_RXOVERRUN_MASK)); 264 cmsdk_apb_uart_update(s); 265 break; 266 case A_CTRL: 267 s->ctrl = value & 0x7f; 268 if ((s->ctrl & R_CTRL_TX_EN_MASK) && !uart_baudrate_ok(s)) { 269 qemu_log_mask(LOG_GUEST_ERROR, 270 "CMSDK APB UART: Tx enabled with invalid baudrate\n"); 271 } 272 cmsdk_apb_uart_update(s); 273 break; 274 case A_INTSTATUS: 275 /* All bits are W1C. Clearing the overrun interrupt bits really 276 * clears the overrun status bits in the STATE register (which 277 * is then reflected into the intstatus value by the update function). 278 */ 279 s->state &= ~(value & (R_INTSTATUS_TXO_MASK | R_INTSTATUS_RXO_MASK)); 280 s->intstatus &= ~value; 281 cmsdk_apb_uart_update(s); 282 break; 283 case A_BAUDDIV: 284 s->bauddiv = value & 0xFFFFF; 285 uart_update_parameters(s); 286 break; 287 case A_PID4 ... A_CID3: 288 qemu_log_mask(LOG_GUEST_ERROR, 289 "CMSDK APB UART write: write to RO offset 0x%x\n", 290 (int)offset); 291 break; 292 default: 293 qemu_log_mask(LOG_GUEST_ERROR, 294 "CMSDK APB UART write: bad offset 0x%x\n", (int) offset); 295 break; 296 } 297 } 298 299 static const MemoryRegionOps uart_ops = { 300 .read = uart_read, 301 .write = uart_write, 302 .endianness = DEVICE_LITTLE_ENDIAN, 303 }; 304 305 static void cmsdk_apb_uart_reset(DeviceState *dev) 306 { 307 CMSDKAPBUART *s = CMSDK_APB_UART(dev); 308 309 trace_cmsdk_apb_uart_reset(); 310 uart_cancel_transmit(s); 311 s->state = 0; 312 s->ctrl = 0; 313 s->intstatus = 0; 314 s->bauddiv = 0; 315 s->txbuf = 0; 316 s->rxbuf = 0; 317 } 318 319 static void cmsdk_apb_uart_init(Object *obj) 320 { 321 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 322 CMSDKAPBUART *s = CMSDK_APB_UART(obj); 323 324 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); 325 sysbus_init_mmio(sbd, &s->iomem); 326 sysbus_init_irq(sbd, &s->txint); 327 sysbus_init_irq(sbd, &s->rxint); 328 sysbus_init_irq(sbd, &s->txovrint); 329 sysbus_init_irq(sbd, &s->rxovrint); 330 sysbus_init_irq(sbd, &s->uartint); 331 } 332 333 static void cmsdk_apb_uart_realize(DeviceState *dev, Error **errp) 334 { 335 CMSDKAPBUART *s = CMSDK_APB_UART(dev); 336 337 if (s->pclk_frq == 0) { 338 error_setg(errp, "CMSDK APB UART: pclk-frq property must be set"); 339 return; 340 } 341 342 /* This UART has no flow control, so we do not need to register 343 * an event handler to deal with CHR_EVENT_BREAK. 344 */ 345 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, 346 NULL, NULL, s, NULL, true); 347 } 348 349 static int cmsdk_apb_uart_post_load(void *opaque, int version_id) 350 { 351 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 352 353 /* If we have a pending character, arrange to resend it. */ 354 if (s->state & R_STATE_TXFULL_MASK) { 355 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 356 uart_transmit, s); 357 } 358 uart_update_parameters(s); 359 return 0; 360 } 361 362 static const VMStateDescription cmsdk_apb_uart_vmstate = { 363 .name = "cmsdk-apb-uart", 364 .version_id = 1, 365 .minimum_version_id = 1, 366 .post_load = cmsdk_apb_uart_post_load, 367 .fields = (VMStateField[]) { 368 VMSTATE_UINT32(state, CMSDKAPBUART), 369 VMSTATE_UINT32(ctrl, CMSDKAPBUART), 370 VMSTATE_UINT32(intstatus, CMSDKAPBUART), 371 VMSTATE_UINT32(bauddiv, CMSDKAPBUART), 372 VMSTATE_UINT8(txbuf, CMSDKAPBUART), 373 VMSTATE_UINT8(rxbuf, CMSDKAPBUART), 374 VMSTATE_END_OF_LIST() 375 } 376 }; 377 378 static Property cmsdk_apb_uart_properties[] = { 379 DEFINE_PROP_CHR("chardev", CMSDKAPBUART, chr), 380 DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBUART, pclk_frq, 0), 381 DEFINE_PROP_END_OF_LIST(), 382 }; 383 384 static void cmsdk_apb_uart_class_init(ObjectClass *klass, void *data) 385 { 386 DeviceClass *dc = DEVICE_CLASS(klass); 387 388 dc->realize = cmsdk_apb_uart_realize; 389 dc->vmsd = &cmsdk_apb_uart_vmstate; 390 dc->reset = cmsdk_apb_uart_reset; 391 dc->props = cmsdk_apb_uart_properties; 392 } 393 394 static const TypeInfo cmsdk_apb_uart_info = { 395 .name = TYPE_CMSDK_APB_UART, 396 .parent = TYPE_SYS_BUS_DEVICE, 397 .instance_size = sizeof(CMSDKAPBUART), 398 .instance_init = cmsdk_apb_uart_init, 399 .class_init = cmsdk_apb_uart_class_init, 400 }; 401 402 static void cmsdk_apb_uart_register_types(void) 403 { 404 type_register_static(&cmsdk_apb_uart_info); 405 } 406 407 type_init(cmsdk_apb_uart_register_types); 408