1 /* 2 * ARM CMSDK APB UART emulation 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the "APB UART" which is part of the Cortex-M 13 * System Design Kit (CMSDK) and documented in the Cortex-M System 14 * Design Kit Technical Reference Manual (ARM DDI0479C): 15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 #include "hw/sysbus.h" 23 #include "hw/registerfields.h" 24 #include "chardev/char-fe.h" 25 #include "chardev/char-serial.h" 26 #include "hw/char/cmsdk-apb-uart.h" 27 28 REG32(DATA, 0) 29 REG32(STATE, 4) 30 FIELD(STATE, TXFULL, 0, 1) 31 FIELD(STATE, RXFULL, 1, 1) 32 FIELD(STATE, TXOVERRUN, 2, 1) 33 FIELD(STATE, RXOVERRUN, 3, 1) 34 REG32(CTRL, 8) 35 FIELD(CTRL, TX_EN, 0, 1) 36 FIELD(CTRL, RX_EN, 1, 1) 37 FIELD(CTRL, TX_INTEN, 2, 1) 38 FIELD(CTRL, RX_INTEN, 3, 1) 39 FIELD(CTRL, TXO_INTEN, 4, 1) 40 FIELD(CTRL, RXO_INTEN, 5, 1) 41 FIELD(CTRL, HSTEST, 6, 1) 42 REG32(INTSTATUS, 0xc) 43 FIELD(INTSTATUS, TX, 0, 1) 44 FIELD(INTSTATUS, RX, 1, 1) 45 FIELD(INTSTATUS, TXO, 2, 1) 46 FIELD(INTSTATUS, RXO, 3, 1) 47 REG32(BAUDDIV, 0x10) 48 REG32(PID4, 0xFD0) 49 REG32(PID5, 0xFD4) 50 REG32(PID6, 0xFD8) 51 REG32(PID7, 0xFDC) 52 REG32(PID0, 0xFE0) 53 REG32(PID1, 0xFE4) 54 REG32(PID2, 0xFE8) 55 REG32(PID3, 0xFEC) 56 REG32(CID0, 0xFF0) 57 REG32(CID1, 0xFF4) 58 REG32(CID2, 0xFF8) 59 REG32(CID3, 0xFFC) 60 61 /* PID/CID values */ 62 static const int uart_id[] = { 63 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 64 0x21, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ 65 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 66 }; 67 68 static bool uart_baudrate_ok(CMSDKAPBUART *s) 69 { 70 /* The minimum permitted bauddiv setting is 16, so we just ignore 71 * settings below that (usually this means the device has just 72 * been reset and not yet programmed). 73 */ 74 return s->bauddiv >= 16 && s->bauddiv <= s->pclk_frq; 75 } 76 77 static void uart_update_parameters(CMSDKAPBUART *s) 78 { 79 QEMUSerialSetParams ssp; 80 81 /* This UART is always 8N1 but the baud rate is programmable. */ 82 if (!uart_baudrate_ok(s)) { 83 return; 84 } 85 86 ssp.data_bits = 8; 87 ssp.parity = 'N'; 88 ssp.stop_bits = 1; 89 ssp.speed = s->pclk_frq / s->bauddiv; 90 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 91 trace_cmsdk_apb_uart_set_params(ssp.speed); 92 } 93 94 static void cmsdk_apb_uart_update(CMSDKAPBUART *s) 95 { 96 /* update outbound irqs, including handling the way the rxo and txo 97 * interrupt status bits are just logical AND of the overrun bit in 98 * STATE and the overrun interrupt enable bit in CTRL. 99 */ 100 uint32_t omask = (R_INTSTATUS_RXO_MASK | R_INTSTATUS_TXO_MASK); 101 s->intstatus &= ~omask; 102 s->intstatus |= (s->state & (s->ctrl >> 2) & omask); 103 104 qemu_set_irq(s->txint, !!(s->intstatus & R_INTSTATUS_TX_MASK)); 105 qemu_set_irq(s->rxint, !!(s->intstatus & R_INTSTATUS_RX_MASK)); 106 qemu_set_irq(s->txovrint, !!(s->intstatus & R_INTSTATUS_TXO_MASK)); 107 qemu_set_irq(s->rxovrint, !!(s->intstatus & R_INTSTATUS_RXO_MASK)); 108 qemu_set_irq(s->uartint, !!(s->intstatus)); 109 } 110 111 static int uart_can_receive(void *opaque) 112 { 113 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 114 115 /* We can take a char if RX is enabled and the buffer is empty */ 116 if (s->ctrl & R_CTRL_RX_EN_MASK && !(s->state & R_STATE_RXFULL_MASK)) { 117 return 1; 118 } 119 return 0; 120 } 121 122 static void uart_receive(void *opaque, const uint8_t *buf, int size) 123 { 124 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 125 126 trace_cmsdk_apb_uart_receive(*buf); 127 128 /* In fact uart_can_receive() ensures that we can't be 129 * called unless RX is enabled and the buffer is empty, 130 * but we include this logic as documentation of what the 131 * hardware does if a character arrives in these circumstances. 132 */ 133 if (!(s->ctrl & R_CTRL_RX_EN_MASK)) { 134 /* Just drop the character on the floor */ 135 return; 136 } 137 138 if (s->state & R_STATE_RXFULL_MASK) { 139 s->state |= R_STATE_RXOVERRUN_MASK; 140 } 141 142 s->rxbuf = *buf; 143 s->state |= R_STATE_RXFULL_MASK; 144 if (s->ctrl & R_CTRL_RX_INTEN_MASK) { 145 s->intstatus |= R_INTSTATUS_RX_MASK; 146 } 147 cmsdk_apb_uart_update(s); 148 } 149 150 static uint64_t uart_read(void *opaque, hwaddr offset, unsigned size) 151 { 152 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 153 uint64_t r; 154 155 switch (offset) { 156 case A_DATA: 157 r = s->rxbuf; 158 s->state &= ~R_STATE_RXFULL_MASK; 159 cmsdk_apb_uart_update(s); 160 qemu_chr_fe_accept_input(&s->chr); 161 break; 162 case A_STATE: 163 r = s->state; 164 break; 165 case A_CTRL: 166 r = s->ctrl; 167 break; 168 case A_INTSTATUS: 169 r = s->intstatus; 170 break; 171 case A_BAUDDIV: 172 r = s->bauddiv; 173 break; 174 case A_PID4 ... A_CID3: 175 r = uart_id[(offset - A_PID4) / 4]; 176 break; 177 default: 178 qemu_log_mask(LOG_GUEST_ERROR, 179 "CMSDK APB UART read: bad offset %x\n", (int) offset); 180 r = 0; 181 break; 182 } 183 trace_cmsdk_apb_uart_read(offset, r, size); 184 return r; 185 } 186 187 /* Try to send tx data, and arrange to be called back later if 188 * we can't (ie the char backend is busy/blocking). 189 */ 190 static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque) 191 { 192 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 193 int ret; 194 195 s->watch_tag = 0; 196 197 if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK)) { 198 return FALSE; 199 } 200 201 ret = qemu_chr_fe_write(&s->chr, &s->txbuf, 1); 202 if (ret <= 0) { 203 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 204 uart_transmit, s); 205 if (!s->watch_tag) { 206 /* Most common reason to be here is "no chardev backend": 207 * just insta-drain the buffer, so the serial output 208 * goes into a void, rather than blocking the guest. 209 */ 210 goto buffer_drained; 211 } 212 /* Transmit pending */ 213 trace_cmsdk_apb_uart_tx_pending(); 214 return FALSE; 215 } 216 217 buffer_drained: 218 /* Character successfully sent */ 219 trace_cmsdk_apb_uart_tx(s->txbuf); 220 s->state &= ~R_STATE_TXFULL_MASK; 221 /* Going from TXFULL set to clear triggers the tx interrupt */ 222 if (s->ctrl & R_CTRL_TX_INTEN_MASK) { 223 s->intstatus |= R_INTSTATUS_TX_MASK; 224 } 225 cmsdk_apb_uart_update(s); 226 return FALSE; 227 } 228 229 static void uart_cancel_transmit(CMSDKAPBUART *s) 230 { 231 if (s->watch_tag) { 232 g_source_remove(s->watch_tag); 233 s->watch_tag = 0; 234 } 235 } 236 237 static void uart_write(void *opaque, hwaddr offset, uint64_t value, 238 unsigned size) 239 { 240 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 241 242 trace_cmsdk_apb_uart_write(offset, value, size); 243 244 switch (offset) { 245 case A_DATA: 246 s->txbuf = value; 247 if (s->state & R_STATE_TXFULL_MASK) { 248 /* Buffer already full -- note the overrun and let the 249 * existing pending transmit callback handle the new char. 250 */ 251 s->state |= R_STATE_TXOVERRUN_MASK; 252 cmsdk_apb_uart_update(s); 253 } else { 254 s->state |= R_STATE_TXFULL_MASK; 255 uart_transmit(NULL, G_IO_OUT, s); 256 } 257 break; 258 case A_STATE: 259 /* Bits 0 and 1 are read only; bits 2 and 3 are W1C */ 260 s->state &= ~(value & 261 (R_STATE_TXOVERRUN_MASK | R_STATE_RXOVERRUN_MASK)); 262 cmsdk_apb_uart_update(s); 263 break; 264 case A_CTRL: 265 s->ctrl = value & 0x7f; 266 if ((s->ctrl & R_CTRL_TX_EN_MASK) && !uart_baudrate_ok(s)) { 267 qemu_log_mask(LOG_GUEST_ERROR, 268 "CMSDK APB UART: Tx enabled with invalid baudrate\n"); 269 } 270 cmsdk_apb_uart_update(s); 271 break; 272 case A_INTSTATUS: 273 /* All bits are W1C. Clearing the overrun interrupt bits really 274 * clears the overrun status bits in the STATE register (which 275 * is then reflected into the intstatus value by the update function). 276 */ 277 s->state &= ~(value & (R_INTSTATUS_TXO_MASK | R_INTSTATUS_RXO_MASK)); 278 s->intstatus &= ~value; 279 cmsdk_apb_uart_update(s); 280 break; 281 case A_BAUDDIV: 282 s->bauddiv = value & 0xFFFFF; 283 uart_update_parameters(s); 284 break; 285 case A_PID4 ... A_CID3: 286 qemu_log_mask(LOG_GUEST_ERROR, 287 "CMSDK APB UART write: write to RO offset 0x%x\n", 288 (int)offset); 289 break; 290 default: 291 qemu_log_mask(LOG_GUEST_ERROR, 292 "CMSDK APB UART write: bad offset 0x%x\n", (int) offset); 293 break; 294 } 295 } 296 297 static const MemoryRegionOps uart_ops = { 298 .read = uart_read, 299 .write = uart_write, 300 .endianness = DEVICE_LITTLE_ENDIAN, 301 }; 302 303 static void cmsdk_apb_uart_reset(DeviceState *dev) 304 { 305 CMSDKAPBUART *s = CMSDK_APB_UART(dev); 306 307 trace_cmsdk_apb_uart_reset(); 308 uart_cancel_transmit(s); 309 s->state = 0; 310 s->ctrl = 0; 311 s->intstatus = 0; 312 s->bauddiv = 0; 313 s->txbuf = 0; 314 s->rxbuf = 0; 315 } 316 317 static void cmsdk_apb_uart_init(Object *obj) 318 { 319 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 320 CMSDKAPBUART *s = CMSDK_APB_UART(obj); 321 322 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); 323 sysbus_init_mmio(sbd, &s->iomem); 324 sysbus_init_irq(sbd, &s->txint); 325 sysbus_init_irq(sbd, &s->rxint); 326 sysbus_init_irq(sbd, &s->txovrint); 327 sysbus_init_irq(sbd, &s->rxovrint); 328 sysbus_init_irq(sbd, &s->uartint); 329 } 330 331 static void cmsdk_apb_uart_realize(DeviceState *dev, Error **errp) 332 { 333 CMSDKAPBUART *s = CMSDK_APB_UART(dev); 334 335 if (s->pclk_frq == 0) { 336 error_setg(errp, "CMSDK APB UART: pclk-frq property must be set"); 337 return; 338 } 339 340 /* This UART has no flow control, so we do not need to register 341 * an event handler to deal with CHR_EVENT_BREAK. 342 */ 343 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, 344 NULL, NULL, s, NULL, true); 345 } 346 347 static int cmsdk_apb_uart_post_load(void *opaque, int version_id) 348 { 349 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 350 351 /* If we have a pending character, arrange to resend it. */ 352 if (s->state & R_STATE_TXFULL_MASK) { 353 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 354 uart_transmit, s); 355 } 356 uart_update_parameters(s); 357 return 0; 358 } 359 360 static const VMStateDescription cmsdk_apb_uart_vmstate = { 361 .name = "cmsdk-apb-uart", 362 .version_id = 1, 363 .minimum_version_id = 1, 364 .post_load = cmsdk_apb_uart_post_load, 365 .fields = (VMStateField[]) { 366 VMSTATE_UINT32(state, CMSDKAPBUART), 367 VMSTATE_UINT32(ctrl, CMSDKAPBUART), 368 VMSTATE_UINT32(intstatus, CMSDKAPBUART), 369 VMSTATE_UINT32(bauddiv, CMSDKAPBUART), 370 VMSTATE_UINT8(txbuf, CMSDKAPBUART), 371 VMSTATE_UINT8(rxbuf, CMSDKAPBUART), 372 VMSTATE_END_OF_LIST() 373 } 374 }; 375 376 static Property cmsdk_apb_uart_properties[] = { 377 DEFINE_PROP_CHR("chardev", CMSDKAPBUART, chr), 378 DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBUART, pclk_frq, 0), 379 DEFINE_PROP_END_OF_LIST(), 380 }; 381 382 static void cmsdk_apb_uart_class_init(ObjectClass *klass, void *data) 383 { 384 DeviceClass *dc = DEVICE_CLASS(klass); 385 386 dc->realize = cmsdk_apb_uart_realize; 387 dc->vmsd = &cmsdk_apb_uart_vmstate; 388 dc->reset = cmsdk_apb_uart_reset; 389 dc->props = cmsdk_apb_uart_properties; 390 } 391 392 static const TypeInfo cmsdk_apb_uart_info = { 393 .name = TYPE_CMSDK_APB_UART, 394 .parent = TYPE_SYS_BUS_DEVICE, 395 .instance_size = sizeof(CMSDKAPBUART), 396 .instance_init = cmsdk_apb_uart_init, 397 .class_init = cmsdk_apb_uart_class_init, 398 }; 399 400 static void cmsdk_apb_uart_register_types(void) 401 { 402 type_register_static(&cmsdk_apb_uart_info); 403 } 404 405 type_init(cmsdk_apb_uart_register_types); 406