1 /* 2 * ARM CMSDK APB UART emulation 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the "APB UART" which is part of the Cortex-M 13 * System Design Kit (CMSDK) and documented in the Cortex-M System 14 * Design Kit Technical Reference Manual (ARM DDI0479C): 15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 #include "hw/sysbus.h" 23 #include "hw/registerfields.h" 24 #include "chardev/char-fe.h" 25 #include "chardev/char-serial.h" 26 #include "hw/char/cmsdk-apb-uart.h" 27 28 REG32(DATA, 0) 29 REG32(STATE, 4) 30 FIELD(STATE, TXFULL, 0, 1) 31 FIELD(STATE, RXFULL, 1, 1) 32 FIELD(STATE, TXOVERRUN, 2, 1) 33 FIELD(STATE, RXOVERRUN, 3, 1) 34 REG32(CTRL, 8) 35 FIELD(CTRL, TX_EN, 0, 1) 36 FIELD(CTRL, RX_EN, 1, 1) 37 FIELD(CTRL, TX_INTEN, 2, 1) 38 FIELD(CTRL, RX_INTEN, 3, 1) 39 FIELD(CTRL, TXO_INTEN, 4, 1) 40 FIELD(CTRL, RXO_INTEN, 5, 1) 41 FIELD(CTRL, HSTEST, 6, 1) 42 REG32(INTSTATUS, 0xc) 43 FIELD(INTSTATUS, TX, 0, 1) 44 FIELD(INTSTATUS, RX, 1, 1) 45 FIELD(INTSTATUS, TXO, 2, 1) 46 FIELD(INTSTATUS, RXO, 3, 1) 47 REG32(BAUDDIV, 0x10) 48 REG32(PID4, 0xFD0) 49 REG32(PID5, 0xFD4) 50 REG32(PID6, 0xFD8) 51 REG32(PID7, 0xFDC) 52 REG32(PID0, 0xFE0) 53 REG32(PID1, 0xFE4) 54 REG32(PID2, 0xFE8) 55 REG32(PID3, 0xFEC) 56 REG32(CID0, 0xFF0) 57 REG32(CID1, 0xFF4) 58 REG32(CID2, 0xFF8) 59 REG32(CID3, 0xFFC) 60 61 /* PID/CID values */ 62 static const int uart_id[] = { 63 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 64 0x21, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ 65 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 66 }; 67 68 static bool uart_baudrate_ok(CMSDKAPBUART *s) 69 { 70 /* The minimum permitted bauddiv setting is 16, so we just ignore 71 * settings below that (usually this means the device has just 72 * been reset and not yet programmed). 73 */ 74 return s->bauddiv >= 16 && s->bauddiv <= s->pclk_frq; 75 } 76 77 static void uart_update_parameters(CMSDKAPBUART *s) 78 { 79 QEMUSerialSetParams ssp; 80 81 /* This UART is always 8N1 but the baud rate is programmable. */ 82 if (!uart_baudrate_ok(s)) { 83 return; 84 } 85 86 ssp.data_bits = 8; 87 ssp.parity = 'N'; 88 ssp.stop_bits = 1; 89 ssp.speed = s->pclk_frq / s->bauddiv; 90 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 91 trace_cmsdk_apb_uart_set_params(ssp.speed); 92 } 93 94 static void cmsdk_apb_uart_update(CMSDKAPBUART *s) 95 { 96 /* update outbound irqs, including handling the way the rxo and txo 97 * interrupt status bits are just logical AND of the overrun bit in 98 * STATE and the overrun interrupt enable bit in CTRL. 99 */ 100 uint32_t omask = (R_INTSTATUS_RXO_MASK | R_INTSTATUS_TXO_MASK); 101 s->intstatus &= ~omask; 102 s->intstatus |= (s->state & (s->ctrl >> 2) & omask); 103 104 qemu_set_irq(s->txint, !!(s->intstatus & R_INTSTATUS_TX_MASK)); 105 qemu_set_irq(s->rxint, !!(s->intstatus & R_INTSTATUS_RX_MASK)); 106 qemu_set_irq(s->txovrint, !!(s->intstatus & R_INTSTATUS_TXO_MASK)); 107 qemu_set_irq(s->rxovrint, !!(s->intstatus & R_INTSTATUS_RXO_MASK)); 108 qemu_set_irq(s->uartint, !!(s->intstatus)); 109 } 110 111 static int uart_can_receive(void *opaque) 112 { 113 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 114 115 /* We can take a char if RX is enabled and the buffer is empty */ 116 if (s->ctrl & R_CTRL_RX_EN_MASK && !(s->state & R_STATE_RXFULL_MASK)) { 117 return 1; 118 } 119 return 0; 120 } 121 122 static void uart_receive(void *opaque, const uint8_t *buf, int size) 123 { 124 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 125 126 trace_cmsdk_apb_uart_receive(*buf); 127 128 /* In fact uart_can_receive() ensures that we can't be 129 * called unless RX is enabled and the buffer is empty, 130 * but we include this logic as documentation of what the 131 * hardware does if a character arrives in these circumstances. 132 */ 133 if (!(s->ctrl & R_CTRL_RX_EN_MASK)) { 134 /* Just drop the character on the floor */ 135 return; 136 } 137 138 if (s->state & R_STATE_RXFULL_MASK) { 139 s->state |= R_STATE_RXOVERRUN_MASK; 140 } 141 142 s->rxbuf = *buf; 143 s->state |= R_STATE_RXFULL_MASK; 144 if (s->ctrl & R_CTRL_RX_INTEN_MASK) { 145 s->intstatus |= R_INTSTATUS_RX_MASK; 146 } 147 cmsdk_apb_uart_update(s); 148 } 149 150 static uint64_t uart_read(void *opaque, hwaddr offset, unsigned size) 151 { 152 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 153 uint64_t r; 154 155 switch (offset) { 156 case A_DATA: 157 r = s->rxbuf; 158 s->state &= ~R_STATE_RXFULL_MASK; 159 cmsdk_apb_uart_update(s); 160 break; 161 case A_STATE: 162 r = s->state; 163 break; 164 case A_CTRL: 165 r = s->ctrl; 166 break; 167 case A_INTSTATUS: 168 r = s->intstatus; 169 break; 170 case A_BAUDDIV: 171 r = s->bauddiv; 172 break; 173 case A_PID4 ... A_CID3: 174 r = uart_id[(offset - A_PID4) / 4]; 175 break; 176 default: 177 qemu_log_mask(LOG_GUEST_ERROR, 178 "CMSDK APB UART read: bad offset %x\n", (int) offset); 179 r = 0; 180 break; 181 } 182 trace_cmsdk_apb_uart_read(offset, r, size); 183 return r; 184 } 185 186 /* Try to send tx data, and arrange to be called back later if 187 * we can't (ie the char backend is busy/blocking). 188 */ 189 static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque) 190 { 191 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 192 int ret; 193 194 s->watch_tag = 0; 195 196 if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK)) { 197 return FALSE; 198 } 199 200 ret = qemu_chr_fe_write(&s->chr, &s->txbuf, 1); 201 if (ret <= 0) { 202 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 203 uart_transmit, s); 204 if (!s->watch_tag) { 205 /* Most common reason to be here is "no chardev backend": 206 * just insta-drain the buffer, so the serial output 207 * goes into a void, rather than blocking the guest. 208 */ 209 goto buffer_drained; 210 } 211 /* Transmit pending */ 212 trace_cmsdk_apb_uart_tx_pending(); 213 return FALSE; 214 } 215 216 buffer_drained: 217 /* Character successfully sent */ 218 trace_cmsdk_apb_uart_tx(s->txbuf); 219 s->state &= ~R_STATE_TXFULL_MASK; 220 /* Going from TXFULL set to clear triggers the tx interrupt */ 221 if (s->ctrl & R_CTRL_TX_INTEN_MASK) { 222 s->intstatus |= R_INTSTATUS_TX_MASK; 223 } 224 cmsdk_apb_uart_update(s); 225 return FALSE; 226 } 227 228 static void uart_cancel_transmit(CMSDKAPBUART *s) 229 { 230 if (s->watch_tag) { 231 g_source_remove(s->watch_tag); 232 s->watch_tag = 0; 233 } 234 } 235 236 static void uart_write(void *opaque, hwaddr offset, uint64_t value, 237 unsigned size) 238 { 239 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 240 241 trace_cmsdk_apb_uart_write(offset, value, size); 242 243 switch (offset) { 244 case A_DATA: 245 s->txbuf = value; 246 if (s->state & R_STATE_TXFULL_MASK) { 247 /* Buffer already full -- note the overrun and let the 248 * existing pending transmit callback handle the new char. 249 */ 250 s->state |= R_STATE_TXOVERRUN_MASK; 251 cmsdk_apb_uart_update(s); 252 } else { 253 s->state |= R_STATE_TXFULL_MASK; 254 uart_transmit(NULL, G_IO_OUT, s); 255 } 256 break; 257 case A_STATE: 258 /* Bits 0 and 1 are read only; bits 2 and 3 are W1C */ 259 s->state &= ~(value & 260 (R_STATE_TXOVERRUN_MASK | R_STATE_RXOVERRUN_MASK)); 261 cmsdk_apb_uart_update(s); 262 break; 263 case A_CTRL: 264 s->ctrl = value & 0x7f; 265 if ((s->ctrl & R_CTRL_TX_EN_MASK) && !uart_baudrate_ok(s)) { 266 qemu_log_mask(LOG_GUEST_ERROR, 267 "CMSDK APB UART: Tx enabled with invalid baudrate\n"); 268 } 269 cmsdk_apb_uart_update(s); 270 break; 271 case A_INTSTATUS: 272 /* All bits are W1C. Clearing the overrun interrupt bits really 273 * clears the overrun status bits in the STATE register (which 274 * is then reflected into the intstatus value by the update function). 275 */ 276 s->state &= ~(value & (R_INTSTATUS_TXO_MASK | R_INTSTATUS_RXO_MASK)); 277 cmsdk_apb_uart_update(s); 278 break; 279 case A_BAUDDIV: 280 s->bauddiv = value & 0xFFFFF; 281 uart_update_parameters(s); 282 break; 283 case A_PID4 ... A_CID3: 284 qemu_log_mask(LOG_GUEST_ERROR, 285 "CMSDK APB UART write: write to RO offset 0x%x\n", 286 (int)offset); 287 break; 288 default: 289 qemu_log_mask(LOG_GUEST_ERROR, 290 "CMSDK APB UART write: bad offset 0x%x\n", (int) offset); 291 break; 292 } 293 } 294 295 static const MemoryRegionOps uart_ops = { 296 .read = uart_read, 297 .write = uart_write, 298 .endianness = DEVICE_LITTLE_ENDIAN, 299 }; 300 301 static void cmsdk_apb_uart_reset(DeviceState *dev) 302 { 303 CMSDKAPBUART *s = CMSDK_APB_UART(dev); 304 305 trace_cmsdk_apb_uart_reset(); 306 uart_cancel_transmit(s); 307 s->state = 0; 308 s->ctrl = 0; 309 s->intstatus = 0; 310 s->bauddiv = 0; 311 s->txbuf = 0; 312 s->rxbuf = 0; 313 } 314 315 static void cmsdk_apb_uart_init(Object *obj) 316 { 317 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 318 CMSDKAPBUART *s = CMSDK_APB_UART(obj); 319 320 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); 321 sysbus_init_mmio(sbd, &s->iomem); 322 sysbus_init_irq(sbd, &s->txint); 323 sysbus_init_irq(sbd, &s->rxint); 324 sysbus_init_irq(sbd, &s->txovrint); 325 sysbus_init_irq(sbd, &s->rxovrint); 326 sysbus_init_irq(sbd, &s->uartint); 327 } 328 329 static void cmsdk_apb_uart_realize(DeviceState *dev, Error **errp) 330 { 331 CMSDKAPBUART *s = CMSDK_APB_UART(dev); 332 333 if (s->pclk_frq == 0) { 334 error_setg(errp, "CMSDK APB UART: pclk-frq property must be set"); 335 return; 336 } 337 338 /* This UART has no flow control, so we do not need to register 339 * an event handler to deal with CHR_EVENT_BREAK. 340 */ 341 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, 342 NULL, NULL, s, NULL, true); 343 } 344 345 static int cmsdk_apb_uart_post_load(void *opaque, int version_id) 346 { 347 CMSDKAPBUART *s = CMSDK_APB_UART(opaque); 348 349 /* If we have a pending character, arrange to resend it. */ 350 if (s->state & R_STATE_TXFULL_MASK) { 351 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 352 uart_transmit, s); 353 } 354 uart_update_parameters(s); 355 return 0; 356 } 357 358 static const VMStateDescription cmsdk_apb_uart_vmstate = { 359 .name = "cmsdk-apb-uart", 360 .version_id = 1, 361 .minimum_version_id = 1, 362 .post_load = cmsdk_apb_uart_post_load, 363 .fields = (VMStateField[]) { 364 VMSTATE_UINT32(state, CMSDKAPBUART), 365 VMSTATE_UINT32(ctrl, CMSDKAPBUART), 366 VMSTATE_UINT32(intstatus, CMSDKAPBUART), 367 VMSTATE_UINT32(bauddiv, CMSDKAPBUART), 368 VMSTATE_UINT8(txbuf, CMSDKAPBUART), 369 VMSTATE_UINT8(rxbuf, CMSDKAPBUART), 370 VMSTATE_END_OF_LIST() 371 } 372 }; 373 374 static Property cmsdk_apb_uart_properties[] = { 375 DEFINE_PROP_CHR("chardev", CMSDKAPBUART, chr), 376 DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBUART, pclk_frq, 0), 377 DEFINE_PROP_END_OF_LIST(), 378 }; 379 380 static void cmsdk_apb_uart_class_init(ObjectClass *klass, void *data) 381 { 382 DeviceClass *dc = DEVICE_CLASS(klass); 383 384 dc->realize = cmsdk_apb_uart_realize; 385 dc->vmsd = &cmsdk_apb_uart_vmstate; 386 dc->reset = cmsdk_apb_uart_reset; 387 dc->props = cmsdk_apb_uart_properties; 388 } 389 390 static const TypeInfo cmsdk_apb_uart_info = { 391 .name = TYPE_CMSDK_APB_UART, 392 .parent = TYPE_SYS_BUS_DEVICE, 393 .instance_size = sizeof(CMSDKAPBUART), 394 .instance_init = cmsdk_apb_uart_init, 395 .class_init = cmsdk_apb_uart_class_init, 396 }; 397 398 static void cmsdk_apb_uart_register_types(void) 399 { 400 type_register_static(&cmsdk_apb_uart_info); 401 } 402 403 type_init(cmsdk_apb_uart_register_types); 404