1 /* 2 * Device model for Cadence UART 3 * 4 * Reference: Xilinx Zynq 7000 reference manual 5 * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf 6 * - Chapter 19 UART Controller 7 * - Appendix B for Register details 8 * 9 * Copyright (c) 2010 Xilinx Inc. 10 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 11 * Copyright (c) 2012 PetaLogix Pty Ltd. 12 * Written by Haibing Ma 13 * M.Habib 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/sysbus.h" 26 #include "sysemu/char.h" 27 #include "qemu/timer.h" 28 #include "qemu/log.h" 29 #include "hw/char/cadence_uart.h" 30 31 #ifdef CADENCE_UART_ERR_DEBUG 32 #define DB_PRINT(...) do { \ 33 fprintf(stderr, ": %s: ", __func__); \ 34 fprintf(stderr, ## __VA_ARGS__); \ 35 } while (0); 36 #else 37 #define DB_PRINT(...) 38 #endif 39 40 #define UART_SR_INTR_RTRIG 0x00000001 41 #define UART_SR_INTR_REMPTY 0x00000002 42 #define UART_SR_INTR_RFUL 0x00000004 43 #define UART_SR_INTR_TEMPTY 0x00000008 44 #define UART_SR_INTR_TFUL 0x00000010 45 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ 46 #define UART_SR_TTRIG 0x00002000 47 #define UART_INTR_TTRIG 0x00000400 48 /* bits fields in CSR that correlate to CISR. If any of these bits are set in 49 * SR, then the same bit in CISR is set high too */ 50 #define UART_SR_TO_CISR_MASK 0x0000001F 51 52 #define UART_INTR_ROVR 0x00000020 53 #define UART_INTR_FRAME 0x00000040 54 #define UART_INTR_PARE 0x00000080 55 #define UART_INTR_TIMEOUT 0x00000100 56 #define UART_INTR_DMSI 0x00000200 57 #define UART_INTR_TOVR 0x00001000 58 59 #define UART_SR_RACTIVE 0x00000400 60 #define UART_SR_TACTIVE 0x00000800 61 #define UART_SR_FDELT 0x00001000 62 63 #define UART_CR_RXRST 0x00000001 64 #define UART_CR_TXRST 0x00000002 65 #define UART_CR_RX_EN 0x00000004 66 #define UART_CR_RX_DIS 0x00000008 67 #define UART_CR_TX_EN 0x00000010 68 #define UART_CR_TX_DIS 0x00000020 69 #define UART_CR_RST_TO 0x00000040 70 #define UART_CR_STARTBRK 0x00000080 71 #define UART_CR_STOPBRK 0x00000100 72 73 #define UART_MR_CLKS 0x00000001 74 #define UART_MR_CHRL 0x00000006 75 #define UART_MR_CHRL_SH 1 76 #define UART_MR_PAR 0x00000038 77 #define UART_MR_PAR_SH 3 78 #define UART_MR_NBSTOP 0x000000C0 79 #define UART_MR_NBSTOP_SH 6 80 #define UART_MR_CHMODE 0x00000300 81 #define UART_MR_CHMODE_SH 8 82 #define UART_MR_UCLKEN 0x00000400 83 #define UART_MR_IRMODE 0x00000800 84 85 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) 86 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) 87 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) 88 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) 89 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) 90 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) 91 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) 92 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) 93 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) 94 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) 95 96 #define UART_INPUT_CLK 50000000 97 98 #define R_CR (0x00/4) 99 #define R_MR (0x04/4) 100 #define R_IER (0x08/4) 101 #define R_IDR (0x0C/4) 102 #define R_IMR (0x10/4) 103 #define R_CISR (0x14/4) 104 #define R_BRGR (0x18/4) 105 #define R_RTOR (0x1C/4) 106 #define R_RTRIG (0x20/4) 107 #define R_MCR (0x24/4) 108 #define R_MSR (0x28/4) 109 #define R_SR (0x2C/4) 110 #define R_TX_RX (0x30/4) 111 #define R_BDIV (0x34/4) 112 #define R_FDEL (0x38/4) 113 #define R_PMIN (0x3C/4) 114 #define R_PWID (0x40/4) 115 #define R_TTRIG (0x44/4) 116 117 118 static void uart_update_status(CadenceUARTState *s) 119 { 120 s->r[R_SR] = 0; 121 122 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL 123 : 0; 124 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; 125 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; 126 127 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL 128 : 0; 129 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; 130 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; 131 132 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; 133 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; 134 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); 135 } 136 137 static void fifo_trigger_update(void *opaque) 138 { 139 CadenceUARTState *s = opaque; 140 141 if (s->r[R_RTOR]) { 142 s->r[R_CISR] |= UART_INTR_TIMEOUT; 143 uart_update_status(s); 144 } 145 } 146 147 static void uart_rx_reset(CadenceUARTState *s) 148 { 149 s->rx_wpos = 0; 150 s->rx_count = 0; 151 qemu_chr_fe_accept_input(&s->chr); 152 } 153 154 static void uart_tx_reset(CadenceUARTState *s) 155 { 156 s->tx_count = 0; 157 } 158 159 static void uart_send_breaks(CadenceUARTState *s) 160 { 161 int break_enabled = 1; 162 163 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 164 &break_enabled); 165 } 166 167 static void uart_parameters_setup(CadenceUARTState *s) 168 { 169 QEMUSerialSetParams ssp; 170 unsigned int baud_rate, packet_size; 171 172 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? 173 UART_INPUT_CLK / 8 : UART_INPUT_CLK; 174 175 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); 176 packet_size = 1; 177 178 switch (s->r[R_MR] & UART_MR_PAR) { 179 case UART_PARITY_EVEN: 180 ssp.parity = 'E'; 181 packet_size++; 182 break; 183 case UART_PARITY_ODD: 184 ssp.parity = 'O'; 185 packet_size++; 186 break; 187 default: 188 ssp.parity = 'N'; 189 break; 190 } 191 192 switch (s->r[R_MR] & UART_MR_CHRL) { 193 case UART_DATA_BITS_6: 194 ssp.data_bits = 6; 195 break; 196 case UART_DATA_BITS_7: 197 ssp.data_bits = 7; 198 break; 199 default: 200 ssp.data_bits = 8; 201 break; 202 } 203 204 switch (s->r[R_MR] & UART_MR_NBSTOP) { 205 case UART_STOP_BITS_1: 206 ssp.stop_bits = 1; 207 break; 208 default: 209 ssp.stop_bits = 2; 210 break; 211 } 212 213 packet_size += ssp.data_bits + ssp.stop_bits; 214 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size; 215 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 216 } 217 218 static int uart_can_receive(void *opaque) 219 { 220 CadenceUARTState *s = opaque; 221 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); 222 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 223 224 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 225 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); 226 } 227 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 228 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count); 229 } 230 return ret; 231 } 232 233 static void uart_ctrl_update(CadenceUARTState *s) 234 { 235 if (s->r[R_CR] & UART_CR_TXRST) { 236 uart_tx_reset(s); 237 } 238 239 if (s->r[R_CR] & UART_CR_RXRST) { 240 uart_rx_reset(s); 241 } 242 243 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); 244 245 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { 246 uart_send_breaks(s); 247 } 248 } 249 250 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) 251 { 252 CadenceUARTState *s = opaque; 253 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 254 int i; 255 256 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 257 return; 258 } 259 260 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) { 261 s->r[R_CISR] |= UART_INTR_ROVR; 262 } else { 263 for (i = 0; i < size; i++) { 264 s->rx_fifo[s->rx_wpos] = buf[i]; 265 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE; 266 s->rx_count++; 267 } 268 timer_mod(s->fifo_trigger_handle, new_rx_time + 269 (s->char_tx_time * 4)); 270 } 271 uart_update_status(s); 272 } 273 274 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, 275 void *opaque) 276 { 277 CadenceUARTState *s = opaque; 278 int ret; 279 280 /* instant drain the fifo when there's no back-end */ 281 if (!qemu_chr_fe_get_driver(&s->chr)) { 282 s->tx_count = 0; 283 return FALSE; 284 } 285 286 if (!s->tx_count) { 287 return FALSE; 288 } 289 290 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count); 291 292 if (ret >= 0) { 293 s->tx_count -= ret; 294 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); 295 } 296 297 if (s->tx_count) { 298 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 299 cadence_uart_xmit, s); 300 if (!r) { 301 s->tx_count = 0; 302 return FALSE; 303 } 304 } 305 306 uart_update_status(s); 307 return FALSE; 308 } 309 310 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, 311 int size) 312 { 313 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { 314 return; 315 } 316 317 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) { 318 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; 319 /* 320 * This can only be a guest error via a bad tx fifo register push, 321 * as can_receive() should stop remote loop and echo modes ever getting 322 * us to here. 323 */ 324 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow"); 325 s->r[R_CISR] |= UART_INTR_ROVR; 326 } 327 328 memcpy(s->tx_fifo + s->tx_count, buf, size); 329 s->tx_count += size; 330 331 cadence_uart_xmit(NULL, G_IO_OUT, s); 332 } 333 334 static void uart_receive(void *opaque, const uint8_t *buf, int size) 335 { 336 CadenceUARTState *s = opaque; 337 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 338 339 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 340 uart_write_rx_fifo(opaque, buf, size); 341 } 342 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 343 uart_write_tx_fifo(s, buf, size); 344 } 345 } 346 347 static void uart_event(void *opaque, int event) 348 { 349 CadenceUARTState *s = opaque; 350 uint8_t buf = '\0'; 351 352 if (event == CHR_EVENT_BREAK) { 353 uart_write_rx_fifo(opaque, &buf, 1); 354 } 355 356 uart_update_status(s); 357 } 358 359 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c) 360 { 361 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 362 return; 363 } 364 365 if (s->rx_count) { 366 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos - 367 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE; 368 *c = s->rx_fifo[rx_rpos]; 369 s->rx_count--; 370 371 qemu_chr_fe_accept_input(&s->chr); 372 } else { 373 *c = 0; 374 } 375 376 uart_update_status(s); 377 } 378 379 static void uart_write(void *opaque, hwaddr offset, 380 uint64_t value, unsigned size) 381 { 382 CadenceUARTState *s = opaque; 383 384 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); 385 offset >>= 2; 386 if (offset >= CADENCE_UART_R_MAX) { 387 return; 388 } 389 switch (offset) { 390 case R_IER: /* ier (wts imr) */ 391 s->r[R_IMR] |= value; 392 break; 393 case R_IDR: /* idr (wtc imr) */ 394 s->r[R_IMR] &= ~value; 395 break; 396 case R_IMR: /* imr (read only) */ 397 break; 398 case R_CISR: /* cisr (wtc) */ 399 s->r[R_CISR] &= ~value; 400 break; 401 case R_TX_RX: /* UARTDR */ 402 switch (s->r[R_MR] & UART_MR_CHMODE) { 403 case NORMAL_MODE: 404 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 405 break; 406 case LOCAL_LOOPBACK: 407 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1); 408 break; 409 } 410 break; 411 case R_BRGR: /* Baud rate generator */ 412 if (value >= 0x01) { 413 s->r[offset] = value & 0xFFFF; 414 } 415 break; 416 case R_BDIV: /* Baud rate divider */ 417 if (value >= 0x04) { 418 s->r[offset] = value & 0xFF; 419 } 420 break; 421 default: 422 s->r[offset] = value; 423 } 424 425 switch (offset) { 426 case R_CR: 427 uart_ctrl_update(s); 428 break; 429 case R_MR: 430 uart_parameters_setup(s); 431 break; 432 } 433 uart_update_status(s); 434 } 435 436 static uint64_t uart_read(void *opaque, hwaddr offset, 437 unsigned size) 438 { 439 CadenceUARTState *s = opaque; 440 uint32_t c = 0; 441 442 offset >>= 2; 443 if (offset >= CADENCE_UART_R_MAX) { 444 c = 0; 445 } else if (offset == R_TX_RX) { 446 uart_read_rx_fifo(s, &c); 447 } else { 448 c = s->r[offset]; 449 } 450 451 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); 452 return c; 453 } 454 455 static const MemoryRegionOps uart_ops = { 456 .read = uart_read, 457 .write = uart_write, 458 .endianness = DEVICE_NATIVE_ENDIAN, 459 }; 460 461 static void cadence_uart_reset(DeviceState *dev) 462 { 463 CadenceUARTState *s = CADENCE_UART(dev); 464 465 s->r[R_CR] = 0x00000128; 466 s->r[R_IMR] = 0; 467 s->r[R_CISR] = 0; 468 s->r[R_RTRIG] = 0x00000020; 469 s->r[R_BRGR] = 0x0000028B; 470 s->r[R_BDIV] = 0x0000000F; 471 s->r[R_TTRIG] = 0x00000020; 472 473 uart_rx_reset(s); 474 uart_tx_reset(s); 475 476 uart_update_status(s); 477 } 478 479 static void cadence_uart_realize(DeviceState *dev, Error **errp) 480 { 481 CadenceUARTState *s = CADENCE_UART(dev); 482 483 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 484 fifo_trigger_update, s); 485 486 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, 487 uart_event, s, NULL, true); 488 } 489 490 static void cadence_uart_init(Object *obj) 491 { 492 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 493 CadenceUARTState *s = CADENCE_UART(obj); 494 495 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); 496 sysbus_init_mmio(sbd, &s->iomem); 497 sysbus_init_irq(sbd, &s->irq); 498 499 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; 500 } 501 502 static int cadence_uart_post_load(void *opaque, int version_id) 503 { 504 CadenceUARTState *s = opaque; 505 506 /* Ensure these two aren't invalid numbers */ 507 if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF || 508 s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) { 509 /* Value is invalid, abort */ 510 return 1; 511 } 512 513 uart_parameters_setup(s); 514 uart_update_status(s); 515 return 0; 516 } 517 518 static const VMStateDescription vmstate_cadence_uart = { 519 .name = "cadence_uart", 520 .version_id = 2, 521 .minimum_version_id = 2, 522 .post_load = cadence_uart_post_load, 523 .fields = (VMStateField[]) { 524 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX), 525 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState, 526 CADENCE_UART_RX_FIFO_SIZE), 527 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState, 528 CADENCE_UART_TX_FIFO_SIZE), 529 VMSTATE_UINT32(rx_count, CadenceUARTState), 530 VMSTATE_UINT32(tx_count, CadenceUARTState), 531 VMSTATE_UINT32(rx_wpos, CadenceUARTState), 532 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), 533 VMSTATE_END_OF_LIST() 534 } 535 }; 536 537 static Property cadence_uart_properties[] = { 538 DEFINE_PROP_CHR("chardev", CadenceUARTState, chr), 539 DEFINE_PROP_END_OF_LIST(), 540 }; 541 542 static void cadence_uart_class_init(ObjectClass *klass, void *data) 543 { 544 DeviceClass *dc = DEVICE_CLASS(klass); 545 546 dc->realize = cadence_uart_realize; 547 dc->vmsd = &vmstate_cadence_uart; 548 dc->reset = cadence_uart_reset; 549 dc->props = cadence_uart_properties; 550 } 551 552 static const TypeInfo cadence_uart_info = { 553 .name = TYPE_CADENCE_UART, 554 .parent = TYPE_SYS_BUS_DEVICE, 555 .instance_size = sizeof(CadenceUARTState), 556 .instance_init = cadence_uart_init, 557 .class_init = cadence_uart_class_init, 558 }; 559 560 static void cadence_uart_register_types(void) 561 { 562 type_register_static(&cadence_uart_info); 563 } 564 565 type_init(cadence_uart_register_types) 566