1 /* 2 * Device model for Cadence UART 3 * 4 * Copyright (c) 2010 Xilinx Inc. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 6 * Copyright (c) 2012 PetaLogix Pty Ltd. 7 * Written by Haibing Ma 8 * M.Habib 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "hw/sysbus.h" 20 #include "sysemu/char.h" 21 #include "qemu/timer.h" 22 23 #ifdef CADENCE_UART_ERR_DEBUG 24 #define DB_PRINT(...) do { \ 25 fprintf(stderr, ": %s: ", __func__); \ 26 fprintf(stderr, ## __VA_ARGS__); \ 27 } while (0); 28 #else 29 #define DB_PRINT(...) 30 #endif 31 32 #define UART_SR_INTR_RTRIG 0x00000001 33 #define UART_SR_INTR_REMPTY 0x00000002 34 #define UART_SR_INTR_RFUL 0x00000004 35 #define UART_SR_INTR_TEMPTY 0x00000008 36 #define UART_SR_INTR_TFUL 0x00000010 37 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ 38 #define UART_SR_TTRIG 0x00002000 39 #define UART_INTR_TTRIG 0x00000400 40 /* bits fields in CSR that correlate to CISR. If any of these bits are set in 41 * SR, then the same bit in CISR is set high too */ 42 #define UART_SR_TO_CISR_MASK 0x0000001F 43 44 #define UART_INTR_ROVR 0x00000020 45 #define UART_INTR_FRAME 0x00000040 46 #define UART_INTR_PARE 0x00000080 47 #define UART_INTR_TIMEOUT 0x00000100 48 #define UART_INTR_DMSI 0x00000200 49 #define UART_INTR_TOVR 0x00001000 50 51 #define UART_SR_RACTIVE 0x00000400 52 #define UART_SR_TACTIVE 0x00000800 53 #define UART_SR_FDELT 0x00001000 54 55 #define UART_CR_RXRST 0x00000001 56 #define UART_CR_TXRST 0x00000002 57 #define UART_CR_RX_EN 0x00000004 58 #define UART_CR_RX_DIS 0x00000008 59 #define UART_CR_TX_EN 0x00000010 60 #define UART_CR_TX_DIS 0x00000020 61 #define UART_CR_RST_TO 0x00000040 62 #define UART_CR_STARTBRK 0x00000080 63 #define UART_CR_STOPBRK 0x00000100 64 65 #define UART_MR_CLKS 0x00000001 66 #define UART_MR_CHRL 0x00000006 67 #define UART_MR_CHRL_SH 1 68 #define UART_MR_PAR 0x00000038 69 #define UART_MR_PAR_SH 3 70 #define UART_MR_NBSTOP 0x000000C0 71 #define UART_MR_NBSTOP_SH 6 72 #define UART_MR_CHMODE 0x00000300 73 #define UART_MR_CHMODE_SH 8 74 #define UART_MR_UCLKEN 0x00000400 75 #define UART_MR_IRMODE 0x00000800 76 77 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) 78 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) 79 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) 80 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) 81 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) 82 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) 83 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) 84 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) 85 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) 86 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) 87 88 #define RX_FIFO_SIZE 16 89 #define TX_FIFO_SIZE 16 90 #define UART_INPUT_CLK 50000000 91 92 #define R_CR (0x00/4) 93 #define R_MR (0x04/4) 94 #define R_IER (0x08/4) 95 #define R_IDR (0x0C/4) 96 #define R_IMR (0x10/4) 97 #define R_CISR (0x14/4) 98 #define R_BRGR (0x18/4) 99 #define R_RTOR (0x1C/4) 100 #define R_RTRIG (0x20/4) 101 #define R_MCR (0x24/4) 102 #define R_MSR (0x28/4) 103 #define R_SR (0x2C/4) 104 #define R_TX_RX (0x30/4) 105 #define R_BDIV (0x34/4) 106 #define R_FDEL (0x38/4) 107 #define R_PMIN (0x3C/4) 108 #define R_PWID (0x40/4) 109 #define R_TTRIG (0x44/4) 110 111 #define R_MAX (R_TTRIG + 1) 112 113 #define TYPE_CADENCE_UART "cadence_uart" 114 #define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART) 115 116 typedef struct { 117 /*< private >*/ 118 SysBusDevice parent_obj; 119 /*< public >*/ 120 121 MemoryRegion iomem; 122 uint32_t r[R_MAX]; 123 uint8_t rx_fifo[RX_FIFO_SIZE]; 124 uint8_t tx_fifo[TX_FIFO_SIZE]; 125 uint32_t rx_wpos; 126 uint32_t rx_count; 127 uint32_t tx_count; 128 uint64_t char_tx_time; 129 CharDriverState *chr; 130 qemu_irq irq; 131 QEMUTimer *fifo_trigger_handle; 132 } UartState; 133 134 static void uart_update_status(UartState *s) 135 { 136 s->r[R_SR] = 0; 137 138 s->r[R_SR] |= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0; 139 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; 140 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; 141 142 s->r[R_SR] |= s->tx_count == TX_FIFO_SIZE ? UART_SR_INTR_TFUL : 0; 143 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; 144 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; 145 146 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; 147 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; 148 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); 149 } 150 151 static void fifo_trigger_update(void *opaque) 152 { 153 UartState *s = (UartState *)opaque; 154 155 s->r[R_CISR] |= UART_INTR_TIMEOUT; 156 157 uart_update_status(s); 158 } 159 160 static void uart_rx_reset(UartState *s) 161 { 162 s->rx_wpos = 0; 163 s->rx_count = 0; 164 if (s->chr) { 165 qemu_chr_accept_input(s->chr); 166 } 167 } 168 169 static void uart_tx_reset(UartState *s) 170 { 171 s->tx_count = 0; 172 } 173 174 static void uart_send_breaks(UartState *s) 175 { 176 int break_enabled = 1; 177 178 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 179 &break_enabled); 180 } 181 182 static void uart_parameters_setup(UartState *s) 183 { 184 QEMUSerialSetParams ssp; 185 unsigned int baud_rate, packet_size; 186 187 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? 188 UART_INPUT_CLK / 8 : UART_INPUT_CLK; 189 190 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); 191 packet_size = 1; 192 193 switch (s->r[R_MR] & UART_MR_PAR) { 194 case UART_PARITY_EVEN: 195 ssp.parity = 'E'; 196 packet_size++; 197 break; 198 case UART_PARITY_ODD: 199 ssp.parity = 'O'; 200 packet_size++; 201 break; 202 default: 203 ssp.parity = 'N'; 204 break; 205 } 206 207 switch (s->r[R_MR] & UART_MR_CHRL) { 208 case UART_DATA_BITS_6: 209 ssp.data_bits = 6; 210 break; 211 case UART_DATA_BITS_7: 212 ssp.data_bits = 7; 213 break; 214 default: 215 ssp.data_bits = 8; 216 break; 217 } 218 219 switch (s->r[R_MR] & UART_MR_NBSTOP) { 220 case UART_STOP_BITS_1: 221 ssp.stop_bits = 1; 222 break; 223 default: 224 ssp.stop_bits = 2; 225 break; 226 } 227 228 packet_size += ssp.data_bits + ssp.stop_bits; 229 s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size; 230 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 231 } 232 233 static int uart_can_receive(void *opaque) 234 { 235 UartState *s = (UartState *)opaque; 236 int ret = MAX(RX_FIFO_SIZE, TX_FIFO_SIZE); 237 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 238 239 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 240 ret = MIN(ret, RX_FIFO_SIZE - s->rx_count); 241 } 242 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 243 ret = MIN(ret, TX_FIFO_SIZE - s->tx_count); 244 } 245 return ret; 246 } 247 248 static void uart_ctrl_update(UartState *s) 249 { 250 if (s->r[R_CR] & UART_CR_TXRST) { 251 uart_tx_reset(s); 252 } 253 254 if (s->r[R_CR] & UART_CR_RXRST) { 255 uart_rx_reset(s); 256 } 257 258 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); 259 260 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { 261 uart_send_breaks(s); 262 } 263 } 264 265 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) 266 { 267 UartState *s = (UartState *)opaque; 268 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 269 int i; 270 271 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 272 return; 273 } 274 275 if (s->rx_count == RX_FIFO_SIZE) { 276 s->r[R_CISR] |= UART_INTR_ROVR; 277 } else { 278 for (i = 0; i < size; i++) { 279 s->rx_fifo[s->rx_wpos] = buf[i]; 280 s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE; 281 s->rx_count++; 282 } 283 timer_mod(s->fifo_trigger_handle, new_rx_time + 284 (s->char_tx_time * 4)); 285 } 286 uart_update_status(s); 287 } 288 289 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, 290 void *opaque) 291 { 292 UartState *s = opaque; 293 int ret; 294 295 /* instant drain the fifo when there's no back-end */ 296 if (!s->chr) { 297 s->tx_count = 0; 298 } 299 300 if (!s->tx_count) { 301 return FALSE; 302 } 303 304 ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count); 305 s->tx_count -= ret; 306 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); 307 308 if (s->tx_count) { 309 int r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT, cadence_uart_xmit, s); 310 assert(r); 311 } 312 313 uart_update_status(s); 314 return FALSE; 315 } 316 317 static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size) 318 { 319 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { 320 return; 321 } 322 323 if (size > TX_FIFO_SIZE - s->tx_count) { 324 size = TX_FIFO_SIZE - s->tx_count; 325 /* 326 * This can only be a guest error via a bad tx fifo register push, 327 * as can_receive() should stop remote loop and echo modes ever getting 328 * us to here. 329 */ 330 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow"); 331 s->r[R_CISR] |= UART_INTR_ROVR; 332 } 333 334 memcpy(s->tx_fifo + s->tx_count, buf, size); 335 s->tx_count += size; 336 337 cadence_uart_xmit(NULL, G_IO_OUT, s); 338 } 339 340 static void uart_receive(void *opaque, const uint8_t *buf, int size) 341 { 342 UartState *s = (UartState *)opaque; 343 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 344 345 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 346 uart_write_rx_fifo(opaque, buf, size); 347 } 348 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 349 uart_write_tx_fifo(s, buf, size); 350 } 351 } 352 353 static void uart_event(void *opaque, int event) 354 { 355 UartState *s = (UartState *)opaque; 356 uint8_t buf = '\0'; 357 358 if (event == CHR_EVENT_BREAK) { 359 uart_write_rx_fifo(opaque, &buf, 1); 360 } 361 362 uart_update_status(s); 363 } 364 365 static void uart_read_rx_fifo(UartState *s, uint32_t *c) 366 { 367 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 368 return; 369 } 370 371 if (s->rx_count) { 372 uint32_t rx_rpos = 373 (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE; 374 *c = s->rx_fifo[rx_rpos]; 375 s->rx_count--; 376 377 qemu_chr_accept_input(s->chr); 378 } else { 379 *c = 0; 380 } 381 382 uart_update_status(s); 383 } 384 385 static void uart_write(void *opaque, hwaddr offset, 386 uint64_t value, unsigned size) 387 { 388 UartState *s = (UartState *)opaque; 389 390 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); 391 offset >>= 2; 392 switch (offset) { 393 case R_IER: /* ier (wts imr) */ 394 s->r[R_IMR] |= value; 395 break; 396 case R_IDR: /* idr (wtc imr) */ 397 s->r[R_IMR] &= ~value; 398 break; 399 case R_IMR: /* imr (read only) */ 400 break; 401 case R_CISR: /* cisr (wtc) */ 402 s->r[R_CISR] &= ~value; 403 break; 404 case R_TX_RX: /* UARTDR */ 405 switch (s->r[R_MR] & UART_MR_CHMODE) { 406 case NORMAL_MODE: 407 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 408 break; 409 case LOCAL_LOOPBACK: 410 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1); 411 break; 412 } 413 break; 414 default: 415 s->r[offset] = value; 416 } 417 418 switch (offset) { 419 case R_CR: 420 uart_ctrl_update(s); 421 break; 422 case R_MR: 423 uart_parameters_setup(s); 424 break; 425 } 426 uart_update_status(s); 427 } 428 429 static uint64_t uart_read(void *opaque, hwaddr offset, 430 unsigned size) 431 { 432 UartState *s = (UartState *)opaque; 433 uint32_t c = 0; 434 435 offset >>= 2; 436 if (offset >= R_MAX) { 437 c = 0; 438 } else if (offset == R_TX_RX) { 439 uart_read_rx_fifo(s, &c); 440 } else { 441 c = s->r[offset]; 442 } 443 444 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); 445 return c; 446 } 447 448 static const MemoryRegionOps uart_ops = { 449 .read = uart_read, 450 .write = uart_write, 451 .endianness = DEVICE_NATIVE_ENDIAN, 452 }; 453 454 static void cadence_uart_reset(DeviceState *dev) 455 { 456 UartState *s = CADENCE_UART(dev); 457 458 s->r[R_CR] = 0x00000128; 459 s->r[R_IMR] = 0; 460 s->r[R_CISR] = 0; 461 s->r[R_RTRIG] = 0x00000020; 462 s->r[R_BRGR] = 0x0000000F; 463 s->r[R_TTRIG] = 0x00000020; 464 465 uart_rx_reset(s); 466 uart_tx_reset(s); 467 468 uart_update_status(s); 469 } 470 471 static int cadence_uart_init(SysBusDevice *dev) 472 { 473 UartState *s = CADENCE_UART(dev); 474 475 memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000); 476 sysbus_init_mmio(dev, &s->iomem); 477 sysbus_init_irq(dev, &s->irq); 478 479 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 480 (QEMUTimerCB *)fifo_trigger_update, s); 481 482 s->char_tx_time = (get_ticks_per_sec() / 9600) * 10; 483 484 s->chr = qemu_char_get_next_serial(); 485 486 if (s->chr) { 487 qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive, 488 uart_event, s); 489 } 490 491 return 0; 492 } 493 494 static int cadence_uart_post_load(void *opaque, int version_id) 495 { 496 UartState *s = opaque; 497 498 uart_parameters_setup(s); 499 uart_update_status(s); 500 return 0; 501 } 502 503 static const VMStateDescription vmstate_cadence_uart = { 504 .name = "cadence_uart", 505 .version_id = 2, 506 .minimum_version_id = 2, 507 .minimum_version_id_old = 2, 508 .post_load = cadence_uart_post_load, 509 .fields = (VMStateField[]) { 510 VMSTATE_UINT32_ARRAY(r, UartState, R_MAX), 511 VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE), 512 VMSTATE_UINT8_ARRAY(tx_fifo, UartState, RX_FIFO_SIZE), 513 VMSTATE_UINT32(rx_count, UartState), 514 VMSTATE_UINT32(tx_count, UartState), 515 VMSTATE_UINT32(rx_wpos, UartState), 516 VMSTATE_TIMER(fifo_trigger_handle, UartState), 517 VMSTATE_END_OF_LIST() 518 } 519 }; 520 521 static void cadence_uart_class_init(ObjectClass *klass, void *data) 522 { 523 DeviceClass *dc = DEVICE_CLASS(klass); 524 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 525 526 sdc->init = cadence_uart_init; 527 dc->vmsd = &vmstate_cadence_uart; 528 dc->reset = cadence_uart_reset; 529 } 530 531 static const TypeInfo cadence_uart_info = { 532 .name = TYPE_CADENCE_UART, 533 .parent = TYPE_SYS_BUS_DEVICE, 534 .instance_size = sizeof(UartState), 535 .class_init = cadence_uart_class_init, 536 }; 537 538 static void cadence_uart_register_types(void) 539 { 540 type_register_static(&cadence_uart_info); 541 } 542 543 type_init(cadence_uart_register_types) 544