1 /* 2 * Device model for Cadence UART 3 * 4 * Reference: Xilinx Zynq 7000 reference manual 5 * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf 6 * - Chapter 19 UART Controller 7 * - Appendix B for Register details 8 * 9 * Copyright (c) 2010 Xilinx Inc. 10 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 11 * Copyright (c) 2012 PetaLogix Pty Ltd. 12 * Written by Haibing Ma 13 * M.Habib 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/sysbus.h" 26 #include "chardev/char-fe.h" 27 #include "chardev/char-serial.h" 28 #include "qemu/timer.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 #include "hw/char/cadence_uart.h" 32 #include "hw/irq.h" 33 34 #ifdef CADENCE_UART_ERR_DEBUG 35 #define DB_PRINT(...) do { \ 36 fprintf(stderr, ": %s: ", __func__); \ 37 fprintf(stderr, ## __VA_ARGS__); \ 38 } while (0) 39 #else 40 #define DB_PRINT(...) 41 #endif 42 43 #define UART_SR_INTR_RTRIG 0x00000001 44 #define UART_SR_INTR_REMPTY 0x00000002 45 #define UART_SR_INTR_RFUL 0x00000004 46 #define UART_SR_INTR_TEMPTY 0x00000008 47 #define UART_SR_INTR_TFUL 0x00000010 48 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ 49 #define UART_SR_TTRIG 0x00002000 50 #define UART_INTR_TTRIG 0x00000400 51 /* bits fields in CSR that correlate to CISR. If any of these bits are set in 52 * SR, then the same bit in CISR is set high too */ 53 #define UART_SR_TO_CISR_MASK 0x0000001F 54 55 #define UART_INTR_ROVR 0x00000020 56 #define UART_INTR_FRAME 0x00000040 57 #define UART_INTR_PARE 0x00000080 58 #define UART_INTR_TIMEOUT 0x00000100 59 #define UART_INTR_DMSI 0x00000200 60 #define UART_INTR_TOVR 0x00001000 61 62 #define UART_SR_RACTIVE 0x00000400 63 #define UART_SR_TACTIVE 0x00000800 64 #define UART_SR_FDELT 0x00001000 65 66 #define UART_CR_RXRST 0x00000001 67 #define UART_CR_TXRST 0x00000002 68 #define UART_CR_RX_EN 0x00000004 69 #define UART_CR_RX_DIS 0x00000008 70 #define UART_CR_TX_EN 0x00000010 71 #define UART_CR_TX_DIS 0x00000020 72 #define UART_CR_RST_TO 0x00000040 73 #define UART_CR_STARTBRK 0x00000080 74 #define UART_CR_STOPBRK 0x00000100 75 76 #define UART_MR_CLKS 0x00000001 77 #define UART_MR_CHRL 0x00000006 78 #define UART_MR_CHRL_SH 1 79 #define UART_MR_PAR 0x00000038 80 #define UART_MR_PAR_SH 3 81 #define UART_MR_NBSTOP 0x000000C0 82 #define UART_MR_NBSTOP_SH 6 83 #define UART_MR_CHMODE 0x00000300 84 #define UART_MR_CHMODE_SH 8 85 #define UART_MR_UCLKEN 0x00000400 86 #define UART_MR_IRMODE 0x00000800 87 88 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) 89 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) 90 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) 91 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) 92 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) 93 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) 94 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) 95 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) 96 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) 97 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) 98 99 #define UART_INPUT_CLK 50000000 100 101 #define R_CR (0x00/4) 102 #define R_MR (0x04/4) 103 #define R_IER (0x08/4) 104 #define R_IDR (0x0C/4) 105 #define R_IMR (0x10/4) 106 #define R_CISR (0x14/4) 107 #define R_BRGR (0x18/4) 108 #define R_RTOR (0x1C/4) 109 #define R_RTRIG (0x20/4) 110 #define R_MCR (0x24/4) 111 #define R_MSR (0x28/4) 112 #define R_SR (0x2C/4) 113 #define R_TX_RX (0x30/4) 114 #define R_BDIV (0x34/4) 115 #define R_FDEL (0x38/4) 116 #define R_PMIN (0x3C/4) 117 #define R_PWID (0x40/4) 118 #define R_TTRIG (0x44/4) 119 120 121 static void uart_update_status(CadenceUARTState *s) 122 { 123 s->r[R_SR] = 0; 124 125 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL 126 : 0; 127 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; 128 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; 129 130 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL 131 : 0; 132 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; 133 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; 134 135 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; 136 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; 137 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); 138 } 139 140 static void fifo_trigger_update(void *opaque) 141 { 142 CadenceUARTState *s = opaque; 143 144 if (s->r[R_RTOR]) { 145 s->r[R_CISR] |= UART_INTR_TIMEOUT; 146 uart_update_status(s); 147 } 148 } 149 150 static void uart_rx_reset(CadenceUARTState *s) 151 { 152 s->rx_wpos = 0; 153 s->rx_count = 0; 154 qemu_chr_fe_accept_input(&s->chr); 155 } 156 157 static void uart_tx_reset(CadenceUARTState *s) 158 { 159 s->tx_count = 0; 160 } 161 162 static void uart_send_breaks(CadenceUARTState *s) 163 { 164 int break_enabled = 1; 165 166 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 167 &break_enabled); 168 } 169 170 static void uart_parameters_setup(CadenceUARTState *s) 171 { 172 QEMUSerialSetParams ssp; 173 unsigned int baud_rate, packet_size; 174 175 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? 176 UART_INPUT_CLK / 8 : UART_INPUT_CLK; 177 178 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); 179 packet_size = 1; 180 181 switch (s->r[R_MR] & UART_MR_PAR) { 182 case UART_PARITY_EVEN: 183 ssp.parity = 'E'; 184 packet_size++; 185 break; 186 case UART_PARITY_ODD: 187 ssp.parity = 'O'; 188 packet_size++; 189 break; 190 default: 191 ssp.parity = 'N'; 192 break; 193 } 194 195 switch (s->r[R_MR] & UART_MR_CHRL) { 196 case UART_DATA_BITS_6: 197 ssp.data_bits = 6; 198 break; 199 case UART_DATA_BITS_7: 200 ssp.data_bits = 7; 201 break; 202 default: 203 ssp.data_bits = 8; 204 break; 205 } 206 207 switch (s->r[R_MR] & UART_MR_NBSTOP) { 208 case UART_STOP_BITS_1: 209 ssp.stop_bits = 1; 210 break; 211 default: 212 ssp.stop_bits = 2; 213 break; 214 } 215 216 packet_size += ssp.data_bits + ssp.stop_bits; 217 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size; 218 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 219 } 220 221 static int uart_can_receive(void *opaque) 222 { 223 CadenceUARTState *s = opaque; 224 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); 225 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 226 227 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 228 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); 229 } 230 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 231 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count); 232 } 233 return ret; 234 } 235 236 static void uart_ctrl_update(CadenceUARTState *s) 237 { 238 if (s->r[R_CR] & UART_CR_TXRST) { 239 uart_tx_reset(s); 240 } 241 242 if (s->r[R_CR] & UART_CR_RXRST) { 243 uart_rx_reset(s); 244 } 245 246 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); 247 248 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { 249 uart_send_breaks(s); 250 } 251 } 252 253 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) 254 { 255 CadenceUARTState *s = opaque; 256 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 257 int i; 258 259 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 260 return; 261 } 262 263 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) { 264 s->r[R_CISR] |= UART_INTR_ROVR; 265 } else { 266 for (i = 0; i < size; i++) { 267 s->rx_fifo[s->rx_wpos] = buf[i]; 268 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE; 269 s->rx_count++; 270 } 271 timer_mod(s->fifo_trigger_handle, new_rx_time + 272 (s->char_tx_time * 4)); 273 } 274 uart_update_status(s); 275 } 276 277 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, 278 void *opaque) 279 { 280 CadenceUARTState *s = opaque; 281 int ret; 282 283 /* instant drain the fifo when there's no back-end */ 284 if (!qemu_chr_fe_backend_connected(&s->chr)) { 285 s->tx_count = 0; 286 return FALSE; 287 } 288 289 if (!s->tx_count) { 290 return FALSE; 291 } 292 293 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count); 294 295 if (ret >= 0) { 296 s->tx_count -= ret; 297 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); 298 } 299 300 if (s->tx_count) { 301 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 302 cadence_uart_xmit, s); 303 if (!r) { 304 s->tx_count = 0; 305 return FALSE; 306 } 307 } 308 309 uart_update_status(s); 310 return FALSE; 311 } 312 313 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, 314 int size) 315 { 316 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { 317 return; 318 } 319 320 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) { 321 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; 322 /* 323 * This can only be a guest error via a bad tx fifo register push, 324 * as can_receive() should stop remote loop and echo modes ever getting 325 * us to here. 326 */ 327 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow"); 328 s->r[R_CISR] |= UART_INTR_ROVR; 329 } 330 331 memcpy(s->tx_fifo + s->tx_count, buf, size); 332 s->tx_count += size; 333 334 cadence_uart_xmit(NULL, G_IO_OUT, s); 335 } 336 337 static void uart_receive(void *opaque, const uint8_t *buf, int size) 338 { 339 CadenceUARTState *s = opaque; 340 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 341 342 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 343 uart_write_rx_fifo(opaque, buf, size); 344 } 345 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 346 uart_write_tx_fifo(s, buf, size); 347 } 348 } 349 350 static void uart_event(void *opaque, int event) 351 { 352 CadenceUARTState *s = opaque; 353 uint8_t buf = '\0'; 354 355 if (event == CHR_EVENT_BREAK) { 356 uart_write_rx_fifo(opaque, &buf, 1); 357 } 358 359 uart_update_status(s); 360 } 361 362 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c) 363 { 364 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 365 return; 366 } 367 368 if (s->rx_count) { 369 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos - 370 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE; 371 *c = s->rx_fifo[rx_rpos]; 372 s->rx_count--; 373 374 qemu_chr_fe_accept_input(&s->chr); 375 } else { 376 *c = 0; 377 } 378 379 uart_update_status(s); 380 } 381 382 static void uart_write(void *opaque, hwaddr offset, 383 uint64_t value, unsigned size) 384 { 385 CadenceUARTState *s = opaque; 386 387 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); 388 offset >>= 2; 389 if (offset >= CADENCE_UART_R_MAX) { 390 return; 391 } 392 switch (offset) { 393 case R_IER: /* ier (wts imr) */ 394 s->r[R_IMR] |= value; 395 break; 396 case R_IDR: /* idr (wtc imr) */ 397 s->r[R_IMR] &= ~value; 398 break; 399 case R_IMR: /* imr (read only) */ 400 break; 401 case R_CISR: /* cisr (wtc) */ 402 s->r[R_CISR] &= ~value; 403 break; 404 case R_TX_RX: /* UARTDR */ 405 switch (s->r[R_MR] & UART_MR_CHMODE) { 406 case NORMAL_MODE: 407 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 408 break; 409 case LOCAL_LOOPBACK: 410 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1); 411 break; 412 } 413 break; 414 case R_BRGR: /* Baud rate generator */ 415 if (value >= 0x01) { 416 s->r[offset] = value & 0xFFFF; 417 } 418 break; 419 case R_BDIV: /* Baud rate divider */ 420 if (value >= 0x04) { 421 s->r[offset] = value & 0xFF; 422 } 423 break; 424 default: 425 s->r[offset] = value; 426 } 427 428 switch (offset) { 429 case R_CR: 430 uart_ctrl_update(s); 431 break; 432 case R_MR: 433 uart_parameters_setup(s); 434 break; 435 } 436 uart_update_status(s); 437 } 438 439 static uint64_t uart_read(void *opaque, hwaddr offset, 440 unsigned size) 441 { 442 CadenceUARTState *s = opaque; 443 uint32_t c = 0; 444 445 offset >>= 2; 446 if (offset >= CADENCE_UART_R_MAX) { 447 c = 0; 448 } else if (offset == R_TX_RX) { 449 uart_read_rx_fifo(s, &c); 450 } else { 451 c = s->r[offset]; 452 } 453 454 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); 455 return c; 456 } 457 458 static const MemoryRegionOps uart_ops = { 459 .read = uart_read, 460 .write = uart_write, 461 .endianness = DEVICE_NATIVE_ENDIAN, 462 }; 463 464 static void cadence_uart_reset(DeviceState *dev) 465 { 466 CadenceUARTState *s = CADENCE_UART(dev); 467 468 s->r[R_CR] = 0x00000128; 469 s->r[R_IMR] = 0; 470 s->r[R_CISR] = 0; 471 s->r[R_RTRIG] = 0x00000020; 472 s->r[R_BRGR] = 0x0000028B; 473 s->r[R_BDIV] = 0x0000000F; 474 s->r[R_TTRIG] = 0x00000020; 475 476 uart_rx_reset(s); 477 uart_tx_reset(s); 478 479 uart_update_status(s); 480 } 481 482 static void cadence_uart_realize(DeviceState *dev, Error **errp) 483 { 484 CadenceUARTState *s = CADENCE_UART(dev); 485 486 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 487 fifo_trigger_update, s); 488 489 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, 490 uart_event, NULL, s, NULL, true); 491 } 492 493 static void cadence_uart_init(Object *obj) 494 { 495 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 496 CadenceUARTState *s = CADENCE_UART(obj); 497 498 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); 499 sysbus_init_mmio(sbd, &s->iomem); 500 sysbus_init_irq(sbd, &s->irq); 501 502 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; 503 } 504 505 static int cadence_uart_post_load(void *opaque, int version_id) 506 { 507 CadenceUARTState *s = opaque; 508 509 /* Ensure these two aren't invalid numbers */ 510 if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF || 511 s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) { 512 /* Value is invalid, abort */ 513 return 1; 514 } 515 516 uart_parameters_setup(s); 517 uart_update_status(s); 518 return 0; 519 } 520 521 static const VMStateDescription vmstate_cadence_uart = { 522 .name = "cadence_uart", 523 .version_id = 2, 524 .minimum_version_id = 2, 525 .post_load = cadence_uart_post_load, 526 .fields = (VMStateField[]) { 527 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX), 528 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState, 529 CADENCE_UART_RX_FIFO_SIZE), 530 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState, 531 CADENCE_UART_TX_FIFO_SIZE), 532 VMSTATE_UINT32(rx_count, CadenceUARTState), 533 VMSTATE_UINT32(tx_count, CadenceUARTState), 534 VMSTATE_UINT32(rx_wpos, CadenceUARTState), 535 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), 536 VMSTATE_END_OF_LIST() 537 } 538 }; 539 540 static Property cadence_uart_properties[] = { 541 DEFINE_PROP_CHR("chardev", CadenceUARTState, chr), 542 DEFINE_PROP_END_OF_LIST(), 543 }; 544 545 static void cadence_uart_class_init(ObjectClass *klass, void *data) 546 { 547 DeviceClass *dc = DEVICE_CLASS(klass); 548 549 dc->realize = cadence_uart_realize; 550 dc->vmsd = &vmstate_cadence_uart; 551 dc->reset = cadence_uart_reset; 552 dc->props = cadence_uart_properties; 553 } 554 555 static const TypeInfo cadence_uart_info = { 556 .name = TYPE_CADENCE_UART, 557 .parent = TYPE_SYS_BUS_DEVICE, 558 .instance_size = sizeof(CadenceUARTState), 559 .instance_init = cadence_uart_init, 560 .class_init = cadence_uart_class_init, 561 }; 562 563 static void cadence_uart_register_types(void) 564 { 565 type_register_static(&cadence_uart_info); 566 } 567 568 type_init(cadence_uart_register_types) 569