1 /* 2 * Device model for Cadence UART 3 * 4 * Copyright (c) 2010 Xilinx Inc. 5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 6 * Copyright (c) 2012 PetaLogix Pty Ltd. 7 * Written by Haibing Ma 8 * M.Habib 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/char/cadence_uart.h" 21 22 #ifdef CADENCE_UART_ERR_DEBUG 23 #define DB_PRINT(...) do { \ 24 fprintf(stderr, ": %s: ", __func__); \ 25 fprintf(stderr, ## __VA_ARGS__); \ 26 } while (0); 27 #else 28 #define DB_PRINT(...) 29 #endif 30 31 #define UART_SR_INTR_RTRIG 0x00000001 32 #define UART_SR_INTR_REMPTY 0x00000002 33 #define UART_SR_INTR_RFUL 0x00000004 34 #define UART_SR_INTR_TEMPTY 0x00000008 35 #define UART_SR_INTR_TFUL 0x00000010 36 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ 37 #define UART_SR_TTRIG 0x00002000 38 #define UART_INTR_TTRIG 0x00000400 39 /* bits fields in CSR that correlate to CISR. If any of these bits are set in 40 * SR, then the same bit in CISR is set high too */ 41 #define UART_SR_TO_CISR_MASK 0x0000001F 42 43 #define UART_INTR_ROVR 0x00000020 44 #define UART_INTR_FRAME 0x00000040 45 #define UART_INTR_PARE 0x00000080 46 #define UART_INTR_TIMEOUT 0x00000100 47 #define UART_INTR_DMSI 0x00000200 48 #define UART_INTR_TOVR 0x00001000 49 50 #define UART_SR_RACTIVE 0x00000400 51 #define UART_SR_TACTIVE 0x00000800 52 #define UART_SR_FDELT 0x00001000 53 54 #define UART_CR_RXRST 0x00000001 55 #define UART_CR_TXRST 0x00000002 56 #define UART_CR_RX_EN 0x00000004 57 #define UART_CR_RX_DIS 0x00000008 58 #define UART_CR_TX_EN 0x00000010 59 #define UART_CR_TX_DIS 0x00000020 60 #define UART_CR_RST_TO 0x00000040 61 #define UART_CR_STARTBRK 0x00000080 62 #define UART_CR_STOPBRK 0x00000100 63 64 #define UART_MR_CLKS 0x00000001 65 #define UART_MR_CHRL 0x00000006 66 #define UART_MR_CHRL_SH 1 67 #define UART_MR_PAR 0x00000038 68 #define UART_MR_PAR_SH 3 69 #define UART_MR_NBSTOP 0x000000C0 70 #define UART_MR_NBSTOP_SH 6 71 #define UART_MR_CHMODE 0x00000300 72 #define UART_MR_CHMODE_SH 8 73 #define UART_MR_UCLKEN 0x00000400 74 #define UART_MR_IRMODE 0x00000800 75 76 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) 77 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) 78 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) 79 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) 80 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) 81 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) 82 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) 83 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) 84 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) 85 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) 86 87 #define UART_INPUT_CLK 50000000 88 89 #define R_CR (0x00/4) 90 #define R_MR (0x04/4) 91 #define R_IER (0x08/4) 92 #define R_IDR (0x0C/4) 93 #define R_IMR (0x10/4) 94 #define R_CISR (0x14/4) 95 #define R_BRGR (0x18/4) 96 #define R_RTOR (0x1C/4) 97 #define R_RTRIG (0x20/4) 98 #define R_MCR (0x24/4) 99 #define R_MSR (0x28/4) 100 #define R_SR (0x2C/4) 101 #define R_TX_RX (0x30/4) 102 #define R_BDIV (0x34/4) 103 #define R_FDEL (0x38/4) 104 #define R_PMIN (0x3C/4) 105 #define R_PWID (0x40/4) 106 #define R_TTRIG (0x44/4) 107 108 109 static void uart_update_status(CadenceUARTState *s) 110 { 111 s->r[R_SR] = 0; 112 113 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL 114 : 0; 115 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; 116 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; 117 118 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL 119 : 0; 120 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; 121 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; 122 123 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; 124 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; 125 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); 126 } 127 128 static void fifo_trigger_update(void *opaque) 129 { 130 CadenceUARTState *s = opaque; 131 132 s->r[R_CISR] |= UART_INTR_TIMEOUT; 133 134 uart_update_status(s); 135 } 136 137 static void uart_rx_reset(CadenceUARTState *s) 138 { 139 s->rx_wpos = 0; 140 s->rx_count = 0; 141 if (s->chr) { 142 qemu_chr_accept_input(s->chr); 143 } 144 } 145 146 static void uart_tx_reset(CadenceUARTState *s) 147 { 148 s->tx_count = 0; 149 } 150 151 static void uart_send_breaks(CadenceUARTState *s) 152 { 153 int break_enabled = 1; 154 155 if (s->chr) { 156 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 157 &break_enabled); 158 } 159 } 160 161 static void uart_parameters_setup(CadenceUARTState *s) 162 { 163 QEMUSerialSetParams ssp; 164 unsigned int baud_rate, packet_size; 165 166 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? 167 UART_INPUT_CLK / 8 : UART_INPUT_CLK; 168 169 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); 170 packet_size = 1; 171 172 switch (s->r[R_MR] & UART_MR_PAR) { 173 case UART_PARITY_EVEN: 174 ssp.parity = 'E'; 175 packet_size++; 176 break; 177 case UART_PARITY_ODD: 178 ssp.parity = 'O'; 179 packet_size++; 180 break; 181 default: 182 ssp.parity = 'N'; 183 break; 184 } 185 186 switch (s->r[R_MR] & UART_MR_CHRL) { 187 case UART_DATA_BITS_6: 188 ssp.data_bits = 6; 189 break; 190 case UART_DATA_BITS_7: 191 ssp.data_bits = 7; 192 break; 193 default: 194 ssp.data_bits = 8; 195 break; 196 } 197 198 switch (s->r[R_MR] & UART_MR_NBSTOP) { 199 case UART_STOP_BITS_1: 200 ssp.stop_bits = 1; 201 break; 202 default: 203 ssp.stop_bits = 2; 204 break; 205 } 206 207 packet_size += ssp.data_bits + ssp.stop_bits; 208 s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size; 209 if (s->chr) { 210 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 211 } 212 } 213 214 static int uart_can_receive(void *opaque) 215 { 216 CadenceUARTState *s = opaque; 217 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); 218 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 219 220 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 221 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); 222 } 223 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 224 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count); 225 } 226 return ret; 227 } 228 229 static void uart_ctrl_update(CadenceUARTState *s) 230 { 231 if (s->r[R_CR] & UART_CR_TXRST) { 232 uart_tx_reset(s); 233 } 234 235 if (s->r[R_CR] & UART_CR_RXRST) { 236 uart_rx_reset(s); 237 } 238 239 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); 240 241 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { 242 uart_send_breaks(s); 243 } 244 } 245 246 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) 247 { 248 CadenceUARTState *s = opaque; 249 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 250 int i; 251 252 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 253 return; 254 } 255 256 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) { 257 s->r[R_CISR] |= UART_INTR_ROVR; 258 } else { 259 for (i = 0; i < size; i++) { 260 s->rx_fifo[s->rx_wpos] = buf[i]; 261 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE; 262 s->rx_count++; 263 } 264 timer_mod(s->fifo_trigger_handle, new_rx_time + 265 (s->char_tx_time * 4)); 266 } 267 uart_update_status(s); 268 } 269 270 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, 271 void *opaque) 272 { 273 CadenceUARTState *s = opaque; 274 int ret; 275 276 /* instant drain the fifo when there's no back-end */ 277 if (!s->chr) { 278 s->tx_count = 0; 279 return FALSE; 280 } 281 282 if (!s->tx_count) { 283 return FALSE; 284 } 285 286 ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count); 287 s->tx_count -= ret; 288 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); 289 290 if (s->tx_count) { 291 int r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP, 292 cadence_uart_xmit, s); 293 assert(r); 294 } 295 296 uart_update_status(s); 297 return FALSE; 298 } 299 300 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, 301 int size) 302 { 303 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { 304 return; 305 } 306 307 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) { 308 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; 309 /* 310 * This can only be a guest error via a bad tx fifo register push, 311 * as can_receive() should stop remote loop and echo modes ever getting 312 * us to here. 313 */ 314 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow"); 315 s->r[R_CISR] |= UART_INTR_ROVR; 316 } 317 318 memcpy(s->tx_fifo + s->tx_count, buf, size); 319 s->tx_count += size; 320 321 cadence_uart_xmit(NULL, G_IO_OUT, s); 322 } 323 324 static void uart_receive(void *opaque, const uint8_t *buf, int size) 325 { 326 CadenceUARTState *s = opaque; 327 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 328 329 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 330 uart_write_rx_fifo(opaque, buf, size); 331 } 332 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 333 uart_write_tx_fifo(s, buf, size); 334 } 335 } 336 337 static void uart_event(void *opaque, int event) 338 { 339 CadenceUARTState *s = opaque; 340 uint8_t buf = '\0'; 341 342 if (event == CHR_EVENT_BREAK) { 343 uart_write_rx_fifo(opaque, &buf, 1); 344 } 345 346 uart_update_status(s); 347 } 348 349 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c) 350 { 351 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 352 return; 353 } 354 355 if (s->rx_count) { 356 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos - 357 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE; 358 *c = s->rx_fifo[rx_rpos]; 359 s->rx_count--; 360 361 if (s->chr) { 362 qemu_chr_accept_input(s->chr); 363 } 364 } else { 365 *c = 0; 366 } 367 368 uart_update_status(s); 369 } 370 371 static void uart_write(void *opaque, hwaddr offset, 372 uint64_t value, unsigned size) 373 { 374 CadenceUARTState *s = opaque; 375 376 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); 377 offset >>= 2; 378 switch (offset) { 379 case R_IER: /* ier (wts imr) */ 380 s->r[R_IMR] |= value; 381 break; 382 case R_IDR: /* idr (wtc imr) */ 383 s->r[R_IMR] &= ~value; 384 break; 385 case R_IMR: /* imr (read only) */ 386 break; 387 case R_CISR: /* cisr (wtc) */ 388 s->r[R_CISR] &= ~value; 389 break; 390 case R_TX_RX: /* UARTDR */ 391 switch (s->r[R_MR] & UART_MR_CHMODE) { 392 case NORMAL_MODE: 393 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 394 break; 395 case LOCAL_LOOPBACK: 396 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1); 397 break; 398 } 399 break; 400 default: 401 s->r[offset] = value; 402 } 403 404 switch (offset) { 405 case R_CR: 406 uart_ctrl_update(s); 407 break; 408 case R_MR: 409 uart_parameters_setup(s); 410 break; 411 } 412 uart_update_status(s); 413 } 414 415 static uint64_t uart_read(void *opaque, hwaddr offset, 416 unsigned size) 417 { 418 CadenceUARTState *s = opaque; 419 uint32_t c = 0; 420 421 offset >>= 2; 422 if (offset >= CADENCE_UART_R_MAX) { 423 c = 0; 424 } else if (offset == R_TX_RX) { 425 uart_read_rx_fifo(s, &c); 426 } else { 427 c = s->r[offset]; 428 } 429 430 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); 431 return c; 432 } 433 434 static const MemoryRegionOps uart_ops = { 435 .read = uart_read, 436 .write = uart_write, 437 .endianness = DEVICE_NATIVE_ENDIAN, 438 }; 439 440 static void cadence_uart_reset(DeviceState *dev) 441 { 442 CadenceUARTState *s = CADENCE_UART(dev); 443 444 s->r[R_CR] = 0x00000128; 445 s->r[R_IMR] = 0; 446 s->r[R_CISR] = 0; 447 s->r[R_RTRIG] = 0x00000020; 448 s->r[R_BRGR] = 0x0000000F; 449 s->r[R_TTRIG] = 0x00000020; 450 451 uart_rx_reset(s); 452 uart_tx_reset(s); 453 454 uart_update_status(s); 455 } 456 457 static void cadence_uart_realize(DeviceState *dev, Error **errp) 458 { 459 CadenceUARTState *s = CADENCE_UART(dev); 460 461 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 462 fifo_trigger_update, s); 463 464 /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */ 465 s->chr = qemu_char_get_next_serial(); 466 467 if (s->chr) { 468 qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive, 469 uart_event, s); 470 } 471 } 472 473 static void cadence_uart_init(Object *obj) 474 { 475 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 476 CadenceUARTState *s = CADENCE_UART(obj); 477 478 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); 479 sysbus_init_mmio(sbd, &s->iomem); 480 sysbus_init_irq(sbd, &s->irq); 481 482 s->char_tx_time = (get_ticks_per_sec() / 9600) * 10; 483 } 484 485 static int cadence_uart_post_load(void *opaque, int version_id) 486 { 487 CadenceUARTState *s = opaque; 488 489 uart_parameters_setup(s); 490 uart_update_status(s); 491 return 0; 492 } 493 494 static const VMStateDescription vmstate_cadence_uart = { 495 .name = "cadence_uart", 496 .version_id = 2, 497 .minimum_version_id = 2, 498 .post_load = cadence_uart_post_load, 499 .fields = (VMStateField[]) { 500 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX), 501 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState, 502 CADENCE_UART_RX_FIFO_SIZE), 503 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState, 504 CADENCE_UART_TX_FIFO_SIZE), 505 VMSTATE_UINT32(rx_count, CadenceUARTState), 506 VMSTATE_UINT32(tx_count, CadenceUARTState), 507 VMSTATE_UINT32(rx_wpos, CadenceUARTState), 508 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), 509 VMSTATE_END_OF_LIST() 510 } 511 }; 512 513 static void cadence_uart_class_init(ObjectClass *klass, void *data) 514 { 515 DeviceClass *dc = DEVICE_CLASS(klass); 516 517 dc->realize = cadence_uart_realize; 518 dc->vmsd = &vmstate_cadence_uart; 519 dc->reset = cadence_uart_reset; 520 /* Reason: realize() method uses qemu_char_get_next_serial() */ 521 dc->cannot_instantiate_with_device_add_yet = true; 522 } 523 524 static const TypeInfo cadence_uart_info = { 525 .name = TYPE_CADENCE_UART, 526 .parent = TYPE_SYS_BUS_DEVICE, 527 .instance_size = sizeof(CadenceUARTState), 528 .instance_init = cadence_uart_init, 529 .class_init = cadence_uart_class_init, 530 }; 531 532 static void cadence_uart_register_types(void) 533 { 534 type_register_static(&cadence_uart_info); 535 } 536 537 type_init(cadence_uart_register_types) 538