1 /* 2 * Device model for Cadence UART 3 * 4 * Reference: Xilinx Zynq 7000 reference manual 5 * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf 6 * - Chapter 19 UART Controller 7 * - Appendix B for Register details 8 * 9 * Copyright (c) 2010 Xilinx Inc. 10 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 11 * Copyright (c) 2012 PetaLogix Pty Ltd. 12 * Written by Haibing Ma 13 * M.Habib 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/sysbus.h" 26 #include "migration/vmstate.h" 27 #include "chardev/char-fe.h" 28 #include "chardev/char-serial.h" 29 #include "qemu/timer.h" 30 #include "qemu/log.h" 31 #include "qemu/module.h" 32 #include "hw/char/cadence_uart.h" 33 #include "hw/irq.h" 34 35 #ifdef CADENCE_UART_ERR_DEBUG 36 #define DB_PRINT(...) do { \ 37 fprintf(stderr, ": %s: ", __func__); \ 38 fprintf(stderr, ## __VA_ARGS__); \ 39 } while (0) 40 #else 41 #define DB_PRINT(...) 42 #endif 43 44 #define UART_SR_INTR_RTRIG 0x00000001 45 #define UART_SR_INTR_REMPTY 0x00000002 46 #define UART_SR_INTR_RFUL 0x00000004 47 #define UART_SR_INTR_TEMPTY 0x00000008 48 #define UART_SR_INTR_TFUL 0x00000010 49 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ 50 #define UART_SR_TTRIG 0x00002000 51 #define UART_INTR_TTRIG 0x00000400 52 /* bits fields in CSR that correlate to CISR. If any of these bits are set in 53 * SR, then the same bit in CISR is set high too */ 54 #define UART_SR_TO_CISR_MASK 0x0000001F 55 56 #define UART_INTR_ROVR 0x00000020 57 #define UART_INTR_FRAME 0x00000040 58 #define UART_INTR_PARE 0x00000080 59 #define UART_INTR_TIMEOUT 0x00000100 60 #define UART_INTR_DMSI 0x00000200 61 #define UART_INTR_TOVR 0x00001000 62 63 #define UART_SR_RACTIVE 0x00000400 64 #define UART_SR_TACTIVE 0x00000800 65 #define UART_SR_FDELT 0x00001000 66 67 #define UART_CR_RXRST 0x00000001 68 #define UART_CR_TXRST 0x00000002 69 #define UART_CR_RX_EN 0x00000004 70 #define UART_CR_RX_DIS 0x00000008 71 #define UART_CR_TX_EN 0x00000010 72 #define UART_CR_TX_DIS 0x00000020 73 #define UART_CR_RST_TO 0x00000040 74 #define UART_CR_STARTBRK 0x00000080 75 #define UART_CR_STOPBRK 0x00000100 76 77 #define UART_MR_CLKS 0x00000001 78 #define UART_MR_CHRL 0x00000006 79 #define UART_MR_CHRL_SH 1 80 #define UART_MR_PAR 0x00000038 81 #define UART_MR_PAR_SH 3 82 #define UART_MR_NBSTOP 0x000000C0 83 #define UART_MR_NBSTOP_SH 6 84 #define UART_MR_CHMODE 0x00000300 85 #define UART_MR_CHMODE_SH 8 86 #define UART_MR_UCLKEN 0x00000400 87 #define UART_MR_IRMODE 0x00000800 88 89 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) 90 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) 91 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) 92 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) 93 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) 94 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) 95 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) 96 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) 97 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) 98 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) 99 100 #define UART_INPUT_CLK 50000000 101 102 #define R_CR (0x00/4) 103 #define R_MR (0x04/4) 104 #define R_IER (0x08/4) 105 #define R_IDR (0x0C/4) 106 #define R_IMR (0x10/4) 107 #define R_CISR (0x14/4) 108 #define R_BRGR (0x18/4) 109 #define R_RTOR (0x1C/4) 110 #define R_RTRIG (0x20/4) 111 #define R_MCR (0x24/4) 112 #define R_MSR (0x28/4) 113 #define R_SR (0x2C/4) 114 #define R_TX_RX (0x30/4) 115 #define R_BDIV (0x34/4) 116 #define R_FDEL (0x38/4) 117 #define R_PMIN (0x3C/4) 118 #define R_PWID (0x40/4) 119 #define R_TTRIG (0x44/4) 120 121 122 static void uart_update_status(CadenceUARTState *s) 123 { 124 s->r[R_SR] = 0; 125 126 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL 127 : 0; 128 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; 129 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; 130 131 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL 132 : 0; 133 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; 134 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; 135 136 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; 137 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; 138 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); 139 } 140 141 static void fifo_trigger_update(void *opaque) 142 { 143 CadenceUARTState *s = opaque; 144 145 if (s->r[R_RTOR]) { 146 s->r[R_CISR] |= UART_INTR_TIMEOUT; 147 uart_update_status(s); 148 } 149 } 150 151 static void uart_rx_reset(CadenceUARTState *s) 152 { 153 s->rx_wpos = 0; 154 s->rx_count = 0; 155 qemu_chr_fe_accept_input(&s->chr); 156 } 157 158 static void uart_tx_reset(CadenceUARTState *s) 159 { 160 s->tx_count = 0; 161 } 162 163 static void uart_send_breaks(CadenceUARTState *s) 164 { 165 int break_enabled = 1; 166 167 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 168 &break_enabled); 169 } 170 171 static void uart_parameters_setup(CadenceUARTState *s) 172 { 173 QEMUSerialSetParams ssp; 174 unsigned int baud_rate, packet_size; 175 176 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? 177 UART_INPUT_CLK / 8 : UART_INPUT_CLK; 178 179 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); 180 packet_size = 1; 181 182 switch (s->r[R_MR] & UART_MR_PAR) { 183 case UART_PARITY_EVEN: 184 ssp.parity = 'E'; 185 packet_size++; 186 break; 187 case UART_PARITY_ODD: 188 ssp.parity = 'O'; 189 packet_size++; 190 break; 191 default: 192 ssp.parity = 'N'; 193 break; 194 } 195 196 switch (s->r[R_MR] & UART_MR_CHRL) { 197 case UART_DATA_BITS_6: 198 ssp.data_bits = 6; 199 break; 200 case UART_DATA_BITS_7: 201 ssp.data_bits = 7; 202 break; 203 default: 204 ssp.data_bits = 8; 205 break; 206 } 207 208 switch (s->r[R_MR] & UART_MR_NBSTOP) { 209 case UART_STOP_BITS_1: 210 ssp.stop_bits = 1; 211 break; 212 default: 213 ssp.stop_bits = 2; 214 break; 215 } 216 217 packet_size += ssp.data_bits + ssp.stop_bits; 218 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size; 219 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 220 } 221 222 static int uart_can_receive(void *opaque) 223 { 224 CadenceUARTState *s = opaque; 225 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); 226 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 227 228 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 229 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); 230 } 231 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 232 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count); 233 } 234 return ret; 235 } 236 237 static void uart_ctrl_update(CadenceUARTState *s) 238 { 239 if (s->r[R_CR] & UART_CR_TXRST) { 240 uart_tx_reset(s); 241 } 242 243 if (s->r[R_CR] & UART_CR_RXRST) { 244 uart_rx_reset(s); 245 } 246 247 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); 248 249 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { 250 uart_send_breaks(s); 251 } 252 } 253 254 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) 255 { 256 CadenceUARTState *s = opaque; 257 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 258 int i; 259 260 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 261 return; 262 } 263 264 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) { 265 s->r[R_CISR] |= UART_INTR_ROVR; 266 } else { 267 for (i = 0; i < size; i++) { 268 s->rx_fifo[s->rx_wpos] = buf[i]; 269 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE; 270 s->rx_count++; 271 } 272 timer_mod(s->fifo_trigger_handle, new_rx_time + 273 (s->char_tx_time * 4)); 274 } 275 uart_update_status(s); 276 } 277 278 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, 279 void *opaque) 280 { 281 CadenceUARTState *s = opaque; 282 int ret; 283 284 /* instant drain the fifo when there's no back-end */ 285 if (!qemu_chr_fe_backend_connected(&s->chr)) { 286 s->tx_count = 0; 287 return FALSE; 288 } 289 290 if (!s->tx_count) { 291 return FALSE; 292 } 293 294 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count); 295 296 if (ret >= 0) { 297 s->tx_count -= ret; 298 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); 299 } 300 301 if (s->tx_count) { 302 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 303 cadence_uart_xmit, s); 304 if (!r) { 305 s->tx_count = 0; 306 return FALSE; 307 } 308 } 309 310 uart_update_status(s); 311 return FALSE; 312 } 313 314 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, 315 int size) 316 { 317 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { 318 return; 319 } 320 321 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) { 322 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; 323 /* 324 * This can only be a guest error via a bad tx fifo register push, 325 * as can_receive() should stop remote loop and echo modes ever getting 326 * us to here. 327 */ 328 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow"); 329 s->r[R_CISR] |= UART_INTR_ROVR; 330 } 331 332 memcpy(s->tx_fifo + s->tx_count, buf, size); 333 s->tx_count += size; 334 335 cadence_uart_xmit(NULL, G_IO_OUT, s); 336 } 337 338 static void uart_receive(void *opaque, const uint8_t *buf, int size) 339 { 340 CadenceUARTState *s = opaque; 341 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 342 343 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 344 uart_write_rx_fifo(opaque, buf, size); 345 } 346 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 347 uart_write_tx_fifo(s, buf, size); 348 } 349 } 350 351 static void uart_event(void *opaque, QEMUChrEvent event) 352 { 353 CadenceUARTState *s = opaque; 354 uint8_t buf = '\0'; 355 356 if (event == CHR_EVENT_BREAK) { 357 uart_write_rx_fifo(opaque, &buf, 1); 358 } 359 360 uart_update_status(s); 361 } 362 363 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c) 364 { 365 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 366 return; 367 } 368 369 if (s->rx_count) { 370 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos - 371 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE; 372 *c = s->rx_fifo[rx_rpos]; 373 s->rx_count--; 374 375 qemu_chr_fe_accept_input(&s->chr); 376 } else { 377 *c = 0; 378 } 379 380 uart_update_status(s); 381 } 382 383 static void uart_write(void *opaque, hwaddr offset, 384 uint64_t value, unsigned size) 385 { 386 CadenceUARTState *s = opaque; 387 388 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); 389 offset >>= 2; 390 if (offset >= CADENCE_UART_R_MAX) { 391 return; 392 } 393 switch (offset) { 394 case R_IER: /* ier (wts imr) */ 395 s->r[R_IMR] |= value; 396 break; 397 case R_IDR: /* idr (wtc imr) */ 398 s->r[R_IMR] &= ~value; 399 break; 400 case R_IMR: /* imr (read only) */ 401 break; 402 case R_CISR: /* cisr (wtc) */ 403 s->r[R_CISR] &= ~value; 404 break; 405 case R_TX_RX: /* UARTDR */ 406 switch (s->r[R_MR] & UART_MR_CHMODE) { 407 case NORMAL_MODE: 408 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 409 break; 410 case LOCAL_LOOPBACK: 411 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1); 412 break; 413 } 414 break; 415 case R_BRGR: /* Baud rate generator */ 416 if (value >= 0x01) { 417 s->r[offset] = value & 0xFFFF; 418 } 419 break; 420 case R_BDIV: /* Baud rate divider */ 421 if (value >= 0x04) { 422 s->r[offset] = value & 0xFF; 423 } 424 break; 425 default: 426 s->r[offset] = value; 427 } 428 429 switch (offset) { 430 case R_CR: 431 uart_ctrl_update(s); 432 break; 433 case R_MR: 434 uart_parameters_setup(s); 435 break; 436 } 437 uart_update_status(s); 438 } 439 440 static uint64_t uart_read(void *opaque, hwaddr offset, 441 unsigned size) 442 { 443 CadenceUARTState *s = opaque; 444 uint32_t c = 0; 445 446 offset >>= 2; 447 if (offset >= CADENCE_UART_R_MAX) { 448 c = 0; 449 } else if (offset == R_TX_RX) { 450 uart_read_rx_fifo(s, &c); 451 } else { 452 c = s->r[offset]; 453 } 454 455 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); 456 return c; 457 } 458 459 static const MemoryRegionOps uart_ops = { 460 .read = uart_read, 461 .write = uart_write, 462 .endianness = DEVICE_NATIVE_ENDIAN, 463 }; 464 465 static void cadence_uart_reset(DeviceState *dev) 466 { 467 CadenceUARTState *s = CADENCE_UART(dev); 468 469 s->r[R_CR] = 0x00000128; 470 s->r[R_IMR] = 0; 471 s->r[R_CISR] = 0; 472 s->r[R_RTRIG] = 0x00000020; 473 s->r[R_BRGR] = 0x0000028B; 474 s->r[R_BDIV] = 0x0000000F; 475 s->r[R_TTRIG] = 0x00000020; 476 477 uart_rx_reset(s); 478 uart_tx_reset(s); 479 480 uart_update_status(s); 481 } 482 483 static void cadence_uart_realize(DeviceState *dev, Error **errp) 484 { 485 CadenceUARTState *s = CADENCE_UART(dev); 486 487 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 488 fifo_trigger_update, s); 489 490 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, 491 uart_event, NULL, s, NULL, true); 492 } 493 494 static void cadence_uart_init(Object *obj) 495 { 496 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 497 CadenceUARTState *s = CADENCE_UART(obj); 498 499 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); 500 sysbus_init_mmio(sbd, &s->iomem); 501 sysbus_init_irq(sbd, &s->irq); 502 503 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; 504 } 505 506 static int cadence_uart_post_load(void *opaque, int version_id) 507 { 508 CadenceUARTState *s = opaque; 509 510 /* Ensure these two aren't invalid numbers */ 511 if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF || 512 s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) { 513 /* Value is invalid, abort */ 514 return 1; 515 } 516 517 uart_parameters_setup(s); 518 uart_update_status(s); 519 return 0; 520 } 521 522 static const VMStateDescription vmstate_cadence_uart = { 523 .name = "cadence_uart", 524 .version_id = 2, 525 .minimum_version_id = 2, 526 .post_load = cadence_uart_post_load, 527 .fields = (VMStateField[]) { 528 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX), 529 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState, 530 CADENCE_UART_RX_FIFO_SIZE), 531 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState, 532 CADENCE_UART_TX_FIFO_SIZE), 533 VMSTATE_UINT32(rx_count, CadenceUARTState), 534 VMSTATE_UINT32(tx_count, CadenceUARTState), 535 VMSTATE_UINT32(rx_wpos, CadenceUARTState), 536 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), 537 VMSTATE_END_OF_LIST() 538 } 539 }; 540 541 static Property cadence_uart_properties[] = { 542 DEFINE_PROP_CHR("chardev", CadenceUARTState, chr), 543 DEFINE_PROP_END_OF_LIST(), 544 }; 545 546 static void cadence_uart_class_init(ObjectClass *klass, void *data) 547 { 548 DeviceClass *dc = DEVICE_CLASS(klass); 549 550 dc->realize = cadence_uart_realize; 551 dc->vmsd = &vmstate_cadence_uart; 552 dc->reset = cadence_uart_reset; 553 device_class_set_props(dc, cadence_uart_properties); 554 } 555 556 static const TypeInfo cadence_uart_info = { 557 .name = TYPE_CADENCE_UART, 558 .parent = TYPE_SYS_BUS_DEVICE, 559 .instance_size = sizeof(CadenceUARTState), 560 .instance_init = cadence_uart_init, 561 .class_init = cadence_uart_class_init, 562 }; 563 564 static void cadence_uart_register_types(void) 565 { 566 type_register_static(&cadence_uart_info); 567 } 568 569 type_init(cadence_uart_register_types) 570