xref: /openbmc/qemu/hw/char/cadence_uart.c (revision 2993683b)
1 /*
2  * Device model for Cadence UART
3  *
4  * Copyright (c) 2010 Xilinx Inc.
5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
6  * Copyright (c) 2012 PetaLogix Pty Ltd.
7  * Written by Haibing Ma
8  *            M.Habib
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version
13  * 2 of the License, or (at your option) any later version.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #include "hw/sysbus.h"
20 #include "sysemu/char.h"
21 #include "qemu/timer.h"
22 
23 #ifdef CADENCE_UART_ERR_DEBUG
24 #define DB_PRINT(...) do { \
25     fprintf(stderr,  ": %s: ", __func__); \
26     fprintf(stderr, ## __VA_ARGS__); \
27     } while (0);
28 #else
29     #define DB_PRINT(...)
30 #endif
31 
32 #define UART_SR_INTR_RTRIG     0x00000001
33 #define UART_SR_INTR_REMPTY    0x00000002
34 #define UART_SR_INTR_RFUL      0x00000004
35 #define UART_SR_INTR_TEMPTY    0x00000008
36 #define UART_SR_INTR_TFUL      0x00000010
37 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
38  * SR, then the same bit in CISR is set high too */
39 #define UART_SR_TO_CISR_MASK   0x0000001F
40 
41 #define UART_INTR_ROVR         0x00000020
42 #define UART_INTR_FRAME        0x00000040
43 #define UART_INTR_PARE         0x00000080
44 #define UART_INTR_TIMEOUT      0x00000100
45 #define UART_INTR_DMSI         0x00000200
46 
47 #define UART_SR_RACTIVE    0x00000400
48 #define UART_SR_TACTIVE    0x00000800
49 #define UART_SR_FDELT      0x00001000
50 
51 #define UART_CR_RXRST       0x00000001
52 #define UART_CR_TXRST       0x00000002
53 #define UART_CR_RX_EN       0x00000004
54 #define UART_CR_RX_DIS      0x00000008
55 #define UART_CR_TX_EN       0x00000010
56 #define UART_CR_TX_DIS      0x00000020
57 #define UART_CR_RST_TO      0x00000040
58 #define UART_CR_STARTBRK    0x00000080
59 #define UART_CR_STOPBRK     0x00000100
60 
61 #define UART_MR_CLKS            0x00000001
62 #define UART_MR_CHRL            0x00000006
63 #define UART_MR_CHRL_SH         1
64 #define UART_MR_PAR             0x00000038
65 #define UART_MR_PAR_SH          3
66 #define UART_MR_NBSTOP          0x000000C0
67 #define UART_MR_NBSTOP_SH       6
68 #define UART_MR_CHMODE          0x00000300
69 #define UART_MR_CHMODE_SH       8
70 #define UART_MR_UCLKEN          0x00000400
71 #define UART_MR_IRMODE          0x00000800
72 
73 #define UART_DATA_BITS_6       (0x3 << UART_MR_CHRL_SH)
74 #define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
75 #define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
76 #define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
77 #define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
78 #define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
79 #define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
80 #define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)
81 #define LOCAL_LOOPBACK         (0x2 << UART_MR_CHMODE_SH)
82 #define REMOTE_LOOPBACK        (0x3 << UART_MR_CHMODE_SH)
83 
84 #define RX_FIFO_SIZE           16
85 #define TX_FIFO_SIZE           16
86 #define UART_INPUT_CLK         50000000
87 
88 #define R_CR       (0x00/4)
89 #define R_MR       (0x04/4)
90 #define R_IER      (0x08/4)
91 #define R_IDR      (0x0C/4)
92 #define R_IMR      (0x10/4)
93 #define R_CISR     (0x14/4)
94 #define R_BRGR     (0x18/4)
95 #define R_RTOR     (0x1C/4)
96 #define R_RTRIG    (0x20/4)
97 #define R_MCR      (0x24/4)
98 #define R_MSR      (0x28/4)
99 #define R_SR       (0x2C/4)
100 #define R_TX_RX    (0x30/4)
101 #define R_BDIV     (0x34/4)
102 #define R_FDEL     (0x38/4)
103 #define R_PMIN     (0x3C/4)
104 #define R_PWID     (0x40/4)
105 #define R_TTRIG    (0x44/4)
106 
107 #define R_MAX (R_TTRIG + 1)
108 
109 typedef struct {
110     SysBusDevice busdev;
111     MemoryRegion iomem;
112     uint32_t r[R_MAX];
113     uint8_t r_fifo[RX_FIFO_SIZE];
114     uint32_t rx_wpos;
115     uint32_t rx_count;
116     uint64_t char_tx_time;
117     CharDriverState *chr;
118     qemu_irq irq;
119     struct QEMUTimer *fifo_trigger_handle;
120     struct QEMUTimer *tx_time_handle;
121 } UartState;
122 
123 static void uart_update_status(UartState *s)
124 {
125     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
126     qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
127 }
128 
129 static void fifo_trigger_update(void *opaque)
130 {
131     UartState *s = (UartState *)opaque;
132 
133     s->r[R_CISR] |= UART_INTR_TIMEOUT;
134 
135     uart_update_status(s);
136 }
137 
138 static void uart_tx_redo(UartState *s)
139 {
140     uint64_t new_tx_time = qemu_get_clock_ns(vm_clock);
141 
142     qemu_mod_timer(s->tx_time_handle, new_tx_time + s->char_tx_time);
143 
144     s->r[R_SR] |= UART_SR_INTR_TEMPTY;
145 
146     uart_update_status(s);
147 }
148 
149 static void uart_tx_write(void *opaque)
150 {
151     UartState *s = (UartState *)opaque;
152 
153     uart_tx_redo(s);
154 }
155 
156 static void uart_rx_reset(UartState *s)
157 {
158     s->rx_wpos = 0;
159     s->rx_count = 0;
160     qemu_chr_accept_input(s->chr);
161 
162     s->r[R_SR] |= UART_SR_INTR_REMPTY;
163     s->r[R_SR] &= ~UART_SR_INTR_RFUL;
164 }
165 
166 static void uart_tx_reset(UartState *s)
167 {
168     s->r[R_SR] |= UART_SR_INTR_TEMPTY;
169     s->r[R_SR] &= ~UART_SR_INTR_TFUL;
170 }
171 
172 static void uart_send_breaks(UartState *s)
173 {
174     int break_enabled = 1;
175 
176     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
177                                &break_enabled);
178 }
179 
180 static void uart_parameters_setup(UartState *s)
181 {
182     QEMUSerialSetParams ssp;
183     unsigned int baud_rate, packet_size;
184 
185     baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
186             UART_INPUT_CLK / 8 : UART_INPUT_CLK;
187 
188     ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
189     packet_size = 1;
190 
191     switch (s->r[R_MR] & UART_MR_PAR) {
192     case UART_PARITY_EVEN:
193         ssp.parity = 'E';
194         packet_size++;
195         break;
196     case UART_PARITY_ODD:
197         ssp.parity = 'O';
198         packet_size++;
199         break;
200     default:
201         ssp.parity = 'N';
202         break;
203     }
204 
205     switch (s->r[R_MR] & UART_MR_CHRL) {
206     case UART_DATA_BITS_6:
207         ssp.data_bits = 6;
208         break;
209     case UART_DATA_BITS_7:
210         ssp.data_bits = 7;
211         break;
212     default:
213         ssp.data_bits = 8;
214         break;
215     }
216 
217     switch (s->r[R_MR] & UART_MR_NBSTOP) {
218     case UART_STOP_BITS_1:
219         ssp.stop_bits = 1;
220         break;
221     default:
222         ssp.stop_bits = 2;
223         break;
224     }
225 
226     packet_size += ssp.data_bits + ssp.stop_bits;
227     s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size;
228     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
229 }
230 
231 static int uart_can_receive(void *opaque)
232 {
233     UartState *s = (UartState *)opaque;
234 
235     return RX_FIFO_SIZE - s->rx_count;
236 }
237 
238 static void uart_ctrl_update(UartState *s)
239 {
240     if (s->r[R_CR] & UART_CR_TXRST) {
241         uart_tx_reset(s);
242     }
243 
244     if (s->r[R_CR] & UART_CR_RXRST) {
245         uart_rx_reset(s);
246     }
247 
248     s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
249 
250     if ((s->r[R_CR] & UART_CR_TX_EN) && !(s->r[R_CR] & UART_CR_TX_DIS)) {
251             uart_tx_redo(s);
252     }
253 
254     if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
255         uart_send_breaks(s);
256     }
257 }
258 
259 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
260 {
261     UartState *s = (UartState *)opaque;
262     uint64_t new_rx_time = qemu_get_clock_ns(vm_clock);
263     int i;
264 
265     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
266         return;
267     }
268 
269     s->r[R_SR] &= ~UART_SR_INTR_REMPTY;
270 
271     if (s->rx_count == RX_FIFO_SIZE) {
272         s->r[R_CISR] |= UART_INTR_ROVR;
273     } else {
274         for (i = 0; i < size; i++) {
275             s->r_fifo[s->rx_wpos] = buf[i];
276             s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
277             s->rx_count++;
278 
279             if (s->rx_count == RX_FIFO_SIZE) {
280                 s->r[R_SR] |= UART_SR_INTR_RFUL;
281                 break;
282             }
283 
284             if (s->rx_count >= s->r[R_RTRIG]) {
285                 s->r[R_SR] |= UART_SR_INTR_RTRIG;
286             }
287         }
288         qemu_mod_timer(s->fifo_trigger_handle, new_rx_time +
289                                                 (s->char_tx_time * 4));
290     }
291     uart_update_status(s);
292 }
293 
294 static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
295 {
296     if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
297         return;
298     }
299 
300     while (size) {
301         size -= qemu_chr_fe_write(s->chr, buf, size);
302     }
303 }
304 
305 static void uart_receive(void *opaque, const uint8_t *buf, int size)
306 {
307     UartState *s = (UartState *)opaque;
308     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
309 
310     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
311         uart_write_rx_fifo(opaque, buf, size);
312     }
313     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
314         uart_write_tx_fifo(s, buf, size);
315     }
316 }
317 
318 static void uart_event(void *opaque, int event)
319 {
320     UartState *s = (UartState *)opaque;
321     uint8_t buf = '\0';
322 
323     if (event == CHR_EVENT_BREAK) {
324         uart_write_rx_fifo(opaque, &buf, 1);
325     }
326 
327     uart_update_status(s);
328 }
329 
330 static void uart_read_rx_fifo(UartState *s, uint32_t *c)
331 {
332     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
333         return;
334     }
335 
336     s->r[R_SR] &= ~UART_SR_INTR_RFUL;
337 
338     if (s->rx_count) {
339         uint32_t rx_rpos =
340                 (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
341         *c = s->r_fifo[rx_rpos];
342         s->rx_count--;
343 
344         if (!s->rx_count) {
345             s->r[R_SR] |= UART_SR_INTR_REMPTY;
346         }
347         qemu_chr_accept_input(s->chr);
348     } else {
349         *c = 0;
350         s->r[R_SR] |= UART_SR_INTR_REMPTY;
351     }
352 
353     if (s->rx_count < s->r[R_RTRIG]) {
354         s->r[R_SR] &= ~UART_SR_INTR_RTRIG;
355     }
356     uart_update_status(s);
357 }
358 
359 static void uart_write(void *opaque, hwaddr offset,
360                           uint64_t value, unsigned size)
361 {
362     UartState *s = (UartState *)opaque;
363 
364     DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
365     offset >>= 2;
366     switch (offset) {
367     case R_IER: /* ier (wts imr) */
368         s->r[R_IMR] |= value;
369         break;
370     case R_IDR: /* idr (wtc imr) */
371         s->r[R_IMR] &= ~value;
372         break;
373     case R_IMR: /* imr (read only) */
374         break;
375     case R_CISR: /* cisr (wtc) */
376         s->r[R_CISR] &= ~value;
377         break;
378     case R_TX_RX: /* UARTDR */
379         switch (s->r[R_MR] & UART_MR_CHMODE) {
380         case NORMAL_MODE:
381             uart_write_tx_fifo(s, (uint8_t *) &value, 1);
382             break;
383         case LOCAL_LOOPBACK:
384             uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
385             break;
386         }
387         break;
388     default:
389         s->r[offset] = value;
390     }
391 
392     switch (offset) {
393     case R_CR:
394         uart_ctrl_update(s);
395         break;
396     case R_MR:
397         uart_parameters_setup(s);
398         break;
399     }
400 }
401 
402 static uint64_t uart_read(void *opaque, hwaddr offset,
403         unsigned size)
404 {
405     UartState *s = (UartState *)opaque;
406     uint32_t c = 0;
407 
408     offset >>= 2;
409     if (offset >= R_MAX) {
410         c = 0;
411     } else if (offset == R_TX_RX) {
412         uart_read_rx_fifo(s, &c);
413     } else {
414        c = s->r[offset];
415     }
416 
417     DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
418     return c;
419 }
420 
421 static const MemoryRegionOps uart_ops = {
422     .read = uart_read,
423     .write = uart_write,
424     .endianness = DEVICE_NATIVE_ENDIAN,
425 };
426 
427 static void cadence_uart_reset(UartState *s)
428 {
429     s->r[R_CR] = 0x00000128;
430     s->r[R_IMR] = 0;
431     s->r[R_CISR] = 0;
432     s->r[R_RTRIG] = 0x00000020;
433     s->r[R_BRGR] = 0x0000000F;
434     s->r[R_TTRIG] = 0x00000020;
435 
436     uart_rx_reset(s);
437     uart_tx_reset(s);
438 
439     s->rx_count = 0;
440     s->rx_wpos = 0;
441 }
442 
443 static int cadence_uart_init(SysBusDevice *dev)
444 {
445     UartState *s = FROM_SYSBUS(UartState, dev);
446 
447     memory_region_init_io(&s->iomem, &uart_ops, s, "uart", 0x1000);
448     sysbus_init_mmio(dev, &s->iomem);
449     sysbus_init_irq(dev, &s->irq);
450 
451     s->fifo_trigger_handle = qemu_new_timer_ns(vm_clock,
452             (QEMUTimerCB *)fifo_trigger_update, s);
453 
454     s->tx_time_handle = qemu_new_timer_ns(vm_clock,
455             (QEMUTimerCB *)uart_tx_write, s);
456 
457     s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;
458 
459     s->chr = qemu_char_get_next_serial();
460 
461     cadence_uart_reset(s);
462 
463     if (s->chr) {
464         qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
465                               uart_event, s);
466     }
467 
468     return 0;
469 }
470 
471 static int cadence_uart_post_load(void *opaque, int version_id)
472 {
473     UartState *s = opaque;
474 
475     uart_parameters_setup(s);
476     uart_update_status(s);
477     return 0;
478 }
479 
480 static const VMStateDescription vmstate_cadence_uart = {
481     .name = "cadence_uart",
482     .version_id = 1,
483     .minimum_version_id = 1,
484     .minimum_version_id_old = 1,
485     .post_load = cadence_uart_post_load,
486     .fields = (VMStateField[]) {
487         VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
488         VMSTATE_UINT8_ARRAY(r_fifo, UartState, RX_FIFO_SIZE),
489         VMSTATE_UINT32(rx_count, UartState),
490         VMSTATE_UINT32(rx_wpos, UartState),
491         VMSTATE_TIMER(fifo_trigger_handle, UartState),
492         VMSTATE_TIMER(tx_time_handle, UartState),
493         VMSTATE_END_OF_LIST()
494     }
495 };
496 
497 static void cadence_uart_class_init(ObjectClass *klass, void *data)
498 {
499     DeviceClass *dc = DEVICE_CLASS(klass);
500     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
501 
502     sdc->init = cadence_uart_init;
503     dc->vmsd = &vmstate_cadence_uart;
504 }
505 
506 static const TypeInfo cadence_uart_info = {
507     .name          = "cadence_uart",
508     .parent        = TYPE_SYS_BUS_DEVICE,
509     .instance_size = sizeof(UartState),
510     .class_init    = cadence_uart_class_init,
511 };
512 
513 static void cadence_uart_register_types(void)
514 {
515     type_register_static(&cadence_uart_info);
516 }
517 
518 type_init(cadence_uart_register_types)
519