1 /* 2 * Device model for Cadence UART 3 * 4 * Reference: Xilinx Zynq 7000 reference manual 5 * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf 6 * - Chapter 19 UART Controller 7 * - Appendix B for Register details 8 * 9 * Copyright (c) 2010 Xilinx Inc. 10 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) 11 * Copyright (c) 2012 PetaLogix Pty Ltd. 12 * Written by Haibing Ma 13 * M.Habib 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 18 * 2 of the License, or (at your option) any later version. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/sysbus.h" 26 #include "chardev/char-fe.h" 27 #include "chardev/char-serial.h" 28 #include "qemu/timer.h" 29 #include "qemu/log.h" 30 #include "hw/char/cadence_uart.h" 31 32 #ifdef CADENCE_UART_ERR_DEBUG 33 #define DB_PRINT(...) do { \ 34 fprintf(stderr, ": %s: ", __func__); \ 35 fprintf(stderr, ## __VA_ARGS__); \ 36 } while (0); 37 #else 38 #define DB_PRINT(...) 39 #endif 40 41 #define UART_SR_INTR_RTRIG 0x00000001 42 #define UART_SR_INTR_REMPTY 0x00000002 43 #define UART_SR_INTR_RFUL 0x00000004 44 #define UART_SR_INTR_TEMPTY 0x00000008 45 #define UART_SR_INTR_TFUL 0x00000010 46 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ 47 #define UART_SR_TTRIG 0x00002000 48 #define UART_INTR_TTRIG 0x00000400 49 /* bits fields in CSR that correlate to CISR. If any of these bits are set in 50 * SR, then the same bit in CISR is set high too */ 51 #define UART_SR_TO_CISR_MASK 0x0000001F 52 53 #define UART_INTR_ROVR 0x00000020 54 #define UART_INTR_FRAME 0x00000040 55 #define UART_INTR_PARE 0x00000080 56 #define UART_INTR_TIMEOUT 0x00000100 57 #define UART_INTR_DMSI 0x00000200 58 #define UART_INTR_TOVR 0x00001000 59 60 #define UART_SR_RACTIVE 0x00000400 61 #define UART_SR_TACTIVE 0x00000800 62 #define UART_SR_FDELT 0x00001000 63 64 #define UART_CR_RXRST 0x00000001 65 #define UART_CR_TXRST 0x00000002 66 #define UART_CR_RX_EN 0x00000004 67 #define UART_CR_RX_DIS 0x00000008 68 #define UART_CR_TX_EN 0x00000010 69 #define UART_CR_TX_DIS 0x00000020 70 #define UART_CR_RST_TO 0x00000040 71 #define UART_CR_STARTBRK 0x00000080 72 #define UART_CR_STOPBRK 0x00000100 73 74 #define UART_MR_CLKS 0x00000001 75 #define UART_MR_CHRL 0x00000006 76 #define UART_MR_CHRL_SH 1 77 #define UART_MR_PAR 0x00000038 78 #define UART_MR_PAR_SH 3 79 #define UART_MR_NBSTOP 0x000000C0 80 #define UART_MR_NBSTOP_SH 6 81 #define UART_MR_CHMODE 0x00000300 82 #define UART_MR_CHMODE_SH 8 83 #define UART_MR_UCLKEN 0x00000400 84 #define UART_MR_IRMODE 0x00000800 85 86 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH) 87 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH) 88 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH) 89 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH) 90 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH) 91 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH) 92 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH) 93 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH) 94 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) 95 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) 96 97 #define UART_INPUT_CLK 50000000 98 99 #define R_CR (0x00/4) 100 #define R_MR (0x04/4) 101 #define R_IER (0x08/4) 102 #define R_IDR (0x0C/4) 103 #define R_IMR (0x10/4) 104 #define R_CISR (0x14/4) 105 #define R_BRGR (0x18/4) 106 #define R_RTOR (0x1C/4) 107 #define R_RTRIG (0x20/4) 108 #define R_MCR (0x24/4) 109 #define R_MSR (0x28/4) 110 #define R_SR (0x2C/4) 111 #define R_TX_RX (0x30/4) 112 #define R_BDIV (0x34/4) 113 #define R_FDEL (0x38/4) 114 #define R_PMIN (0x3C/4) 115 #define R_PWID (0x40/4) 116 #define R_TTRIG (0x44/4) 117 118 119 static void uart_update_status(CadenceUARTState *s) 120 { 121 s->r[R_SR] = 0; 122 123 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL 124 : 0; 125 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; 126 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; 127 128 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL 129 : 0; 130 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; 131 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; 132 133 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; 134 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0; 135 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); 136 } 137 138 static void fifo_trigger_update(void *opaque) 139 { 140 CadenceUARTState *s = opaque; 141 142 if (s->r[R_RTOR]) { 143 s->r[R_CISR] |= UART_INTR_TIMEOUT; 144 uart_update_status(s); 145 } 146 } 147 148 static void uart_rx_reset(CadenceUARTState *s) 149 { 150 s->rx_wpos = 0; 151 s->rx_count = 0; 152 qemu_chr_fe_accept_input(&s->chr); 153 } 154 155 static void uart_tx_reset(CadenceUARTState *s) 156 { 157 s->tx_count = 0; 158 } 159 160 static void uart_send_breaks(CadenceUARTState *s) 161 { 162 int break_enabled = 1; 163 164 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, 165 &break_enabled); 166 } 167 168 static void uart_parameters_setup(CadenceUARTState *s) 169 { 170 QEMUSerialSetParams ssp; 171 unsigned int baud_rate, packet_size; 172 173 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ? 174 UART_INPUT_CLK / 8 : UART_INPUT_CLK; 175 176 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); 177 packet_size = 1; 178 179 switch (s->r[R_MR] & UART_MR_PAR) { 180 case UART_PARITY_EVEN: 181 ssp.parity = 'E'; 182 packet_size++; 183 break; 184 case UART_PARITY_ODD: 185 ssp.parity = 'O'; 186 packet_size++; 187 break; 188 default: 189 ssp.parity = 'N'; 190 break; 191 } 192 193 switch (s->r[R_MR] & UART_MR_CHRL) { 194 case UART_DATA_BITS_6: 195 ssp.data_bits = 6; 196 break; 197 case UART_DATA_BITS_7: 198 ssp.data_bits = 7; 199 break; 200 default: 201 ssp.data_bits = 8; 202 break; 203 } 204 205 switch (s->r[R_MR] & UART_MR_NBSTOP) { 206 case UART_STOP_BITS_1: 207 ssp.stop_bits = 1; 208 break; 209 default: 210 ssp.stop_bits = 2; 211 break; 212 } 213 214 packet_size += ssp.data_bits + ssp.stop_bits; 215 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size; 216 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); 217 } 218 219 static int uart_can_receive(void *opaque) 220 { 221 CadenceUARTState *s = opaque; 222 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); 223 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 224 225 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 226 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); 227 } 228 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 229 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count); 230 } 231 return ret; 232 } 233 234 static void uart_ctrl_update(CadenceUARTState *s) 235 { 236 if (s->r[R_CR] & UART_CR_TXRST) { 237 uart_tx_reset(s); 238 } 239 240 if (s->r[R_CR] & UART_CR_RXRST) { 241 uart_rx_reset(s); 242 } 243 244 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST); 245 246 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) { 247 uart_send_breaks(s); 248 } 249 } 250 251 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) 252 { 253 CadenceUARTState *s = opaque; 254 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 255 int i; 256 257 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 258 return; 259 } 260 261 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) { 262 s->r[R_CISR] |= UART_INTR_ROVR; 263 } else { 264 for (i = 0; i < size; i++) { 265 s->rx_fifo[s->rx_wpos] = buf[i]; 266 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE; 267 s->rx_count++; 268 } 269 timer_mod(s->fifo_trigger_handle, new_rx_time + 270 (s->char_tx_time * 4)); 271 } 272 uart_update_status(s); 273 } 274 275 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, 276 void *opaque) 277 { 278 CadenceUARTState *s = opaque; 279 int ret; 280 281 /* instant drain the fifo when there's no back-end */ 282 if (!qemu_chr_fe_backend_connected(&s->chr)) { 283 s->tx_count = 0; 284 return FALSE; 285 } 286 287 if (!s->tx_count) { 288 return FALSE; 289 } 290 291 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count); 292 293 if (ret >= 0) { 294 s->tx_count -= ret; 295 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); 296 } 297 298 if (s->tx_count) { 299 guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, 300 cadence_uart_xmit, s); 301 if (!r) { 302 s->tx_count = 0; 303 return FALSE; 304 } 305 } 306 307 uart_update_status(s); 308 return FALSE; 309 } 310 311 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, 312 int size) 313 { 314 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { 315 return; 316 } 317 318 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) { 319 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; 320 /* 321 * This can only be a guest error via a bad tx fifo register push, 322 * as can_receive() should stop remote loop and echo modes ever getting 323 * us to here. 324 */ 325 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow"); 326 s->r[R_CISR] |= UART_INTR_ROVR; 327 } 328 329 memcpy(s->tx_fifo + s->tx_count, buf, size); 330 s->tx_count += size; 331 332 cadence_uart_xmit(NULL, G_IO_OUT, s); 333 } 334 335 static void uart_receive(void *opaque, const uint8_t *buf, int size) 336 { 337 CadenceUARTState *s = opaque; 338 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; 339 340 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { 341 uart_write_rx_fifo(opaque, buf, size); 342 } 343 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) { 344 uart_write_tx_fifo(s, buf, size); 345 } 346 } 347 348 static void uart_event(void *opaque, int event) 349 { 350 CadenceUARTState *s = opaque; 351 uint8_t buf = '\0'; 352 353 if (event == CHR_EVENT_BREAK) { 354 uart_write_rx_fifo(opaque, &buf, 1); 355 } 356 357 uart_update_status(s); 358 } 359 360 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c) 361 { 362 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { 363 return; 364 } 365 366 if (s->rx_count) { 367 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos - 368 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE; 369 *c = s->rx_fifo[rx_rpos]; 370 s->rx_count--; 371 372 qemu_chr_fe_accept_input(&s->chr); 373 } else { 374 *c = 0; 375 } 376 377 uart_update_status(s); 378 } 379 380 static void uart_write(void *opaque, hwaddr offset, 381 uint64_t value, unsigned size) 382 { 383 CadenceUARTState *s = opaque; 384 385 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); 386 offset >>= 2; 387 if (offset >= CADENCE_UART_R_MAX) { 388 return; 389 } 390 switch (offset) { 391 case R_IER: /* ier (wts imr) */ 392 s->r[R_IMR] |= value; 393 break; 394 case R_IDR: /* idr (wtc imr) */ 395 s->r[R_IMR] &= ~value; 396 break; 397 case R_IMR: /* imr (read only) */ 398 break; 399 case R_CISR: /* cisr (wtc) */ 400 s->r[R_CISR] &= ~value; 401 break; 402 case R_TX_RX: /* UARTDR */ 403 switch (s->r[R_MR] & UART_MR_CHMODE) { 404 case NORMAL_MODE: 405 uart_write_tx_fifo(s, (uint8_t *) &value, 1); 406 break; 407 case LOCAL_LOOPBACK: 408 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1); 409 break; 410 } 411 break; 412 case R_BRGR: /* Baud rate generator */ 413 if (value >= 0x01) { 414 s->r[offset] = value & 0xFFFF; 415 } 416 break; 417 case R_BDIV: /* Baud rate divider */ 418 if (value >= 0x04) { 419 s->r[offset] = value & 0xFF; 420 } 421 break; 422 default: 423 s->r[offset] = value; 424 } 425 426 switch (offset) { 427 case R_CR: 428 uart_ctrl_update(s); 429 break; 430 case R_MR: 431 uart_parameters_setup(s); 432 break; 433 } 434 uart_update_status(s); 435 } 436 437 static uint64_t uart_read(void *opaque, hwaddr offset, 438 unsigned size) 439 { 440 CadenceUARTState *s = opaque; 441 uint32_t c = 0; 442 443 offset >>= 2; 444 if (offset >= CADENCE_UART_R_MAX) { 445 c = 0; 446 } else if (offset == R_TX_RX) { 447 uart_read_rx_fifo(s, &c); 448 } else { 449 c = s->r[offset]; 450 } 451 452 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); 453 return c; 454 } 455 456 static const MemoryRegionOps uart_ops = { 457 .read = uart_read, 458 .write = uart_write, 459 .endianness = DEVICE_NATIVE_ENDIAN, 460 }; 461 462 static void cadence_uart_reset(DeviceState *dev) 463 { 464 CadenceUARTState *s = CADENCE_UART(dev); 465 466 s->r[R_CR] = 0x00000128; 467 s->r[R_IMR] = 0; 468 s->r[R_CISR] = 0; 469 s->r[R_RTRIG] = 0x00000020; 470 s->r[R_BRGR] = 0x0000028B; 471 s->r[R_BDIV] = 0x0000000F; 472 s->r[R_TTRIG] = 0x00000020; 473 474 uart_rx_reset(s); 475 uart_tx_reset(s); 476 477 uart_update_status(s); 478 } 479 480 static void cadence_uart_realize(DeviceState *dev, Error **errp) 481 { 482 CadenceUARTState *s = CADENCE_UART(dev); 483 484 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, 485 fifo_trigger_update, s); 486 487 qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive, 488 uart_event, NULL, s, NULL, true); 489 } 490 491 static void cadence_uart_init(Object *obj) 492 { 493 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 494 CadenceUARTState *s = CADENCE_UART(obj); 495 496 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); 497 sysbus_init_mmio(sbd, &s->iomem); 498 sysbus_init_irq(sbd, &s->irq); 499 500 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; 501 } 502 503 static int cadence_uart_post_load(void *opaque, int version_id) 504 { 505 CadenceUARTState *s = opaque; 506 507 /* Ensure these two aren't invalid numbers */ 508 if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF || 509 s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) { 510 /* Value is invalid, abort */ 511 return 1; 512 } 513 514 uart_parameters_setup(s); 515 uart_update_status(s); 516 return 0; 517 } 518 519 static const VMStateDescription vmstate_cadence_uart = { 520 .name = "cadence_uart", 521 .version_id = 2, 522 .minimum_version_id = 2, 523 .post_load = cadence_uart_post_load, 524 .fields = (VMStateField[]) { 525 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX), 526 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState, 527 CADENCE_UART_RX_FIFO_SIZE), 528 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState, 529 CADENCE_UART_TX_FIFO_SIZE), 530 VMSTATE_UINT32(rx_count, CadenceUARTState), 531 VMSTATE_UINT32(tx_count, CadenceUARTState), 532 VMSTATE_UINT32(rx_wpos, CadenceUARTState), 533 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), 534 VMSTATE_END_OF_LIST() 535 } 536 }; 537 538 static Property cadence_uart_properties[] = { 539 DEFINE_PROP_CHR("chardev", CadenceUARTState, chr), 540 DEFINE_PROP_END_OF_LIST(), 541 }; 542 543 static void cadence_uart_class_init(ObjectClass *klass, void *data) 544 { 545 DeviceClass *dc = DEVICE_CLASS(klass); 546 547 dc->realize = cadence_uart_realize; 548 dc->vmsd = &vmstate_cadence_uart; 549 dc->reset = cadence_uart_reset; 550 dc->props = cadence_uart_properties; 551 } 552 553 static const TypeInfo cadence_uart_info = { 554 .name = TYPE_CADENCE_UART, 555 .parent = TYPE_SYS_BUS_DEVICE, 556 .instance_size = sizeof(CadenceUARTState), 557 .instance_init = cadence_uart_init, 558 .class_init = cadence_uart_class_init, 559 }; 560 561 static void cadence_uart_register_types(void) 562 { 563 type_register_static(&cadence_uart_info); 564 } 565 566 type_init(cadence_uart_register_types) 567