1 /* 2 * BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI). 3 * Copyright (c) 2015, Microsoft 4 * Written by Andrew Baumann 5 * Based on pl011.c, copyright terms below: 6 * 7 * Arm PrimeCell PL011 UART 8 * 9 * Copyright (c) 2006 CodeSourcery. 10 * Written by Paul Brook 11 * 12 * This code is licensed under the GPL. 13 * 14 * At present only the core UART functions (data path for tx/rx) are 15 * implemented. The following features/registers are unimplemented: 16 * - Line/modem control 17 * - Scratch register 18 * - Extra control 19 * - Baudrate 20 * - SPI interfaces 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/char/bcm2835_aux.h" 25 #include "qemu/log.h" 26 27 #define AUX_IRQ 0x0 28 #define AUX_ENABLES 0x4 29 #define AUX_MU_IO_REG 0x40 30 #define AUX_MU_IER_REG 0x44 31 #define AUX_MU_IIR_REG 0x48 32 #define AUX_MU_LCR_REG 0x4c 33 #define AUX_MU_MCR_REG 0x50 34 #define AUX_MU_LSR_REG 0x54 35 #define AUX_MU_MSR_REG 0x58 36 #define AUX_MU_SCRATCH 0x5c 37 #define AUX_MU_CNTL_REG 0x60 38 #define AUX_MU_STAT_REG 0x64 39 #define AUX_MU_BAUD_REG 0x68 40 41 /* bits in IER/IIR registers */ 42 #define TX_INT 0x1 43 #define RX_INT 0x2 44 45 static void bcm2835_aux_update(BCM2835AuxState *s) 46 { 47 /* signal an interrupt if either: 48 * 1. rx interrupt is enabled and we have a non-empty rx fifo, or 49 * 2. the tx interrupt is enabled (since we instantly drain the tx fifo) 50 */ 51 s->iir = 0; 52 if ((s->ier & RX_INT) && s->read_count != 0) { 53 s->iir |= RX_INT; 54 } 55 if (s->ier & TX_INT) { 56 s->iir |= TX_INT; 57 } 58 qemu_set_irq(s->irq, s->iir != 0); 59 } 60 61 static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size) 62 { 63 BCM2835AuxState *s = opaque; 64 uint32_t c, res; 65 66 switch (offset) { 67 case AUX_IRQ: 68 return s->iir != 0; 69 70 case AUX_ENABLES: 71 return 1; /* mini UART permanently enabled */ 72 73 case AUX_MU_IO_REG: 74 /* "DLAB bit set means access baudrate register" is NYI */ 75 c = s->read_fifo[s->read_pos]; 76 if (s->read_count > 0) { 77 s->read_count--; 78 if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) { 79 s->read_pos = 0; 80 } 81 } 82 if (s->chr) { 83 qemu_chr_accept_input(s->chr); 84 } 85 bcm2835_aux_update(s); 86 return c; 87 88 case AUX_MU_IER_REG: 89 /* "DLAB bit set means access baudrate register" is NYI */ 90 return 0xc0 | s->ier; /* FIFO enables always read 1 */ 91 92 case AUX_MU_IIR_REG: 93 res = 0xc0; /* FIFO enables */ 94 /* The spec is unclear on what happens when both tx and rx 95 * interrupts are active, besides that this cannot occur. At 96 * present, we choose to prioritise the rx interrupt, since 97 * the tx fifo is always empty. */ 98 if (s->read_count != 0) { 99 res |= 0x4; 100 } else { 101 res |= 0x2; 102 } 103 if (s->iir == 0) { 104 res |= 0x1; 105 } 106 return res; 107 108 case AUX_MU_LCR_REG: 109 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__); 110 return 0; 111 112 case AUX_MU_MCR_REG: 113 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__); 114 return 0; 115 116 case AUX_MU_LSR_REG: 117 res = 0x60; /* tx idle, empty */ 118 if (s->read_count != 0) { 119 res |= 0x1; 120 } 121 return res; 122 123 case AUX_MU_MSR_REG: 124 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__); 125 return 0; 126 127 case AUX_MU_SCRATCH: 128 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__); 129 return 0; 130 131 case AUX_MU_CNTL_REG: 132 return 0x3; /* tx, rx enabled */ 133 134 case AUX_MU_STAT_REG: 135 res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */ 136 if (s->read_count > 0) { 137 res |= 0x1; /* data in input buffer */ 138 assert(s->read_count < BCM2835_AUX_RX_FIFO_LEN); 139 res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */ 140 } 141 return res; 142 143 case AUX_MU_BAUD_REG: 144 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__); 145 return 0; 146 147 default: 148 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 149 __func__, offset); 150 return 0; 151 } 152 } 153 154 static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value, 155 unsigned size) 156 { 157 BCM2835AuxState *s = opaque; 158 unsigned char ch; 159 160 switch (offset) { 161 case AUX_ENABLES: 162 if (value != 1) { 163 qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI " 164 "or disable UART\n", __func__); 165 } 166 break; 167 168 case AUX_MU_IO_REG: 169 /* "DLAB bit set means access baudrate register" is NYI */ 170 ch = value; 171 if (s->chr) { 172 qemu_chr_fe_write(s->chr, &ch, 1); 173 } 174 break; 175 176 case AUX_MU_IER_REG: 177 /* "DLAB bit set means access baudrate register" is NYI */ 178 s->ier = value & (TX_INT | RX_INT); 179 bcm2835_aux_update(s); 180 break; 181 182 case AUX_MU_IIR_REG: 183 if (value & 0x2) { 184 s->read_count = 0; 185 } 186 break; 187 188 case AUX_MU_LCR_REG: 189 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__); 190 break; 191 192 case AUX_MU_MCR_REG: 193 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__); 194 break; 195 196 case AUX_MU_SCRATCH: 197 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__); 198 break; 199 200 case AUX_MU_CNTL_REG: 201 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__); 202 break; 203 204 case AUX_MU_BAUD_REG: 205 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__); 206 break; 207 208 default: 209 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 210 __func__, offset); 211 } 212 213 bcm2835_aux_update(s); 214 } 215 216 static int bcm2835_aux_can_receive(void *opaque) 217 { 218 BCM2835AuxState *s = opaque; 219 220 return s->read_count < BCM2835_AUX_RX_FIFO_LEN; 221 } 222 223 static void bcm2835_aux_put_fifo(void *opaque, uint8_t value) 224 { 225 BCM2835AuxState *s = opaque; 226 int slot; 227 228 slot = s->read_pos + s->read_count; 229 if (slot >= BCM2835_AUX_RX_FIFO_LEN) { 230 slot -= BCM2835_AUX_RX_FIFO_LEN; 231 } 232 s->read_fifo[slot] = value; 233 s->read_count++; 234 if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) { 235 /* buffer full */ 236 } 237 bcm2835_aux_update(s); 238 } 239 240 static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size) 241 { 242 bcm2835_aux_put_fifo(opaque, *buf); 243 } 244 245 static const MemoryRegionOps bcm2835_aux_ops = { 246 .read = bcm2835_aux_read, 247 .write = bcm2835_aux_write, 248 .endianness = DEVICE_NATIVE_ENDIAN, 249 .valid.min_access_size = 4, 250 .valid.max_access_size = 4, 251 }; 252 253 static const VMStateDescription vmstate_bcm2835_aux = { 254 .name = TYPE_BCM2835_AUX, 255 .version_id = 1, 256 .minimum_version_id = 1, 257 .fields = (VMStateField[]) { 258 VMSTATE_UINT8_ARRAY(read_fifo, BCM2835AuxState, 259 BCM2835_AUX_RX_FIFO_LEN), 260 VMSTATE_UINT8(read_pos, BCM2835AuxState), 261 VMSTATE_UINT8(read_count, BCM2835AuxState), 262 VMSTATE_UINT8(ier, BCM2835AuxState), 263 VMSTATE_UINT8(iir, BCM2835AuxState), 264 VMSTATE_END_OF_LIST() 265 } 266 }; 267 268 static void bcm2835_aux_init(Object *obj) 269 { 270 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 271 BCM2835AuxState *s = BCM2835_AUX(obj); 272 273 memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s, 274 TYPE_BCM2835_AUX, 0x100); 275 sysbus_init_mmio(sbd, &s->iomem); 276 sysbus_init_irq(sbd, &s->irq); 277 } 278 279 static void bcm2835_aux_realize(DeviceState *dev, Error **errp) 280 { 281 BCM2835AuxState *s = BCM2835_AUX(dev); 282 283 if (s->chr) { 284 qemu_chr_add_handlers(s->chr, bcm2835_aux_can_receive, 285 bcm2835_aux_receive, NULL, s); 286 } 287 } 288 289 static Property bcm2835_aux_props[] = { 290 DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr), 291 DEFINE_PROP_END_OF_LIST(), 292 }; 293 294 static void bcm2835_aux_class_init(ObjectClass *oc, void *data) 295 { 296 DeviceClass *dc = DEVICE_CLASS(oc); 297 298 dc->realize = bcm2835_aux_realize; 299 dc->vmsd = &vmstate_bcm2835_aux; 300 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 301 dc->props = bcm2835_aux_props; 302 } 303 304 static const TypeInfo bcm2835_aux_info = { 305 .name = TYPE_BCM2835_AUX, 306 .parent = TYPE_SYS_BUS_DEVICE, 307 .instance_size = sizeof(BCM2835AuxState), 308 .instance_init = bcm2835_aux_init, 309 .class_init = bcm2835_aux_class_init, 310 }; 311 312 static void bcm2835_aux_register_types(void) 313 { 314 type_register_static(&bcm2835_aux_info); 315 } 316 317 type_init(bcm2835_aux_register_types) 318