1 /* 2 * BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI). 3 * Copyright (c) 2015, Microsoft 4 * Written by Andrew Baumann 5 * Based on pl011.c, copyright terms below: 6 * 7 * Arm PrimeCell PL011 UART 8 * 9 * Copyright (c) 2006 CodeSourcery. 10 * Written by Paul Brook 11 * 12 * This code is licensed under the GPL. 13 * 14 * At present only the core UART functions (data path for tx/rx) are 15 * implemented. The following features/registers are unimplemented: 16 * - Line/modem control 17 * - Scratch register 18 * - Extra control 19 * - Baudrate 20 * - SPI interfaces 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/char/bcm2835_aux.h" 25 #include "hw/irq.h" 26 #include "hw/qdev-properties.h" 27 #include "migration/vmstate.h" 28 #include "qemu/log.h" 29 #include "qemu/module.h" 30 31 #define AUX_IRQ 0x0 32 #define AUX_ENABLES 0x4 33 #define AUX_MU_IO_REG 0x40 34 #define AUX_MU_IER_REG 0x44 35 #define AUX_MU_IIR_REG 0x48 36 #define AUX_MU_LCR_REG 0x4c 37 #define AUX_MU_MCR_REG 0x50 38 #define AUX_MU_LSR_REG 0x54 39 #define AUX_MU_MSR_REG 0x58 40 #define AUX_MU_SCRATCH 0x5c 41 #define AUX_MU_CNTL_REG 0x60 42 #define AUX_MU_STAT_REG 0x64 43 #define AUX_MU_BAUD_REG 0x68 44 45 /* bits in IER/IIR registers */ 46 #define RX_INT 0x1 47 #define TX_INT 0x2 48 49 static void bcm2835_aux_update(BCM2835AuxState *s) 50 { 51 /* signal an interrupt if either: 52 * 1. rx interrupt is enabled and we have a non-empty rx fifo, or 53 * 2. the tx interrupt is enabled (since we instantly drain the tx fifo) 54 */ 55 s->iir = 0; 56 if ((s->ier & RX_INT) && s->read_count != 0) { 57 s->iir |= RX_INT; 58 } 59 if (s->ier & TX_INT) { 60 s->iir |= TX_INT; 61 } 62 qemu_set_irq(s->irq, s->iir != 0); 63 } 64 65 static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size) 66 { 67 BCM2835AuxState *s = opaque; 68 uint32_t c, res; 69 70 switch (offset) { 71 case AUX_IRQ: 72 return s->iir != 0; 73 74 case AUX_ENABLES: 75 return 1; /* mini UART permanently enabled */ 76 77 case AUX_MU_IO_REG: 78 /* "DLAB bit set means access baudrate register" is NYI */ 79 c = s->read_fifo[s->read_pos]; 80 if (s->read_count > 0) { 81 s->read_count--; 82 if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) { 83 s->read_pos = 0; 84 } 85 } 86 qemu_chr_fe_accept_input(&s->chr); 87 bcm2835_aux_update(s); 88 return c; 89 90 case AUX_MU_IER_REG: 91 /* "DLAB bit set means access baudrate register" is NYI */ 92 return 0xc0 | s->ier; /* FIFO enables always read 1 */ 93 94 case AUX_MU_IIR_REG: 95 res = 0xc0; /* FIFO enables */ 96 /* The spec is unclear on what happens when both tx and rx 97 * interrupts are active, besides that this cannot occur. At 98 * present, we choose to prioritise the rx interrupt, since 99 * the tx fifo is always empty. */ 100 if (s->read_count != 0) { 101 res |= 0x4; 102 } else { 103 res |= 0x2; 104 } 105 if (s->iir == 0) { 106 res |= 0x1; 107 } 108 return res; 109 110 case AUX_MU_LCR_REG: 111 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__); 112 return 0; 113 114 case AUX_MU_MCR_REG: 115 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__); 116 return 0; 117 118 case AUX_MU_LSR_REG: 119 res = 0x60; /* tx idle, empty */ 120 if (s->read_count != 0) { 121 res |= 0x1; 122 } 123 return res; 124 125 case AUX_MU_MSR_REG: 126 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__); 127 return 0; 128 129 case AUX_MU_SCRATCH: 130 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__); 131 return 0; 132 133 case AUX_MU_CNTL_REG: 134 return 0x3; /* tx, rx enabled */ 135 136 case AUX_MU_STAT_REG: 137 res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */ 138 if (s->read_count > 0) { 139 res |= 0x1; /* data in input buffer */ 140 assert(s->read_count < BCM2835_AUX_RX_FIFO_LEN); 141 res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */ 142 } 143 return res; 144 145 case AUX_MU_BAUD_REG: 146 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__); 147 return 0; 148 149 default: 150 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 151 __func__, offset); 152 return 0; 153 } 154 } 155 156 static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value, 157 unsigned size) 158 { 159 BCM2835AuxState *s = opaque; 160 unsigned char ch; 161 162 switch (offset) { 163 case AUX_ENABLES: 164 if (value != 1) { 165 qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI" 166 " or disable UART: 0x%"PRIx64"\n", 167 __func__, value); 168 } 169 break; 170 171 case AUX_MU_IO_REG: 172 /* "DLAB bit set means access baudrate register" is NYI */ 173 ch = value; 174 /* XXX this blocks entire thread. Rewrite to use 175 * qemu_chr_fe_write and background I/O callbacks */ 176 qemu_chr_fe_write_all(&s->chr, &ch, 1); 177 break; 178 179 case AUX_MU_IER_REG: 180 /* "DLAB bit set means access baudrate register" is NYI */ 181 s->ier = value & (TX_INT | RX_INT); 182 bcm2835_aux_update(s); 183 break; 184 185 case AUX_MU_IIR_REG: 186 if (value & 0x2) { 187 s->read_count = 0; 188 } 189 break; 190 191 case AUX_MU_LCR_REG: 192 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__); 193 break; 194 195 case AUX_MU_MCR_REG: 196 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__); 197 break; 198 199 case AUX_MU_SCRATCH: 200 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__); 201 break; 202 203 case AUX_MU_CNTL_REG: 204 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__); 205 break; 206 207 case AUX_MU_BAUD_REG: 208 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__); 209 break; 210 211 default: 212 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 213 __func__, offset); 214 } 215 216 bcm2835_aux_update(s); 217 } 218 219 static int bcm2835_aux_can_receive(void *opaque) 220 { 221 BCM2835AuxState *s = opaque; 222 223 return s->read_count < BCM2835_AUX_RX_FIFO_LEN; 224 } 225 226 static void bcm2835_aux_put_fifo(void *opaque, uint8_t value) 227 { 228 BCM2835AuxState *s = opaque; 229 int slot; 230 231 slot = s->read_pos + s->read_count; 232 if (slot >= BCM2835_AUX_RX_FIFO_LEN) { 233 slot -= BCM2835_AUX_RX_FIFO_LEN; 234 } 235 s->read_fifo[slot] = value; 236 s->read_count++; 237 if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) { 238 /* buffer full */ 239 } 240 bcm2835_aux_update(s); 241 } 242 243 static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size) 244 { 245 bcm2835_aux_put_fifo(opaque, *buf); 246 } 247 248 static const MemoryRegionOps bcm2835_aux_ops = { 249 .read = bcm2835_aux_read, 250 .write = bcm2835_aux_write, 251 .endianness = DEVICE_NATIVE_ENDIAN, 252 .impl.min_access_size = 4, 253 .impl.max_access_size = 4, 254 .valid.min_access_size = 1, 255 .valid.max_access_size = 4, 256 }; 257 258 static const VMStateDescription vmstate_bcm2835_aux = { 259 .name = TYPE_BCM2835_AUX, 260 .version_id = 1, 261 .minimum_version_id = 1, 262 .fields = (VMStateField[]) { 263 VMSTATE_UINT8_ARRAY(read_fifo, BCM2835AuxState, 264 BCM2835_AUX_RX_FIFO_LEN), 265 VMSTATE_UINT8(read_pos, BCM2835AuxState), 266 VMSTATE_UINT8(read_count, BCM2835AuxState), 267 VMSTATE_UINT8(ier, BCM2835AuxState), 268 VMSTATE_UINT8(iir, BCM2835AuxState), 269 VMSTATE_END_OF_LIST() 270 } 271 }; 272 273 static void bcm2835_aux_init(Object *obj) 274 { 275 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 276 BCM2835AuxState *s = BCM2835_AUX(obj); 277 278 memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s, 279 TYPE_BCM2835_AUX, 0x100); 280 sysbus_init_mmio(sbd, &s->iomem); 281 sysbus_init_irq(sbd, &s->irq); 282 } 283 284 static void bcm2835_aux_realize(DeviceState *dev, Error **errp) 285 { 286 BCM2835AuxState *s = BCM2835_AUX(dev); 287 288 qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive, 289 bcm2835_aux_receive, NULL, NULL, s, NULL, true); 290 } 291 292 static Property bcm2835_aux_props[] = { 293 DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr), 294 DEFINE_PROP_END_OF_LIST(), 295 }; 296 297 static void bcm2835_aux_class_init(ObjectClass *oc, void *data) 298 { 299 DeviceClass *dc = DEVICE_CLASS(oc); 300 301 dc->realize = bcm2835_aux_realize; 302 dc->vmsd = &vmstate_bcm2835_aux; 303 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 304 device_class_set_props(dc, bcm2835_aux_props); 305 } 306 307 static const TypeInfo bcm2835_aux_info = { 308 .name = TYPE_BCM2835_AUX, 309 .parent = TYPE_SYS_BUS_DEVICE, 310 .instance_size = sizeof(BCM2835AuxState), 311 .instance_init = bcm2835_aux_init, 312 .class_init = bcm2835_aux_class_init, 313 }; 314 315 static void bcm2835_aux_register_types(void) 316 { 317 type_register_static(&bcm2835_aux_info); 318 } 319 320 type_init(bcm2835_aux_register_types) 321