1 /* 2 * CFI parallel flash with AMD command set emulation 3 * 4 * Copyright (c) 2005 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /* 21 * For now, this code can emulate flashes of 1, 2 or 4 bytes width. 22 * Supported commands/modes are: 23 * - flash read 24 * - flash write 25 * - flash ID read 26 * - sector erase 27 * - chip erase 28 * - unlock bypass command 29 * - CFI queries 30 * 31 * It does not support flash interleaving. 32 * It does not implement boot blocs with reduced size 33 * It does not implement software data protection as found in many real chips 34 * It does not implement erase suspend/resume commands 35 * It does not implement multiple sectors erase 36 */ 37 38 #include "qemu/osdep.h" 39 #include "hw/hw.h" 40 #include "hw/block/flash.h" 41 #include "qapi/error.h" 42 #include "qemu/timer.h" 43 #include "sysemu/block-backend.h" 44 #include "qemu/host-utils.h" 45 #include "hw/sysbus.h" 46 #include "trace.h" 47 48 //#define PFLASH_DEBUG 49 #ifdef PFLASH_DEBUG 50 #define DPRINTF(fmt, ...) \ 51 do { \ 52 fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \ 53 } while (0) 54 #else 55 #define DPRINTF(fmt, ...) do { } while (0) 56 #endif 57 58 #define PFLASH_LAZY_ROMD_THRESHOLD 42 59 60 struct PFlashCFI02 { 61 /*< private >*/ 62 SysBusDevice parent_obj; 63 /*< public >*/ 64 65 BlockBackend *blk; 66 uint32_t sector_len; 67 uint32_t nb_blocs; 68 uint32_t chip_len; 69 uint8_t mappings; 70 uint8_t width; 71 uint8_t be; 72 int wcycle; /* if 0, the flash is read normally */ 73 int bypass; 74 int ro; 75 uint8_t cmd; 76 uint8_t status; 77 /* FIXME: implement array device properties */ 78 uint16_t ident0; 79 uint16_t ident1; 80 uint16_t ident2; 81 uint16_t ident3; 82 uint16_t unlock_addr0; 83 uint16_t unlock_addr1; 84 uint8_t cfi_table[0x52]; 85 QEMUTimer timer; 86 /* The device replicates the flash memory across its memory space. Emulate 87 * that by having a container (.mem) filled with an array of aliases 88 * (.mem_mappings) pointing to the flash memory (.orig_mem). 89 */ 90 MemoryRegion mem; 91 MemoryRegion *mem_mappings; /* array; one per mapping */ 92 MemoryRegion orig_mem; 93 int rom_mode; 94 int read_counter; /* used for lazy switch-back to rom mode */ 95 char *name; 96 void *storage; 97 }; 98 99 /* 100 * Set up replicated mappings of the same region. 101 */ 102 static void pflash_setup_mappings(PFlashCFI02 *pfl) 103 { 104 unsigned i; 105 hwaddr size = memory_region_size(&pfl->orig_mem); 106 107 memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size); 108 pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); 109 for (i = 0; i < pfl->mappings; ++i) { 110 memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl), 111 "pflash-alias", &pfl->orig_mem, 0, size); 112 memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); 113 } 114 } 115 116 static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode) 117 { 118 memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode); 119 pfl->rom_mode = rom_mode; 120 } 121 122 static void pflash_timer (void *opaque) 123 { 124 PFlashCFI02 *pfl = opaque; 125 126 trace_pflash_timer_expired(pfl->cmd); 127 /* Reset flash */ 128 pfl->status ^= 0x80; 129 if (pfl->bypass) { 130 pfl->wcycle = 2; 131 } else { 132 pflash_register_memory(pfl, 1); 133 pfl->wcycle = 0; 134 } 135 pfl->cmd = 0; 136 } 137 138 static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr offset, 139 int width, int be) 140 { 141 hwaddr boff; 142 uint32_t ret; 143 uint8_t *p; 144 145 ret = -1; 146 trace_pflash_read(offset, pfl->cmd, width, pfl->wcycle); 147 /* Lazy reset to ROMD mode after a certain amount of read accesses */ 148 if (!pfl->rom_mode && pfl->wcycle == 0 && 149 ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { 150 pflash_register_memory(pfl, 1); 151 } 152 offset &= pfl->chip_len - 1; 153 boff = offset & 0xFF; 154 if (pfl->width == 2) 155 boff = boff >> 1; 156 else if (pfl->width == 4) 157 boff = boff >> 2; 158 switch (pfl->cmd) { 159 default: 160 /* This should never happen : reset state & treat it as a read*/ 161 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); 162 pfl->wcycle = 0; 163 pfl->cmd = 0; 164 /* fall through to the read code */ 165 case 0x80: 166 /* We accept reads during second unlock sequence... */ 167 case 0x00: 168 flash_read: 169 /* Flash area read */ 170 p = pfl->storage; 171 switch (width) { 172 case 1: 173 ret = p[offset]; 174 trace_pflash_data_read8(offset, ret); 175 break; 176 case 2: 177 if (be) { 178 ret = p[offset] << 8; 179 ret |= p[offset + 1]; 180 } else { 181 ret = p[offset]; 182 ret |= p[offset + 1] << 8; 183 } 184 trace_pflash_data_read16(offset, ret); 185 break; 186 case 4: 187 if (be) { 188 ret = p[offset] << 24; 189 ret |= p[offset + 1] << 16; 190 ret |= p[offset + 2] << 8; 191 ret |= p[offset + 3]; 192 } else { 193 ret = p[offset]; 194 ret |= p[offset + 1] << 8; 195 ret |= p[offset + 2] << 16; 196 ret |= p[offset + 3] << 24; 197 } 198 trace_pflash_data_read32(offset, ret); 199 break; 200 } 201 break; 202 case 0x90: 203 /* flash ID read */ 204 switch (boff) { 205 case 0x00: 206 case 0x01: 207 ret = boff & 0x01 ? pfl->ident1 : pfl->ident0; 208 break; 209 case 0x02: 210 ret = 0x00; /* Pretend all sectors are unprotected */ 211 break; 212 case 0x0E: 213 case 0x0F: 214 ret = boff & 0x01 ? pfl->ident3 : pfl->ident2; 215 if (ret == (uint8_t)-1) { 216 goto flash_read; 217 } 218 break; 219 default: 220 goto flash_read; 221 } 222 DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret); 223 break; 224 case 0xA0: 225 case 0x10: 226 case 0x30: 227 /* Status register read */ 228 ret = pfl->status; 229 DPRINTF("%s: status %x\n", __func__, ret); 230 /* Toggle bit 6 */ 231 pfl->status ^= 0x40; 232 break; 233 case 0x98: 234 /* CFI query mode */ 235 if (boff < sizeof(pfl->cfi_table)) { 236 ret = pfl->cfi_table[boff]; 237 } else { 238 ret = 0; 239 } 240 break; 241 } 242 243 return ret; 244 } 245 246 /* update flash content on disk */ 247 static void pflash_update(PFlashCFI02 *pfl, int offset, 248 int size) 249 { 250 int offset_end; 251 if (pfl->blk) { 252 offset_end = offset + size; 253 /* widen to sector boundaries */ 254 offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); 255 offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); 256 blk_pwrite(pfl->blk, offset, pfl->storage + offset, 257 offset_end - offset, 0); 258 } 259 } 260 261 static void pflash_write(PFlashCFI02 *pfl, hwaddr offset, 262 uint32_t value, int width, int be) 263 { 264 hwaddr boff; 265 uint8_t *p; 266 uint8_t cmd; 267 268 cmd = value; 269 if (pfl->cmd != 0xA0 && cmd == 0xF0) { 270 #if 0 271 DPRINTF("%s: flash reset asked (%02x %02x)\n", 272 __func__, pfl->cmd, cmd); 273 #endif 274 goto reset_flash; 275 } 276 trace_pflash_write(offset, value, width, pfl->wcycle); 277 offset &= pfl->chip_len - 1; 278 279 DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__, 280 offset, value, width); 281 boff = offset & (pfl->sector_len - 1); 282 if (pfl->width == 2) 283 boff = boff >> 1; 284 else if (pfl->width == 4) 285 boff = boff >> 2; 286 switch (pfl->wcycle) { 287 case 0: 288 /* Set the device in I/O access mode if required */ 289 if (pfl->rom_mode) 290 pflash_register_memory(pfl, 0); 291 pfl->read_counter = 0; 292 /* We're in read mode */ 293 check_unlock0: 294 if (boff == 0x55 && cmd == 0x98) { 295 enter_CFI_mode: 296 /* Enter CFI query mode */ 297 pfl->wcycle = 7; 298 pfl->cmd = 0x98; 299 return; 300 } 301 if (boff != pfl->unlock_addr0 || cmd != 0xAA) { 302 DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", 303 __func__, boff, cmd, pfl->unlock_addr0); 304 goto reset_flash; 305 } 306 DPRINTF("%s: unlock sequence started\n", __func__); 307 break; 308 case 1: 309 /* We started an unlock sequence */ 310 check_unlock1: 311 if (boff != pfl->unlock_addr1 || cmd != 0x55) { 312 DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, 313 boff, cmd); 314 goto reset_flash; 315 } 316 DPRINTF("%s: unlock sequence done\n", __func__); 317 break; 318 case 2: 319 /* We finished an unlock sequence */ 320 if (!pfl->bypass && boff != pfl->unlock_addr0) { 321 DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, 322 boff, cmd); 323 goto reset_flash; 324 } 325 switch (cmd) { 326 case 0x20: 327 pfl->bypass = 1; 328 goto do_bypass; 329 case 0x80: 330 case 0x90: 331 case 0xA0: 332 pfl->cmd = cmd; 333 DPRINTF("%s: starting command %02x\n", __func__, cmd); 334 break; 335 default: 336 DPRINTF("%s: unknown command %02x\n", __func__, cmd); 337 goto reset_flash; 338 } 339 break; 340 case 3: 341 switch (pfl->cmd) { 342 case 0x80: 343 /* We need another unlock sequence */ 344 goto check_unlock0; 345 case 0xA0: 346 trace_pflash_data_write(offset, value, width, 0); 347 p = pfl->storage; 348 if (!pfl->ro) { 349 switch (width) { 350 case 1: 351 p[offset] &= value; 352 pflash_update(pfl, offset, 1); 353 break; 354 case 2: 355 if (be) { 356 p[offset] &= value >> 8; 357 p[offset + 1] &= value; 358 } else { 359 p[offset] &= value; 360 p[offset + 1] &= value >> 8; 361 } 362 pflash_update(pfl, offset, 2); 363 break; 364 case 4: 365 if (be) { 366 p[offset] &= value >> 24; 367 p[offset + 1] &= value >> 16; 368 p[offset + 2] &= value >> 8; 369 p[offset + 3] &= value; 370 } else { 371 p[offset] &= value; 372 p[offset + 1] &= value >> 8; 373 p[offset + 2] &= value >> 16; 374 p[offset + 3] &= value >> 24; 375 } 376 pflash_update(pfl, offset, 4); 377 break; 378 } 379 } 380 pfl->status = 0x00 | ~(value & 0x80); 381 /* Let's pretend write is immediate */ 382 if (pfl->bypass) 383 goto do_bypass; 384 goto reset_flash; 385 case 0x90: 386 if (pfl->bypass && cmd == 0x00) { 387 /* Unlock bypass reset */ 388 goto reset_flash; 389 } 390 /* We can enter CFI query mode from autoselect mode */ 391 if (boff == 0x55 && cmd == 0x98) 392 goto enter_CFI_mode; 393 /* No break here */ 394 default: 395 DPRINTF("%s: invalid write for command %02x\n", 396 __func__, pfl->cmd); 397 goto reset_flash; 398 } 399 case 4: 400 switch (pfl->cmd) { 401 case 0xA0: 402 /* Ignore writes while flash data write is occurring */ 403 /* As we suppose write is immediate, this should never happen */ 404 return; 405 case 0x80: 406 goto check_unlock1; 407 default: 408 /* Should never happen */ 409 DPRINTF("%s: invalid command state %02x (wc 4)\n", 410 __func__, pfl->cmd); 411 goto reset_flash; 412 } 413 break; 414 case 5: 415 switch (cmd) { 416 case 0x10: 417 if (boff != pfl->unlock_addr0) { 418 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", 419 __func__, offset); 420 goto reset_flash; 421 } 422 /* Chip erase */ 423 DPRINTF("%s: start chip erase\n", __func__); 424 if (!pfl->ro) { 425 memset(pfl->storage, 0xFF, pfl->chip_len); 426 pflash_update(pfl, 0, pfl->chip_len); 427 } 428 pfl->status = 0x00; 429 /* Let's wait 5 seconds before chip erase is done */ 430 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 431 (NANOSECONDS_PER_SECOND * 5)); 432 break; 433 case 0x30: 434 /* Sector erase */ 435 p = pfl->storage; 436 offset &= ~(pfl->sector_len - 1); 437 DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__, 438 offset); 439 if (!pfl->ro) { 440 memset(p + offset, 0xFF, pfl->sector_len); 441 pflash_update(pfl, offset, pfl->sector_len); 442 } 443 pfl->status = 0x00; 444 /* Let's wait 1/2 second before sector erase is done */ 445 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 446 (NANOSECONDS_PER_SECOND / 2)); 447 break; 448 default: 449 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); 450 goto reset_flash; 451 } 452 pfl->cmd = cmd; 453 break; 454 case 6: 455 switch (pfl->cmd) { 456 case 0x10: 457 /* Ignore writes during chip erase */ 458 return; 459 case 0x30: 460 /* Ignore writes during sector erase */ 461 return; 462 default: 463 /* Should never happen */ 464 DPRINTF("%s: invalid command state %02x (wc 6)\n", 465 __func__, pfl->cmd); 466 goto reset_flash; 467 } 468 break; 469 case 7: /* Special value for CFI queries */ 470 DPRINTF("%s: invalid write in CFI query mode\n", __func__); 471 goto reset_flash; 472 default: 473 /* Should never happen */ 474 DPRINTF("%s: invalid write state (wc 7)\n", __func__); 475 goto reset_flash; 476 } 477 pfl->wcycle++; 478 479 return; 480 481 /* Reset flash */ 482 reset_flash: 483 trace_pflash_reset(); 484 pfl->bypass = 0; 485 pfl->wcycle = 0; 486 pfl->cmd = 0; 487 return; 488 489 do_bypass: 490 pfl->wcycle = 2; 491 pfl->cmd = 0; 492 } 493 494 static uint64_t pflash_be_readfn(void *opaque, hwaddr addr, unsigned size) 495 { 496 return pflash_read(opaque, addr, size, 1); 497 } 498 499 static void pflash_be_writefn(void *opaque, hwaddr addr, 500 uint64_t value, unsigned size) 501 { 502 pflash_write(opaque, addr, value, size, 1); 503 } 504 505 static uint64_t pflash_le_readfn(void *opaque, hwaddr addr, unsigned size) 506 { 507 return pflash_read(opaque, addr, size, 0); 508 } 509 510 static void pflash_le_writefn(void *opaque, hwaddr addr, 511 uint64_t value, unsigned size) 512 { 513 pflash_write(opaque, addr, value, size, 0); 514 } 515 516 static const MemoryRegionOps pflash_cfi02_ops_be = { 517 .read = pflash_be_readfn, 518 .write = pflash_be_writefn, 519 .valid.min_access_size = 1, 520 .valid.max_access_size = 4, 521 .endianness = DEVICE_NATIVE_ENDIAN, 522 }; 523 524 static const MemoryRegionOps pflash_cfi02_ops_le = { 525 .read = pflash_le_readfn, 526 .write = pflash_le_writefn, 527 .valid.min_access_size = 1, 528 .valid.max_access_size = 4, 529 .endianness = DEVICE_NATIVE_ENDIAN, 530 }; 531 532 static void pflash_cfi02_realize(DeviceState *dev, Error **errp) 533 { 534 PFlashCFI02 *pfl = PFLASH_CFI02(dev); 535 uint32_t chip_len; 536 int ret; 537 Error *local_err = NULL; 538 539 if (pfl->sector_len == 0) { 540 error_setg(errp, "attribute \"sector-length\" not specified or zero."); 541 return; 542 } 543 if (pfl->nb_blocs == 0) { 544 error_setg(errp, "attribute \"num-blocks\" not specified or zero."); 545 return; 546 } 547 if (pfl->name == NULL) { 548 error_setg(errp, "attribute \"name\" not specified."); 549 return; 550 } 551 552 chip_len = pfl->sector_len * pfl->nb_blocs; 553 /* XXX: to be fixed */ 554 #if 0 555 if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && 556 total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) 557 return NULL; 558 #endif 559 560 memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ? 561 &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, 562 pfl, pfl->name, chip_len, &local_err); 563 if (local_err) { 564 error_propagate(errp, local_err); 565 return; 566 } 567 568 pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); 569 pfl->chip_len = chip_len; 570 571 if (pfl->blk) { 572 uint64_t perm; 573 pfl->ro = blk_is_read_only(pfl->blk); 574 perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE); 575 ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp); 576 if (ret < 0) { 577 return; 578 } 579 } else { 580 pfl->ro = 0; 581 } 582 583 if (pfl->blk) { 584 /* read the initial flash content */ 585 ret = blk_pread(pfl->blk, 0, pfl->storage, chip_len); 586 if (ret < 0) { 587 vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl)); 588 error_setg(errp, "failed to read the initial flash content"); 589 return; 590 } 591 } 592 593 pflash_setup_mappings(pfl); 594 pfl->rom_mode = 1; 595 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); 596 597 timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); 598 pfl->wcycle = 0; 599 pfl->cmd = 0; 600 pfl->status = 0; 601 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ 602 /* Standard "QRY" string */ 603 pfl->cfi_table[0x10] = 'Q'; 604 pfl->cfi_table[0x11] = 'R'; 605 pfl->cfi_table[0x12] = 'Y'; 606 /* Command set (AMD/Fujitsu) */ 607 pfl->cfi_table[0x13] = 0x02; 608 pfl->cfi_table[0x14] = 0x00; 609 /* Primary extended table address */ 610 pfl->cfi_table[0x15] = 0x31; 611 pfl->cfi_table[0x16] = 0x00; 612 /* Alternate command set (none) */ 613 pfl->cfi_table[0x17] = 0x00; 614 pfl->cfi_table[0x18] = 0x00; 615 /* Alternate extended table (none) */ 616 pfl->cfi_table[0x19] = 0x00; 617 pfl->cfi_table[0x1A] = 0x00; 618 /* Vcc min */ 619 pfl->cfi_table[0x1B] = 0x27; 620 /* Vcc max */ 621 pfl->cfi_table[0x1C] = 0x36; 622 /* Vpp min (no Vpp pin) */ 623 pfl->cfi_table[0x1D] = 0x00; 624 /* Vpp max (no Vpp pin) */ 625 pfl->cfi_table[0x1E] = 0x00; 626 /* Reserved */ 627 pfl->cfi_table[0x1F] = 0x07; 628 /* Timeout for min size buffer write (NA) */ 629 pfl->cfi_table[0x20] = 0x00; 630 /* Typical timeout for block erase (512 ms) */ 631 pfl->cfi_table[0x21] = 0x09; 632 /* Typical timeout for full chip erase (4096 ms) */ 633 pfl->cfi_table[0x22] = 0x0C; 634 /* Reserved */ 635 pfl->cfi_table[0x23] = 0x01; 636 /* Max timeout for buffer write (NA) */ 637 pfl->cfi_table[0x24] = 0x00; 638 /* Max timeout for block erase */ 639 pfl->cfi_table[0x25] = 0x0A; 640 /* Max timeout for chip erase */ 641 pfl->cfi_table[0x26] = 0x0D; 642 /* Device size */ 643 pfl->cfi_table[0x27] = ctz32(chip_len); 644 /* Flash device interface (8 & 16 bits) */ 645 pfl->cfi_table[0x28] = 0x02; 646 pfl->cfi_table[0x29] = 0x00; 647 /* Max number of bytes in multi-bytes write */ 648 /* XXX: disable buffered write as it's not supported */ 649 // pfl->cfi_table[0x2A] = 0x05; 650 pfl->cfi_table[0x2A] = 0x00; 651 pfl->cfi_table[0x2B] = 0x00; 652 /* Number of erase block regions (uniform) */ 653 pfl->cfi_table[0x2C] = 0x01; 654 /* Erase block region 1 */ 655 pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; 656 pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; 657 pfl->cfi_table[0x2F] = pfl->sector_len >> 8; 658 pfl->cfi_table[0x30] = pfl->sector_len >> 16; 659 660 /* Extended */ 661 pfl->cfi_table[0x31] = 'P'; 662 pfl->cfi_table[0x32] = 'R'; 663 pfl->cfi_table[0x33] = 'I'; 664 665 pfl->cfi_table[0x34] = '1'; 666 pfl->cfi_table[0x35] = '0'; 667 668 pfl->cfi_table[0x36] = 0x00; 669 pfl->cfi_table[0x37] = 0x00; 670 pfl->cfi_table[0x38] = 0x00; 671 pfl->cfi_table[0x39] = 0x00; 672 673 pfl->cfi_table[0x3a] = 0x00; 674 675 pfl->cfi_table[0x3b] = 0x00; 676 pfl->cfi_table[0x3c] = 0x00; 677 } 678 679 static Property pflash_cfi02_properties[] = { 680 DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk), 681 DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, nb_blocs, 0), 682 DEFINE_PROP_UINT32("sector-length", PFlashCFI02, sector_len, 0), 683 DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0), 684 DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0), 685 DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0), 686 DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0), 687 DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0), 688 DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0), 689 DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0), 690 DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0), 691 DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0), 692 DEFINE_PROP_STRING("name", PFlashCFI02, name), 693 DEFINE_PROP_END_OF_LIST(), 694 }; 695 696 static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp) 697 { 698 PFlashCFI02 *pfl = PFLASH_CFI02(dev); 699 timer_del(&pfl->timer); 700 } 701 702 static void pflash_cfi02_class_init(ObjectClass *klass, void *data) 703 { 704 DeviceClass *dc = DEVICE_CLASS(klass); 705 706 dc->realize = pflash_cfi02_realize; 707 dc->unrealize = pflash_cfi02_unrealize; 708 dc->props = pflash_cfi02_properties; 709 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 710 } 711 712 static const TypeInfo pflash_cfi02_info = { 713 .name = TYPE_PFLASH_CFI02, 714 .parent = TYPE_SYS_BUS_DEVICE, 715 .instance_size = sizeof(PFlashCFI02), 716 .class_init = pflash_cfi02_class_init, 717 }; 718 719 static void pflash_cfi02_register_types(void) 720 { 721 type_register_static(&pflash_cfi02_info); 722 } 723 724 type_init(pflash_cfi02_register_types) 725 726 PFlashCFI02 *pflash_cfi02_register(hwaddr base, 727 const char *name, 728 hwaddr size, 729 BlockBackend *blk, 730 uint32_t sector_len, 731 int nb_mappings, int width, 732 uint16_t id0, uint16_t id1, 733 uint16_t id2, uint16_t id3, 734 uint16_t unlock_addr0, 735 uint16_t unlock_addr1, 736 int be) 737 { 738 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02); 739 740 if (blk) { 741 qdev_prop_set_drive(dev, "drive", blk, &error_abort); 742 } 743 assert(size % sector_len == 0); 744 qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); 745 qdev_prop_set_uint32(dev, "sector-length", sector_len); 746 qdev_prop_set_uint8(dev, "width", width); 747 qdev_prop_set_uint8(dev, "mappings", nb_mappings); 748 qdev_prop_set_uint8(dev, "big-endian", !!be); 749 qdev_prop_set_uint16(dev, "id0", id0); 750 qdev_prop_set_uint16(dev, "id1", id1); 751 qdev_prop_set_uint16(dev, "id2", id2); 752 qdev_prop_set_uint16(dev, "id3", id3); 753 qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); 754 qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); 755 qdev_prop_set_string(dev, "name", name); 756 qdev_init_nofail(dev); 757 758 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 759 return PFLASH_CFI02(dev); 760 } 761