1 /* 2 * CFI parallel flash with AMD command set emulation 3 * 4 * Copyright (c) 2005 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /* 21 * For now, this code can emulate flashes of 1, 2 or 4 bytes width. 22 * Supported commands/modes are: 23 * - flash read 24 * - flash write 25 * - flash ID read 26 * - sector erase 27 * - chip erase 28 * - unlock bypass command 29 * - CFI queries 30 * 31 * It does not support flash interleaving. 32 * It does not implement software data protection as found in many real chips 33 */ 34 35 #include "qemu/osdep.h" 36 #include "hw/hw.h" 37 #include "hw/block/block.h" 38 #include "hw/block/flash.h" 39 #include "qapi/error.h" 40 #include "qemu/bitmap.h" 41 #include "qemu/timer.h" 42 #include "sysemu/block-backend.h" 43 #include "qemu/host-utils.h" 44 #include "qemu/module.h" 45 #include "hw/sysbus.h" 46 #include "trace.h" 47 48 #define PFLASH_DEBUG false 49 #define DPRINTF(fmt, ...) \ 50 do { \ 51 if (PFLASH_DEBUG) { \ 52 fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__); \ 53 } \ 54 } while (0) 55 56 #define PFLASH_LAZY_ROMD_THRESHOLD 42 57 58 /* 59 * The size of the cfi_table indirectly depends on this and the start of the 60 * PRI table directly depends on it. 4 is the maximum size (and also what 61 * seems common) without changing the PRT table address. 62 */ 63 #define PFLASH_MAX_ERASE_REGIONS 4 64 65 /* Special write cycles for CFI queries. */ 66 enum { 67 WCYCLE_CFI = 7, 68 WCYCLE_AUTOSELECT_CFI = 8, 69 }; 70 71 struct PFlashCFI02 { 72 /*< private >*/ 73 SysBusDevice parent_obj; 74 /*< public >*/ 75 76 BlockBackend *blk; 77 uint32_t uniform_nb_blocs; 78 uint32_t uniform_sector_len; 79 uint32_t total_sectors; 80 uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS]; 81 uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS]; 82 uint32_t chip_len; 83 uint8_t mappings; 84 uint8_t width; 85 uint8_t be; 86 int wcycle; /* if 0, the flash is read normally */ 87 int bypass; 88 int ro; 89 uint8_t cmd; 90 uint8_t status; 91 /* FIXME: implement array device properties */ 92 uint16_t ident0; 93 uint16_t ident1; 94 uint16_t ident2; 95 uint16_t ident3; 96 uint16_t unlock_addr0; 97 uint16_t unlock_addr1; 98 uint8_t cfi_table[0x4d]; 99 QEMUTimer timer; 100 /* The device replicates the flash memory across its memory space. Emulate 101 * that by having a container (.mem) filled with an array of aliases 102 * (.mem_mappings) pointing to the flash memory (.orig_mem). 103 */ 104 MemoryRegion mem; 105 MemoryRegion *mem_mappings; /* array; one per mapping */ 106 MemoryRegion orig_mem; 107 int rom_mode; 108 int read_counter; /* used for lazy switch-back to rom mode */ 109 int sectors_to_erase; 110 uint64_t erase_time_remaining; 111 unsigned long *sector_erase_map; 112 char *name; 113 void *storage; 114 }; 115 116 /* 117 * Toggle status bit DQ7. 118 */ 119 static inline void toggle_dq7(PFlashCFI02 *pfl) 120 { 121 pfl->status ^= 0x80; 122 } 123 124 /* 125 * Set status bit DQ7 to bit 7 of value. 126 */ 127 static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value) 128 { 129 pfl->status &= 0x7F; 130 pfl->status |= value & 0x80; 131 } 132 133 /* 134 * Toggle status bit DQ6. 135 */ 136 static inline void toggle_dq6(PFlashCFI02 *pfl) 137 { 138 pfl->status ^= 0x40; 139 } 140 141 /* 142 * Turn on DQ3. 143 */ 144 static inline void assert_dq3(PFlashCFI02 *pfl) 145 { 146 pfl->status |= 0x08; 147 } 148 149 /* 150 * Turn off DQ3. 151 */ 152 static inline void reset_dq3(PFlashCFI02 *pfl) 153 { 154 pfl->status &= ~0x08; 155 } 156 157 /* 158 * Toggle status bit DQ2. 159 */ 160 static inline void toggle_dq2(PFlashCFI02 *pfl) 161 { 162 pfl->status ^= 0x04; 163 } 164 165 /* 166 * Set up replicated mappings of the same region. 167 */ 168 static void pflash_setup_mappings(PFlashCFI02 *pfl) 169 { 170 unsigned i; 171 hwaddr size = memory_region_size(&pfl->orig_mem); 172 173 memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size); 174 pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); 175 for (i = 0; i < pfl->mappings; ++i) { 176 memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl), 177 "pflash-alias", &pfl->orig_mem, 0, size); 178 memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); 179 } 180 } 181 182 static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode) 183 { 184 memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode); 185 pfl->rom_mode = rom_mode; 186 } 187 188 static size_t pflash_regions_count(PFlashCFI02 *pfl) 189 { 190 return pfl->cfi_table[0x2c]; 191 } 192 193 /* 194 * Returns the time it takes to erase the number of sectors scheduled for 195 * erasure based on CFI address 0x21 which is "Typical timeout per individual 196 * block erase 2^N ms." 197 */ 198 static uint64_t pflash_erase_time(PFlashCFI02 *pfl) 199 { 200 /* 201 * If there are no sectors to erase (which can happen if all of the sectors 202 * to be erased are protected), then erase takes 100 us. Protected sectors 203 * aren't supported so this should never happen. 204 */ 205 return ((1ULL << pfl->cfi_table[0x21]) * pfl->sectors_to_erase) * SCALE_US; 206 } 207 208 /* 209 * Returns true if the device is currently in erase suspend mode. 210 */ 211 static inline bool pflash_erase_suspend_mode(PFlashCFI02 *pfl) 212 { 213 return pfl->erase_time_remaining > 0; 214 } 215 216 static void pflash_timer(void *opaque) 217 { 218 PFlashCFI02 *pfl = opaque; 219 220 trace_pflash_timer_expired(pfl->cmd); 221 if (pfl->cmd == 0x30) { 222 /* 223 * Sector erase. If DQ3 is 0 when the timer expires, then the 50 224 * us erase timeout has expired so we need to start the timer for the 225 * sector erase algorithm. Otherwise, the erase completed and we should 226 * go back to read array mode. 227 */ 228 if ((pfl->status & 0x08) == 0) { 229 assert_dq3(pfl); 230 uint64_t timeout = pflash_erase_time(pfl); 231 timer_mod(&pfl->timer, 232 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); 233 DPRINTF("%s: erase timeout fired; erasing %d sectors\n", 234 __func__, pfl->sectors_to_erase); 235 return; 236 } 237 DPRINTF("%s: sector erase complete\n", __func__); 238 bitmap_zero(pfl->sector_erase_map, pfl->total_sectors); 239 pfl->sectors_to_erase = 0; 240 reset_dq3(pfl); 241 } 242 243 /* Reset flash */ 244 toggle_dq7(pfl); 245 if (pfl->bypass) { 246 pfl->wcycle = 2; 247 } else { 248 pflash_register_memory(pfl, 1); 249 pfl->wcycle = 0; 250 } 251 pfl->cmd = 0; 252 } 253 254 /* 255 * Read data from flash. 256 */ 257 static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset, 258 unsigned int width) 259 { 260 uint8_t *p = (uint8_t *)pfl->storage + offset; 261 uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width); 262 trace_pflash_data_read(offset, width << 1, ret); 263 return ret; 264 } 265 266 typedef struct { 267 uint32_t len; 268 uint32_t num; 269 } SectorInfo; 270 271 /* 272 * offset should be a byte offset of the QEMU device and _not_ a device 273 * offset. 274 */ 275 static SectorInfo pflash_sector_info(PFlashCFI02 *pfl, hwaddr offset) 276 { 277 assert(offset < pfl->chip_len); 278 hwaddr addr = 0; 279 uint32_t sector_num = 0; 280 for (int i = 0; i < pflash_regions_count(pfl); ++i) { 281 uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i]; 282 if (addr <= offset && offset < addr + region_size) { 283 return (SectorInfo) { 284 .len = pfl->sector_len[i], 285 .num = sector_num + (offset - addr) / pfl->sector_len[i], 286 }; 287 } 288 sector_num += pfl->nb_blocs[i]; 289 addr += region_size; 290 } 291 abort(); 292 } 293 294 /* 295 * Returns true if the offset refers to a flash sector that is currently being 296 * erased. 297 */ 298 static bool pflash_sector_is_erasing(PFlashCFI02 *pfl, hwaddr offset) 299 { 300 long sector_num = pflash_sector_info(pfl, offset).num; 301 return test_bit(sector_num, pfl->sector_erase_map); 302 } 303 304 static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width) 305 { 306 PFlashCFI02 *pfl = opaque; 307 hwaddr boff; 308 uint64_t ret; 309 310 ret = -1; 311 /* Lazy reset to ROMD mode after a certain amount of read accesses */ 312 if (!pfl->rom_mode && pfl->wcycle == 0 && 313 ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { 314 pflash_register_memory(pfl, 1); 315 } 316 offset &= pfl->chip_len - 1; 317 boff = offset & 0xFF; 318 if (pfl->width == 2) { 319 boff = boff >> 1; 320 } else if (pfl->width == 4) { 321 boff = boff >> 2; 322 } 323 switch (pfl->cmd) { 324 default: 325 /* This should never happen : reset state & treat it as a read*/ 326 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); 327 pfl->wcycle = 0; 328 pfl->cmd = 0; 329 /* fall through to the read code */ 330 case 0x80: /* Erase (unlock) */ 331 /* We accept reads during second unlock sequence... */ 332 case 0x00: 333 if (pflash_erase_suspend_mode(pfl) && 334 pflash_sector_is_erasing(pfl, offset)) { 335 /* Toggle bit 2, but not 6. */ 336 toggle_dq2(pfl); 337 /* Status register read */ 338 ret = pfl->status; 339 DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); 340 break; 341 } 342 /* Flash area read */ 343 ret = pflash_data_read(pfl, offset, width); 344 break; 345 case 0x90: /* flash ID read */ 346 switch (boff) { 347 case 0x00: 348 case 0x01: 349 ret = boff & 0x01 ? pfl->ident1 : pfl->ident0; 350 break; 351 case 0x02: 352 ret = 0x00; /* Pretend all sectors are unprotected */ 353 break; 354 case 0x0E: 355 case 0x0F: 356 ret = boff & 0x01 ? pfl->ident3 : pfl->ident2; 357 if (ret != (uint8_t)-1) { 358 break; 359 } 360 /* Fall through to data read. */ 361 default: 362 ret = pflash_data_read(pfl, offset, width); 363 } 364 DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret); 365 break; 366 case 0x10: /* Chip Erase */ 367 case 0x30: /* Sector Erase */ 368 /* Toggle bit 2 during erase, but not program. */ 369 toggle_dq2(pfl); 370 case 0xA0: /* Program */ 371 /* Toggle bit 6 */ 372 toggle_dq6(pfl); 373 /* Status register read */ 374 ret = pfl->status; 375 DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); 376 break; 377 case 0x98: 378 /* CFI query mode */ 379 if (boff < sizeof(pfl->cfi_table)) { 380 ret = pfl->cfi_table[boff]; 381 } else { 382 ret = 0; 383 } 384 break; 385 } 386 trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle); 387 388 return ret; 389 } 390 391 /* update flash content on disk */ 392 static void pflash_update(PFlashCFI02 *pfl, int offset, int size) 393 { 394 int offset_end; 395 if (pfl->blk) { 396 offset_end = offset + size; 397 /* widen to sector boundaries */ 398 offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); 399 offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); 400 blk_pwrite(pfl->blk, offset, pfl->storage + offset, 401 offset_end - offset, 0); 402 } 403 } 404 405 static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset) 406 { 407 SectorInfo sector_info = pflash_sector_info(pfl, offset); 408 uint64_t sector_len = sector_info.len; 409 offset &= ~(sector_len - 1); 410 DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n", 411 __func__, pfl->width * 2, offset, 412 pfl->width * 2, offset + sector_len - 1); 413 if (!pfl->ro) { 414 uint8_t *p = pfl->storage; 415 memset(p + offset, 0xff, sector_len); 416 pflash_update(pfl, offset, sector_len); 417 } 418 set_dq7(pfl, 0x00); 419 ++pfl->sectors_to_erase; 420 set_bit(sector_info.num, pfl->sector_erase_map); 421 /* Set (or reset) the 50 us timer for additional erase commands. */ 422 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000); 423 } 424 425 static void pflash_write(void *opaque, hwaddr offset, uint64_t value, 426 unsigned int width) 427 { 428 PFlashCFI02 *pfl = opaque; 429 hwaddr boff; 430 uint8_t *p; 431 uint8_t cmd; 432 433 trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); 434 cmd = value; 435 if (pfl->cmd != 0xA0) { 436 /* Reset does nothing during chip erase and sector erase. */ 437 if (cmd == 0xF0 && pfl->cmd != 0x10 && pfl->cmd != 0x30) { 438 if (pfl->wcycle == WCYCLE_AUTOSELECT_CFI) { 439 /* Return to autoselect mode. */ 440 pfl->wcycle = 3; 441 pfl->cmd = 0x90; 442 return; 443 } 444 goto reset_flash; 445 } 446 } 447 offset &= pfl->chip_len - 1; 448 449 boff = offset; 450 if (pfl->width == 2) { 451 boff = boff >> 1; 452 } else if (pfl->width == 4) { 453 boff = boff >> 2; 454 } 455 /* Only the least-significant 11 bits are used in most cases. */ 456 boff &= 0x7FF; 457 switch (pfl->wcycle) { 458 case 0: 459 /* Set the device in I/O access mode if required */ 460 if (pfl->rom_mode) 461 pflash_register_memory(pfl, 0); 462 pfl->read_counter = 0; 463 /* We're in read mode */ 464 check_unlock0: 465 if (boff == 0x55 && cmd == 0x98) { 466 /* Enter CFI query mode */ 467 pfl->wcycle = WCYCLE_CFI; 468 pfl->cmd = 0x98; 469 return; 470 } 471 /* Handle erase resume in erase suspend mode, otherwise reset. */ 472 if (cmd == 0x30) { /* Erase Resume */ 473 if (pflash_erase_suspend_mode(pfl)) { 474 /* Resume the erase. */ 475 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 476 pfl->erase_time_remaining); 477 pfl->erase_time_remaining = 0; 478 pfl->wcycle = 6; 479 pfl->cmd = 0x30; 480 set_dq7(pfl, 0x00); 481 assert_dq3(pfl); 482 return; 483 } 484 goto reset_flash; 485 } 486 /* Ignore erase suspend. */ 487 if (cmd == 0xB0) { /* Erase Suspend */ 488 return; 489 } 490 if (boff != pfl->unlock_addr0 || cmd != 0xAA) { 491 DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", 492 __func__, boff, cmd, pfl->unlock_addr0); 493 goto reset_flash; 494 } 495 DPRINTF("%s: unlock sequence started\n", __func__); 496 break; 497 case 1: 498 /* We started an unlock sequence */ 499 check_unlock1: 500 if (boff != pfl->unlock_addr1 || cmd != 0x55) { 501 DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, 502 boff, cmd); 503 goto reset_flash; 504 } 505 DPRINTF("%s: unlock sequence done\n", __func__); 506 break; 507 case 2: 508 /* We finished an unlock sequence */ 509 if (!pfl->bypass && boff != pfl->unlock_addr0) { 510 DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, 511 boff, cmd); 512 goto reset_flash; 513 } 514 switch (cmd) { 515 case 0x20: 516 pfl->bypass = 1; 517 goto do_bypass; 518 case 0x80: /* Erase */ 519 case 0x90: /* Autoselect */ 520 case 0xA0: /* Program */ 521 pfl->cmd = cmd; 522 DPRINTF("%s: starting command %02x\n", __func__, cmd); 523 break; 524 default: 525 DPRINTF("%s: unknown command %02x\n", __func__, cmd); 526 goto reset_flash; 527 } 528 break; 529 case 3: 530 switch (pfl->cmd) { 531 case 0x80: /* Erase */ 532 /* We need another unlock sequence */ 533 goto check_unlock0; 534 case 0xA0: /* Program */ 535 if (pflash_erase_suspend_mode(pfl) && 536 pflash_sector_is_erasing(pfl, offset)) { 537 /* Ignore writes to erasing sectors. */ 538 if (pfl->bypass) { 539 goto do_bypass; 540 } 541 goto reset_flash; 542 } 543 trace_pflash_data_write(offset, width << 1, value, 0); 544 if (!pfl->ro) { 545 p = (uint8_t *)pfl->storage + offset; 546 if (pfl->be) { 547 uint64_t current = ldn_be_p(p, width); 548 stn_be_p(p, width, current & value); 549 } else { 550 uint64_t current = ldn_le_p(p, width); 551 stn_le_p(p, width, current & value); 552 } 553 pflash_update(pfl, offset, width); 554 } 555 /* 556 * While programming, status bit DQ7 should hold the opposite 557 * value from how it was programmed. 558 */ 559 set_dq7(pfl, ~value); 560 /* Let's pretend write is immediate */ 561 if (pfl->bypass) 562 goto do_bypass; 563 goto reset_flash; 564 case 0x90: /* Autoselect */ 565 if (pfl->bypass && cmd == 0x00) { 566 /* Unlock bypass reset */ 567 goto reset_flash; 568 } 569 /* 570 * We can enter CFI query mode from autoselect mode, but we must 571 * return to autoselect mode after a reset. 572 */ 573 if (boff == 0x55 && cmd == 0x98) { 574 /* Enter autoselect CFI query mode */ 575 pfl->wcycle = WCYCLE_AUTOSELECT_CFI; 576 pfl->cmd = 0x98; 577 return; 578 } 579 /* No break here */ 580 default: 581 DPRINTF("%s: invalid write for command %02x\n", 582 __func__, pfl->cmd); 583 goto reset_flash; 584 } 585 case 4: 586 switch (pfl->cmd) { 587 case 0xA0: /* Program */ 588 /* Ignore writes while flash data write is occurring */ 589 /* As we suppose write is immediate, this should never happen */ 590 return; 591 case 0x80: /* Erase */ 592 goto check_unlock1; 593 default: 594 /* Should never happen */ 595 DPRINTF("%s: invalid command state %02x (wc 4)\n", 596 __func__, pfl->cmd); 597 goto reset_flash; 598 } 599 break; 600 case 5: 601 if (pflash_erase_suspend_mode(pfl)) { 602 /* Erasing is not supported in erase suspend mode. */ 603 goto reset_flash; 604 } 605 switch (cmd) { 606 case 0x10: /* Chip Erase */ 607 if (boff != pfl->unlock_addr0) { 608 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", 609 __func__, offset); 610 goto reset_flash; 611 } 612 /* Chip erase */ 613 DPRINTF("%s: start chip erase\n", __func__); 614 if (!pfl->ro) { 615 memset(pfl->storage, 0xff, pfl->chip_len); 616 pflash_update(pfl, 0, pfl->chip_len); 617 } 618 set_dq7(pfl, 0x00); 619 /* Wait the time specified at CFI address 0x22. */ 620 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 621 (1ULL << pfl->cfi_table[0x22]) * SCALE_MS); 622 break; 623 case 0x30: /* Sector erase */ 624 pflash_sector_erase(pfl, offset); 625 break; 626 default: 627 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); 628 goto reset_flash; 629 } 630 pfl->cmd = cmd; 631 break; 632 case 6: 633 switch (pfl->cmd) { 634 case 0x10: /* Chip Erase */ 635 /* Ignore writes during chip erase */ 636 return; 637 case 0x30: /* Sector erase */ 638 if (cmd == 0xB0) { 639 /* 640 * If erase suspend happens during the erase timeout (so DQ3 is 641 * 0), then the device suspends erasing immediately. Set the 642 * remaining time to be the total time to erase. Otherwise, 643 * there is a maximum amount of time it can take to enter 644 * suspend mode. Let's ignore that and suspend immediately and 645 * set the remaining time to the actual time remaining on the 646 * timer. 647 */ 648 if ((pfl->status & 0x08) == 0) { 649 pfl->erase_time_remaining = pflash_erase_time(pfl); 650 } else { 651 int64_t delta = timer_expire_time_ns(&pfl->timer) - 652 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 653 /* Make sure we have a positive time remaining. */ 654 pfl->erase_time_remaining = delta <= 0 ? 1 : delta; 655 } 656 reset_dq3(pfl); 657 timer_del(&pfl->timer); 658 pfl->wcycle = 0; 659 pfl->cmd = 0; 660 return; 661 } 662 /* 663 * If DQ3 is 0, additional sector erase commands can be 664 * written and anything else (other than an erase suspend) resets 665 * the device. 666 */ 667 if ((pfl->status & 0x08) == 0) { 668 if (cmd == 0x30) { 669 pflash_sector_erase(pfl, offset); 670 } else { 671 goto reset_flash; 672 } 673 } 674 /* Ignore writes during the actual erase. */ 675 return; 676 default: 677 /* Should never happen */ 678 DPRINTF("%s: invalid command state %02x (wc 6)\n", 679 __func__, pfl->cmd); 680 goto reset_flash; 681 } 682 break; 683 /* Special values for CFI queries */ 684 case WCYCLE_CFI: 685 case WCYCLE_AUTOSELECT_CFI: 686 DPRINTF("%s: invalid write in CFI query mode\n", __func__); 687 goto reset_flash; 688 default: 689 /* Should never happen */ 690 DPRINTF("%s: invalid write state (wc 7)\n", __func__); 691 goto reset_flash; 692 } 693 pfl->wcycle++; 694 695 return; 696 697 /* Reset flash */ 698 reset_flash: 699 trace_pflash_reset(); 700 pfl->bypass = 0; 701 pfl->wcycle = 0; 702 pfl->cmd = 0; 703 return; 704 705 do_bypass: 706 pfl->wcycle = 2; 707 pfl->cmd = 0; 708 } 709 710 static const MemoryRegionOps pflash_cfi02_ops = { 711 .read = pflash_read, 712 .write = pflash_write, 713 .valid.min_access_size = 1, 714 .valid.max_access_size = 4, 715 .endianness = DEVICE_NATIVE_ENDIAN, 716 }; 717 718 static void pflash_cfi02_realize(DeviceState *dev, Error **errp) 719 { 720 PFlashCFI02 *pfl = PFLASH_CFI02(dev); 721 int ret; 722 Error *local_err = NULL; 723 724 if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) { 725 error_setg(errp, "attribute \"sector-length\" not specified or zero."); 726 return; 727 } 728 if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) { 729 error_setg(errp, "attribute \"num-blocks\" not specified or zero."); 730 return; 731 } 732 if (pfl->name == NULL) { 733 error_setg(errp, "attribute \"name\" not specified."); 734 return; 735 } 736 737 int nb_regions; 738 pfl->chip_len = 0; 739 pfl->total_sectors = 0; 740 for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) { 741 if (pfl->nb_blocs[nb_regions] == 0) { 742 break; 743 } 744 pfl->total_sectors += pfl->nb_blocs[nb_regions]; 745 uint64_t sector_len_per_device = pfl->sector_len[nb_regions]; 746 747 /* 748 * The size of each flash sector must be a power of 2 and it must be 749 * aligned at the same power of 2. 750 */ 751 if (sector_len_per_device & 0xff || 752 sector_len_per_device >= (1 << 24) || 753 !is_power_of_2(sector_len_per_device)) 754 { 755 error_setg(errp, "unsupported configuration: " 756 "sector length[%d] per device = %" PRIx64 ".", 757 nb_regions, sector_len_per_device); 758 return; 759 } 760 if (pfl->chip_len & (sector_len_per_device - 1)) { 761 error_setg(errp, "unsupported configuration: " 762 "flash region %d not correctly aligned.", 763 nb_regions); 764 return; 765 } 766 767 pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] * 768 pfl->nb_blocs[nb_regions]; 769 } 770 771 uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs * 772 pfl->uniform_sector_len; 773 if (nb_regions == 0) { 774 nb_regions = 1; 775 pfl->nb_blocs[0] = pfl->uniform_nb_blocs; 776 pfl->sector_len[0] = pfl->uniform_sector_len; 777 pfl->chip_len = uniform_len; 778 pfl->total_sectors = pfl->uniform_nb_blocs; 779 } else if (uniform_len != 0 && uniform_len != pfl->chip_len) { 780 error_setg(errp, "\"num-blocks\"*\"sector-length\" " 781 "different from \"num-blocks0\"*\'sector-length0\" + ... + " 782 "\"num-blocks3\"*\"sector-length3\""); 783 return; 784 } 785 786 memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), 787 &pflash_cfi02_ops, pfl, pfl->name, 788 pfl->chip_len, &local_err); 789 if (local_err) { 790 error_propagate(errp, local_err); 791 return; 792 } 793 794 pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); 795 796 if (pfl->blk) { 797 uint64_t perm; 798 pfl->ro = blk_is_read_only(pfl->blk); 799 perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE); 800 ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp); 801 if (ret < 0) { 802 return; 803 } 804 } else { 805 pfl->ro = 0; 806 } 807 808 if (pfl->blk) { 809 if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, 810 pfl->chip_len, errp)) { 811 vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl)); 812 return; 813 } 814 } 815 816 /* Only 11 bits are used in the comparison. */ 817 pfl->unlock_addr0 &= 0x7FF; 818 pfl->unlock_addr1 &= 0x7FF; 819 820 /* Allocate memory for a bitmap for sectors being erased. */ 821 pfl->sector_erase_map = bitmap_new(pfl->total_sectors); 822 823 pflash_setup_mappings(pfl); 824 pfl->rom_mode = 1; 825 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); 826 827 timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); 828 pfl->wcycle = 0; 829 pfl->cmd = 0; 830 pfl->status = 0; 831 832 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ 833 const uint16_t pri_ofs = 0x40; 834 /* Standard "QRY" string */ 835 pfl->cfi_table[0x10] = 'Q'; 836 pfl->cfi_table[0x11] = 'R'; 837 pfl->cfi_table[0x12] = 'Y'; 838 /* Command set (AMD/Fujitsu) */ 839 pfl->cfi_table[0x13] = 0x02; 840 pfl->cfi_table[0x14] = 0x00; 841 /* Primary extended table address */ 842 pfl->cfi_table[0x15] = pri_ofs; 843 pfl->cfi_table[0x16] = pri_ofs >> 8; 844 /* Alternate command set (none) */ 845 pfl->cfi_table[0x17] = 0x00; 846 pfl->cfi_table[0x18] = 0x00; 847 /* Alternate extended table (none) */ 848 pfl->cfi_table[0x19] = 0x00; 849 pfl->cfi_table[0x1A] = 0x00; 850 /* Vcc min */ 851 pfl->cfi_table[0x1B] = 0x27; 852 /* Vcc max */ 853 pfl->cfi_table[0x1C] = 0x36; 854 /* Vpp min (no Vpp pin) */ 855 pfl->cfi_table[0x1D] = 0x00; 856 /* Vpp max (no Vpp pin) */ 857 pfl->cfi_table[0x1E] = 0x00; 858 /* Timeout per single byte/word write (128 ms) */ 859 pfl->cfi_table[0x1F] = 0x07; 860 /* Timeout for min size buffer write (NA) */ 861 pfl->cfi_table[0x20] = 0x00; 862 /* Typical timeout for block erase (512 ms) */ 863 pfl->cfi_table[0x21] = 0x09; 864 /* Typical timeout for full chip erase (4096 ms) */ 865 pfl->cfi_table[0x22] = 0x0C; 866 /* Reserved */ 867 pfl->cfi_table[0x23] = 0x01; 868 /* Max timeout for buffer write (NA) */ 869 pfl->cfi_table[0x24] = 0x00; 870 /* Max timeout for block erase */ 871 pfl->cfi_table[0x25] = 0x0A; 872 /* Max timeout for chip erase */ 873 pfl->cfi_table[0x26] = 0x0D; 874 /* Device size */ 875 pfl->cfi_table[0x27] = ctz32(pfl->chip_len); 876 /* Flash device interface (8 & 16 bits) */ 877 pfl->cfi_table[0x28] = 0x02; 878 pfl->cfi_table[0x29] = 0x00; 879 /* Max number of bytes in multi-bytes write */ 880 /* XXX: disable buffered write as it's not supported */ 881 // pfl->cfi_table[0x2A] = 0x05; 882 pfl->cfi_table[0x2A] = 0x00; 883 pfl->cfi_table[0x2B] = 0x00; 884 /* Number of erase block regions */ 885 pfl->cfi_table[0x2c] = nb_regions; 886 /* Erase block regions */ 887 for (int i = 0; i < nb_regions; ++i) { 888 uint32_t sector_len_per_device = pfl->sector_len[i]; 889 pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1; 890 pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8; 891 pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8; 892 pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16; 893 } 894 assert(0x2c + 4 * nb_regions < pri_ofs); 895 896 /* Extended */ 897 pfl->cfi_table[0x00 + pri_ofs] = 'P'; 898 pfl->cfi_table[0x01 + pri_ofs] = 'R'; 899 pfl->cfi_table[0x02 + pri_ofs] = 'I'; 900 901 /* Extended version 1.0 */ 902 pfl->cfi_table[0x03 + pri_ofs] = '1'; 903 pfl->cfi_table[0x04 + pri_ofs] = '0'; 904 905 /* Address sensitive unlock required. */ 906 pfl->cfi_table[0x05 + pri_ofs] = 0x00; 907 /* Erase suspend to read/write. */ 908 pfl->cfi_table[0x06 + pri_ofs] = 0x02; 909 /* Sector protect not supported. */ 910 pfl->cfi_table[0x07 + pri_ofs] = 0x00; 911 /* Temporary sector unprotect not supported. */ 912 pfl->cfi_table[0x08 + pri_ofs] = 0x00; 913 914 /* Sector protect/unprotect scheme. */ 915 pfl->cfi_table[0x09 + pri_ofs] = 0x00; 916 917 /* Simultaneous operation not supported. */ 918 pfl->cfi_table[0x0a + pri_ofs] = 0x00; 919 /* Burst mode not supported. */ 920 pfl->cfi_table[0x0b + pri_ofs] = 0x00; 921 /* Page mode not supported. */ 922 pfl->cfi_table[0x0c + pri_ofs] = 0x00; 923 assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table)); 924 } 925 926 static Property pflash_cfi02_properties[] = { 927 DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk), 928 DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0), 929 DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0), 930 DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0), 931 DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0), 932 DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0), 933 DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0), 934 DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0), 935 DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0), 936 DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0), 937 DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0), 938 DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0), 939 DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0), 940 DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0), 941 DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0), 942 DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0), 943 DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0), 944 DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0), 945 DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0), 946 DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0), 947 DEFINE_PROP_STRING("name", PFlashCFI02, name), 948 DEFINE_PROP_END_OF_LIST(), 949 }; 950 951 static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp) 952 { 953 PFlashCFI02 *pfl = PFLASH_CFI02(dev); 954 timer_del(&pfl->timer); 955 g_free(pfl->sector_erase_map); 956 } 957 958 static void pflash_cfi02_class_init(ObjectClass *klass, void *data) 959 { 960 DeviceClass *dc = DEVICE_CLASS(klass); 961 962 dc->realize = pflash_cfi02_realize; 963 dc->unrealize = pflash_cfi02_unrealize; 964 dc->props = pflash_cfi02_properties; 965 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 966 } 967 968 static const TypeInfo pflash_cfi02_info = { 969 .name = TYPE_PFLASH_CFI02, 970 .parent = TYPE_SYS_BUS_DEVICE, 971 .instance_size = sizeof(PFlashCFI02), 972 .class_init = pflash_cfi02_class_init, 973 }; 974 975 static void pflash_cfi02_register_types(void) 976 { 977 type_register_static(&pflash_cfi02_info); 978 } 979 980 type_init(pflash_cfi02_register_types) 981 982 PFlashCFI02 *pflash_cfi02_register(hwaddr base, 983 const char *name, 984 hwaddr size, 985 BlockBackend *blk, 986 uint32_t sector_len, 987 int nb_mappings, int width, 988 uint16_t id0, uint16_t id1, 989 uint16_t id2, uint16_t id3, 990 uint16_t unlock_addr0, 991 uint16_t unlock_addr1, 992 int be) 993 { 994 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02); 995 996 if (blk) { 997 qdev_prop_set_drive(dev, "drive", blk, &error_abort); 998 } 999 assert(size % sector_len == 0); 1000 qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); 1001 qdev_prop_set_uint32(dev, "sector-length", sector_len); 1002 qdev_prop_set_uint8(dev, "width", width); 1003 qdev_prop_set_uint8(dev, "mappings", nb_mappings); 1004 qdev_prop_set_uint8(dev, "big-endian", !!be); 1005 qdev_prop_set_uint16(dev, "id0", id0); 1006 qdev_prop_set_uint16(dev, "id1", id1); 1007 qdev_prop_set_uint16(dev, "id2", id2); 1008 qdev_prop_set_uint16(dev, "id3", id3); 1009 qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); 1010 qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); 1011 qdev_prop_set_string(dev, "name", name); 1012 qdev_init_nofail(dev); 1013 1014 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1015 return PFLASH_CFI02(dev); 1016 } 1017