1 /* 2 * CFI parallel flash with Intel command set emulation 3 * 4 * Copyright (c) 2006 Thorsten Zitterell 5 * Copyright (c) 2005 Jocelyn Mayer 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width. 23 * Supported commands/modes are: 24 * - flash read 25 * - flash write 26 * - flash ID read 27 * - sector erase 28 * - CFI queries 29 * 30 * It does not support timings 31 * It does not support flash interleaving 32 * It does not implement software data protection as found in many real chips 33 * It does not implement erase suspend/resume commands 34 * It does not implement multiple sectors erase 35 * 36 * It does not implement much more ... 37 */ 38 39 #include "hw/hw.h" 40 #include "hw/block/flash.h" 41 #include "block/block.h" 42 #include "qemu/timer.h" 43 #include "exec/address-spaces.h" 44 #include "qemu/host-utils.h" 45 #include "hw/sysbus.h" 46 47 #define PFLASH_BUG(fmt, ...) \ 48 do { \ 49 fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \ 50 exit(1); \ 51 } while(0) 52 53 /* #define PFLASH_DEBUG */ 54 #ifdef PFLASH_DEBUG 55 #define DPRINTF(fmt, ...) \ 56 do { \ 57 fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \ 58 } while (0) 59 #else 60 #define DPRINTF(fmt, ...) do { } while (0) 61 #endif 62 63 #define TYPE_CFI_PFLASH01 "cfi.pflash01" 64 #define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01) 65 66 struct pflash_t { 67 /*< private >*/ 68 SysBusDevice parent_obj; 69 /*< public >*/ 70 71 BlockDriverState *bs; 72 uint32_t nb_blocs; 73 uint64_t sector_len; 74 uint8_t width; 75 uint8_t be; 76 uint8_t wcycle; /* if 0, the flash is read normally */ 77 int ro; 78 uint8_t cmd; 79 uint8_t status; 80 uint16_t ident0; 81 uint16_t ident1; 82 uint16_t ident2; 83 uint16_t ident3; 84 uint8_t cfi_len; 85 uint8_t cfi_table[0x52]; 86 uint64_t counter; 87 unsigned int writeblock_size; 88 QEMUTimer *timer; 89 MemoryRegion mem; 90 char *name; 91 void *storage; 92 }; 93 94 static const VMStateDescription vmstate_pflash = { 95 .name = "pflash_cfi01", 96 .version_id = 1, 97 .minimum_version_id = 1, 98 .fields = (VMStateField[]) { 99 VMSTATE_UINT8(wcycle, pflash_t), 100 VMSTATE_UINT8(cmd, pflash_t), 101 VMSTATE_UINT8(status, pflash_t), 102 VMSTATE_UINT64(counter, pflash_t), 103 VMSTATE_END_OF_LIST() 104 } 105 }; 106 107 static void pflash_timer (void *opaque) 108 { 109 pflash_t *pfl = opaque; 110 111 DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); 112 /* Reset flash */ 113 pfl->status ^= 0x80; 114 memory_region_rom_device_set_romd(&pfl->mem, true); 115 pfl->wcycle = 0; 116 pfl->cmd = 0; 117 } 118 119 static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, 120 int width, int be) 121 { 122 hwaddr boff; 123 uint32_t ret; 124 uint8_t *p; 125 126 ret = -1; 127 boff = offset & 0xFF; /* why this here ?? */ 128 129 if (pfl->width == 2) 130 boff = boff >> 1; 131 else if (pfl->width == 4) 132 boff = boff >> 2; 133 134 #if 0 135 DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n", 136 __func__, offset, pfl->cmd, width); 137 #endif 138 switch (pfl->cmd) { 139 default: 140 /* This should never happen : reset state & treat it as a read */ 141 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); 142 pfl->wcycle = 0; 143 pfl->cmd = 0; 144 /* fall through to read code */ 145 case 0x00: 146 /* Flash area read */ 147 p = pfl->storage; 148 switch (width) { 149 case 1: 150 ret = p[offset]; 151 DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n", 152 __func__, offset, ret); 153 break; 154 case 2: 155 if (be) { 156 ret = p[offset] << 8; 157 ret |= p[offset + 1]; 158 } else { 159 ret = p[offset]; 160 ret |= p[offset + 1] << 8; 161 } 162 DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n", 163 __func__, offset, ret); 164 break; 165 case 4: 166 if (be) { 167 ret = p[offset] << 24; 168 ret |= p[offset + 1] << 16; 169 ret |= p[offset + 2] << 8; 170 ret |= p[offset + 3]; 171 } else { 172 ret = p[offset]; 173 ret |= p[offset + 1] << 8; 174 ret |= p[offset + 2] << 16; 175 ret |= p[offset + 3] << 24; 176 } 177 DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n", 178 __func__, offset, ret); 179 break; 180 default: 181 DPRINTF("BUG in %s\n", __func__); 182 } 183 184 break; 185 case 0x10: /* Single byte program */ 186 case 0x20: /* Block erase */ 187 case 0x28: /* Block erase */ 188 case 0x40: /* single byte program */ 189 case 0x50: /* Clear status register */ 190 case 0x60: /* Block /un)lock */ 191 case 0x70: /* Status Register */ 192 case 0xe8: /* Write block */ 193 /* Status register read */ 194 ret = pfl->status; 195 DPRINTF("%s: status %x\n", __func__, ret); 196 break; 197 case 0x90: 198 switch (boff) { 199 case 0: 200 ret = pfl->ident0 << 8 | pfl->ident1; 201 DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret); 202 break; 203 case 1: 204 ret = pfl->ident2 << 8 | pfl->ident3; 205 DPRINTF("%s: Device ID Code %04x\n", __func__, ret); 206 break; 207 default: 208 DPRINTF("%s: Read Device Information boff=%x\n", __func__, 209 (unsigned)boff); 210 ret = 0; 211 break; 212 } 213 break; 214 case 0x98: /* Query mode */ 215 if (boff > pfl->cfi_len) 216 ret = 0; 217 else 218 ret = pfl->cfi_table[boff]; 219 break; 220 } 221 return ret; 222 } 223 224 /* update flash content on disk */ 225 static void pflash_update(pflash_t *pfl, int offset, 226 int size) 227 { 228 int offset_end; 229 if (pfl->bs) { 230 offset_end = offset + size; 231 /* round to sectors */ 232 offset = offset >> 9; 233 offset_end = (offset_end + 511) >> 9; 234 bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9), 235 offset_end - offset); 236 } 237 } 238 239 static inline void pflash_data_write(pflash_t *pfl, hwaddr offset, 240 uint32_t value, int width, int be) 241 { 242 uint8_t *p = pfl->storage; 243 244 DPRINTF("%s: block write offset " TARGET_FMT_plx 245 " value %x counter %016" PRIx64 "\n", 246 __func__, offset, value, pfl->counter); 247 switch (width) { 248 case 1: 249 p[offset] = value; 250 break; 251 case 2: 252 if (be) { 253 p[offset] = value >> 8; 254 p[offset + 1] = value; 255 } else { 256 p[offset] = value; 257 p[offset + 1] = value >> 8; 258 } 259 break; 260 case 4: 261 if (be) { 262 p[offset] = value >> 24; 263 p[offset + 1] = value >> 16; 264 p[offset + 2] = value >> 8; 265 p[offset + 3] = value; 266 } else { 267 p[offset] = value; 268 p[offset + 1] = value >> 8; 269 p[offset + 2] = value >> 16; 270 p[offset + 3] = value >> 24; 271 } 272 break; 273 } 274 275 } 276 277 static void pflash_write(pflash_t *pfl, hwaddr offset, 278 uint32_t value, int width, int be) 279 { 280 uint8_t *p; 281 uint8_t cmd; 282 283 cmd = value; 284 285 DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n", 286 __func__, offset, value, width, pfl->wcycle); 287 288 if (!pfl->wcycle) { 289 /* Set the device in I/O access mode */ 290 memory_region_rom_device_set_romd(&pfl->mem, false); 291 } 292 293 switch (pfl->wcycle) { 294 case 0: 295 /* read mode */ 296 switch (cmd) { 297 case 0x00: /* ??? */ 298 goto reset_flash; 299 case 0x10: /* Single Byte Program */ 300 case 0x40: /* Single Byte Program */ 301 DPRINTF("%s: Single Byte Program\n", __func__); 302 break; 303 case 0x20: /* Block erase */ 304 p = pfl->storage; 305 offset &= ~(pfl->sector_len - 1); 306 307 DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n", 308 __func__, offset, (unsigned)pfl->sector_len); 309 310 if (!pfl->ro) { 311 memset(p + offset, 0xff, pfl->sector_len); 312 pflash_update(pfl, offset, pfl->sector_len); 313 } else { 314 pfl->status |= 0x20; /* Block erase error */ 315 } 316 pfl->status |= 0x80; /* Ready! */ 317 break; 318 case 0x50: /* Clear status bits */ 319 DPRINTF("%s: Clear status bits\n", __func__); 320 pfl->status = 0x0; 321 goto reset_flash; 322 case 0x60: /* Block (un)lock */ 323 DPRINTF("%s: Block unlock\n", __func__); 324 break; 325 case 0x70: /* Status Register */ 326 DPRINTF("%s: Read status register\n", __func__); 327 pfl->cmd = cmd; 328 return; 329 case 0x90: /* Read Device ID */ 330 DPRINTF("%s: Read Device information\n", __func__); 331 pfl->cmd = cmd; 332 return; 333 case 0x98: /* CFI query */ 334 DPRINTF("%s: CFI query\n", __func__); 335 break; 336 case 0xe8: /* Write to buffer */ 337 DPRINTF("%s: Write to buffer\n", __func__); 338 pfl->status |= 0x80; /* Ready! */ 339 break; 340 case 0xf0: /* Probe for AMD flash */ 341 DPRINTF("%s: Probe for AMD flash\n", __func__); 342 goto reset_flash; 343 case 0xff: /* Read array mode */ 344 DPRINTF("%s: Read array mode\n", __func__); 345 goto reset_flash; 346 default: 347 goto error_flash; 348 } 349 pfl->wcycle++; 350 pfl->cmd = cmd; 351 break; 352 case 1: 353 switch (pfl->cmd) { 354 case 0x10: /* Single Byte Program */ 355 case 0x40: /* Single Byte Program */ 356 DPRINTF("%s: Single Byte Program\n", __func__); 357 if (!pfl->ro) { 358 pflash_data_write(pfl, offset, value, width, be); 359 pflash_update(pfl, offset, width); 360 } else { 361 pfl->status |= 0x10; /* Programming error */ 362 } 363 pfl->status |= 0x80; /* Ready! */ 364 pfl->wcycle = 0; 365 break; 366 case 0x20: /* Block erase */ 367 case 0x28: 368 if (cmd == 0xd0) { /* confirm */ 369 pfl->wcycle = 0; 370 pfl->status |= 0x80; 371 } else if (cmd == 0xff) { /* read array mode */ 372 goto reset_flash; 373 } else 374 goto error_flash; 375 376 break; 377 case 0xe8: 378 DPRINTF("%s: block write of %x bytes\n", __func__, value); 379 pfl->counter = value; 380 pfl->wcycle++; 381 break; 382 case 0x60: 383 if (cmd == 0xd0) { 384 pfl->wcycle = 0; 385 pfl->status |= 0x80; 386 } else if (cmd == 0x01) { 387 pfl->wcycle = 0; 388 pfl->status |= 0x80; 389 } else if (cmd == 0xff) { 390 goto reset_flash; 391 } else { 392 DPRINTF("%s: Unknown (un)locking command\n", __func__); 393 goto reset_flash; 394 } 395 break; 396 case 0x98: 397 if (cmd == 0xff) { 398 goto reset_flash; 399 } else { 400 DPRINTF("%s: leaving query mode\n", __func__); 401 } 402 break; 403 default: 404 goto error_flash; 405 } 406 break; 407 case 2: 408 switch (pfl->cmd) { 409 case 0xe8: /* Block write */ 410 if (!pfl->ro) { 411 pflash_data_write(pfl, offset, value, width, be); 412 } else { 413 pfl->status |= 0x10; /* Programming error */ 414 } 415 416 pfl->status |= 0x80; 417 418 if (!pfl->counter) { 419 hwaddr mask = pfl->writeblock_size - 1; 420 mask = ~mask; 421 422 DPRINTF("%s: block write finished\n", __func__); 423 pfl->wcycle++; 424 if (!pfl->ro) { 425 /* Flush the entire write buffer onto backing storage. */ 426 pflash_update(pfl, offset & mask, pfl->writeblock_size); 427 } else { 428 pfl->status |= 0x10; /* Programming error */ 429 } 430 } 431 432 pfl->counter--; 433 break; 434 default: 435 goto error_flash; 436 } 437 break; 438 case 3: /* Confirm mode */ 439 switch (pfl->cmd) { 440 case 0xe8: /* Block write */ 441 if (cmd == 0xd0) { 442 pfl->wcycle = 0; 443 pfl->status |= 0x80; 444 } else { 445 DPRINTF("%s: unknown command for \"write block\"\n", __func__); 446 PFLASH_BUG("Write block confirm"); 447 goto reset_flash; 448 } 449 break; 450 default: 451 goto error_flash; 452 } 453 break; 454 default: 455 /* Should never happen */ 456 DPRINTF("%s: invalid write state\n", __func__); 457 goto reset_flash; 458 } 459 return; 460 461 error_flash: 462 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence " 463 "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" 464 "\n", __func__, offset, pfl->wcycle, pfl->cmd, value); 465 466 reset_flash: 467 memory_region_rom_device_set_romd(&pfl->mem, true); 468 469 pfl->wcycle = 0; 470 pfl->cmd = 0; 471 } 472 473 474 static uint32_t pflash_readb_be(void *opaque, hwaddr addr) 475 { 476 return pflash_read(opaque, addr, 1, 1); 477 } 478 479 static uint32_t pflash_readb_le(void *opaque, hwaddr addr) 480 { 481 return pflash_read(opaque, addr, 1, 0); 482 } 483 484 static uint32_t pflash_readw_be(void *opaque, hwaddr addr) 485 { 486 pflash_t *pfl = opaque; 487 488 return pflash_read(pfl, addr, 2, 1); 489 } 490 491 static uint32_t pflash_readw_le(void *opaque, hwaddr addr) 492 { 493 pflash_t *pfl = opaque; 494 495 return pflash_read(pfl, addr, 2, 0); 496 } 497 498 static uint32_t pflash_readl_be(void *opaque, hwaddr addr) 499 { 500 pflash_t *pfl = opaque; 501 502 return pflash_read(pfl, addr, 4, 1); 503 } 504 505 static uint32_t pflash_readl_le(void *opaque, hwaddr addr) 506 { 507 pflash_t *pfl = opaque; 508 509 return pflash_read(pfl, addr, 4, 0); 510 } 511 512 static void pflash_writeb_be(void *opaque, hwaddr addr, 513 uint32_t value) 514 { 515 pflash_write(opaque, addr, value, 1, 1); 516 } 517 518 static void pflash_writeb_le(void *opaque, hwaddr addr, 519 uint32_t value) 520 { 521 pflash_write(opaque, addr, value, 1, 0); 522 } 523 524 static void pflash_writew_be(void *opaque, hwaddr addr, 525 uint32_t value) 526 { 527 pflash_t *pfl = opaque; 528 529 pflash_write(pfl, addr, value, 2, 1); 530 } 531 532 static void pflash_writew_le(void *opaque, hwaddr addr, 533 uint32_t value) 534 { 535 pflash_t *pfl = opaque; 536 537 pflash_write(pfl, addr, value, 2, 0); 538 } 539 540 static void pflash_writel_be(void *opaque, hwaddr addr, 541 uint32_t value) 542 { 543 pflash_t *pfl = opaque; 544 545 pflash_write(pfl, addr, value, 4, 1); 546 } 547 548 static void pflash_writel_le(void *opaque, hwaddr addr, 549 uint32_t value) 550 { 551 pflash_t *pfl = opaque; 552 553 pflash_write(pfl, addr, value, 4, 0); 554 } 555 556 static const MemoryRegionOps pflash_cfi01_ops_be = { 557 .old_mmio = { 558 .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, 559 .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, 560 }, 561 .endianness = DEVICE_NATIVE_ENDIAN, 562 }; 563 564 static const MemoryRegionOps pflash_cfi01_ops_le = { 565 .old_mmio = { 566 .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, 567 .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, 568 }, 569 .endianness = DEVICE_NATIVE_ENDIAN, 570 }; 571 572 static void pflash_cfi01_realize(DeviceState *dev, Error **errp) 573 { 574 pflash_t *pfl = CFI_PFLASH01(dev); 575 uint64_t total_len; 576 int ret; 577 578 total_len = pfl->sector_len * pfl->nb_blocs; 579 580 /* XXX: to be fixed */ 581 #if 0 582 if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && 583 total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) 584 return NULL; 585 #endif 586 587 memory_region_init_rom_device( 588 &pfl->mem, OBJECT(dev), 589 pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl, 590 pfl->name, total_len); 591 vmstate_register_ram(&pfl->mem, DEVICE(pfl)); 592 pfl->storage = memory_region_get_ram_ptr(&pfl->mem); 593 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); 594 595 if (pfl->bs) { 596 /* read the initial flash content */ 597 ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); 598 599 if (ret < 0) { 600 vmstate_unregister_ram(&pfl->mem, DEVICE(pfl)); 601 memory_region_destroy(&pfl->mem); 602 error_setg(errp, "failed to read the initial flash content"); 603 return; 604 } 605 } 606 607 if (pfl->bs) { 608 pfl->ro = bdrv_is_read_only(pfl->bs); 609 } else { 610 pfl->ro = 0; 611 } 612 613 pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); 614 pfl->wcycle = 0; 615 pfl->cmd = 0; 616 pfl->status = 0; 617 /* Hardcoded CFI table */ 618 pfl->cfi_len = 0x52; 619 /* Standard "QRY" string */ 620 pfl->cfi_table[0x10] = 'Q'; 621 pfl->cfi_table[0x11] = 'R'; 622 pfl->cfi_table[0x12] = 'Y'; 623 /* Command set (Intel) */ 624 pfl->cfi_table[0x13] = 0x01; 625 pfl->cfi_table[0x14] = 0x00; 626 /* Primary extended table address (none) */ 627 pfl->cfi_table[0x15] = 0x31; 628 pfl->cfi_table[0x16] = 0x00; 629 /* Alternate command set (none) */ 630 pfl->cfi_table[0x17] = 0x00; 631 pfl->cfi_table[0x18] = 0x00; 632 /* Alternate extended table (none) */ 633 pfl->cfi_table[0x19] = 0x00; 634 pfl->cfi_table[0x1A] = 0x00; 635 /* Vcc min */ 636 pfl->cfi_table[0x1B] = 0x45; 637 /* Vcc max */ 638 pfl->cfi_table[0x1C] = 0x55; 639 /* Vpp min (no Vpp pin) */ 640 pfl->cfi_table[0x1D] = 0x00; 641 /* Vpp max (no Vpp pin) */ 642 pfl->cfi_table[0x1E] = 0x00; 643 /* Reserved */ 644 pfl->cfi_table[0x1F] = 0x07; 645 /* Timeout for min size buffer write */ 646 pfl->cfi_table[0x20] = 0x07; 647 /* Typical timeout for block erase */ 648 pfl->cfi_table[0x21] = 0x0a; 649 /* Typical timeout for full chip erase (4096 ms) */ 650 pfl->cfi_table[0x22] = 0x00; 651 /* Reserved */ 652 pfl->cfi_table[0x23] = 0x04; 653 /* Max timeout for buffer write */ 654 pfl->cfi_table[0x24] = 0x04; 655 /* Max timeout for block erase */ 656 pfl->cfi_table[0x25] = 0x04; 657 /* Max timeout for chip erase */ 658 pfl->cfi_table[0x26] = 0x00; 659 /* Device size */ 660 pfl->cfi_table[0x27] = ctz32(total_len); // + 1; 661 /* Flash device interface (8 & 16 bits) */ 662 pfl->cfi_table[0x28] = 0x02; 663 pfl->cfi_table[0x29] = 0x00; 664 /* Max number of bytes in multi-bytes write */ 665 if (pfl->width == 1) { 666 pfl->cfi_table[0x2A] = 0x08; 667 } else { 668 pfl->cfi_table[0x2A] = 0x0B; 669 } 670 pfl->writeblock_size = 1 << pfl->cfi_table[0x2A]; 671 672 pfl->cfi_table[0x2B] = 0x00; 673 /* Number of erase block regions (uniform) */ 674 pfl->cfi_table[0x2C] = 0x01; 675 /* Erase block region 1 */ 676 pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; 677 pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; 678 pfl->cfi_table[0x2F] = pfl->sector_len >> 8; 679 pfl->cfi_table[0x30] = pfl->sector_len >> 16; 680 681 /* Extended */ 682 pfl->cfi_table[0x31] = 'P'; 683 pfl->cfi_table[0x32] = 'R'; 684 pfl->cfi_table[0x33] = 'I'; 685 686 pfl->cfi_table[0x34] = '1'; 687 pfl->cfi_table[0x35] = '0'; 688 689 pfl->cfi_table[0x36] = 0x00; 690 pfl->cfi_table[0x37] = 0x00; 691 pfl->cfi_table[0x38] = 0x00; 692 pfl->cfi_table[0x39] = 0x00; 693 694 pfl->cfi_table[0x3a] = 0x00; 695 696 pfl->cfi_table[0x3b] = 0x00; 697 pfl->cfi_table[0x3c] = 0x00; 698 699 pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ 700 } 701 702 static Property pflash_cfi01_properties[] = { 703 DEFINE_PROP_DRIVE("drive", struct pflash_t, bs), 704 DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), 705 DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0), 706 DEFINE_PROP_UINT8("width", struct pflash_t, width, 0), 707 DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), 708 DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), 709 DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), 710 DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0), 711 DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0), 712 DEFINE_PROP_STRING("name", struct pflash_t, name), 713 DEFINE_PROP_END_OF_LIST(), 714 }; 715 716 static void pflash_cfi01_class_init(ObjectClass *klass, void *data) 717 { 718 DeviceClass *dc = DEVICE_CLASS(klass); 719 720 dc->realize = pflash_cfi01_realize; 721 dc->props = pflash_cfi01_properties; 722 dc->vmsd = &vmstate_pflash; 723 } 724 725 726 static const TypeInfo pflash_cfi01_info = { 727 .name = TYPE_CFI_PFLASH01, 728 .parent = TYPE_SYS_BUS_DEVICE, 729 .instance_size = sizeof(struct pflash_t), 730 .class_init = pflash_cfi01_class_init, 731 }; 732 733 static void pflash_cfi01_register_types(void) 734 { 735 type_register_static(&pflash_cfi01_info); 736 } 737 738 type_init(pflash_cfi01_register_types) 739 740 pflash_t *pflash_cfi01_register(hwaddr base, 741 DeviceState *qdev, const char *name, 742 hwaddr size, 743 BlockDriverState *bs, 744 uint32_t sector_len, int nb_blocs, int width, 745 uint16_t id0, uint16_t id1, 746 uint16_t id2, uint16_t id3, int be) 747 { 748 DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH01); 749 750 if (bs && qdev_prop_set_drive(dev, "drive", bs)) { 751 abort(); 752 } 753 qdev_prop_set_uint32(dev, "num-blocks", nb_blocs); 754 qdev_prop_set_uint64(dev, "sector-length", sector_len); 755 qdev_prop_set_uint8(dev, "width", width); 756 qdev_prop_set_uint8(dev, "big-endian", !!be); 757 qdev_prop_set_uint16(dev, "id0", id0); 758 qdev_prop_set_uint16(dev, "id1", id1); 759 qdev_prop_set_uint16(dev, "id2", id2); 760 qdev_prop_set_uint16(dev, "id3", id3); 761 qdev_prop_set_string(dev, "name", name); 762 qdev_init_nofail(dev); 763 764 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 765 return CFI_PFLASH01(dev); 766 } 767 768 MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl) 769 { 770 return &fl->mem; 771 } 772