1 /* 2 * Flash NAND memory emulation. Based on "16M x 8 Bit NAND Flash 3 * Memory" datasheet for the KM29U128AT / K9F2808U0A chips from 4 * Samsung Electronic. 5 * 6 * Copyright (c) 2006 Openedhand Ltd. 7 * Written by Andrzej Zaborowski <balrog@zabor.org> 8 * 9 * Support for additional features based on "MT29F2G16ABCWP 2Gx16" 10 * datasheet from Micron Technology and "NAND02G-B2C" datasheet 11 * from ST Microelectronics. 12 * 13 * This code is licensed under the GNU GPL v2. 14 * 15 * Contributions after 2012-01-13 are licensed under the terms of the 16 * GNU GPL, version 2 or (at your option) any later version. 17 */ 18 19 #ifndef NAND_IO 20 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/block/flash.h" 25 #include "sysemu/block-backend.h" 26 #include "migration/vmstate.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "qemu/module.h" 30 #include "qom/object.h" 31 32 # define NAND_CMD_READ0 0x00 33 # define NAND_CMD_READ1 0x01 34 # define NAND_CMD_READ2 0x50 35 # define NAND_CMD_LPREAD2 0x30 36 # define NAND_CMD_NOSERIALREAD2 0x35 37 # define NAND_CMD_RANDOMREAD1 0x05 38 # define NAND_CMD_RANDOMREAD2 0xe0 39 # define NAND_CMD_READID 0x90 40 # define NAND_CMD_RESET 0xff 41 # define NAND_CMD_PAGEPROGRAM1 0x80 42 # define NAND_CMD_PAGEPROGRAM2 0x10 43 # define NAND_CMD_CACHEPROGRAM2 0x15 44 # define NAND_CMD_BLOCKERASE1 0x60 45 # define NAND_CMD_BLOCKERASE2 0xd0 46 # define NAND_CMD_READSTATUS 0x70 47 # define NAND_CMD_COPYBACKPRG1 0x85 48 49 # define NAND_IOSTATUS_ERROR (1 << 0) 50 # define NAND_IOSTATUS_PLANE0 (1 << 1) 51 # define NAND_IOSTATUS_PLANE1 (1 << 2) 52 # define NAND_IOSTATUS_PLANE2 (1 << 3) 53 # define NAND_IOSTATUS_PLANE3 (1 << 4) 54 # define NAND_IOSTATUS_READY (1 << 6) 55 # define NAND_IOSTATUS_UNPROTCT (1 << 7) 56 57 # define MAX_PAGE 0x800 58 # define MAX_OOB 0x40 59 60 typedef struct NANDFlashState NANDFlashState; 61 struct NANDFlashState { 62 DeviceState parent_obj; 63 64 uint8_t manf_id, chip_id; 65 uint8_t buswidth; /* in BYTES */ 66 int size, pages; 67 int page_shift, oob_shift, erase_shift, addr_shift; 68 uint8_t *storage; 69 BlockBackend *blk; 70 int mem_oob; 71 72 uint8_t cle, ale, ce, wp, gnd; 73 74 uint8_t io[MAX_PAGE + MAX_OOB + 0x400]; 75 uint8_t *ioaddr; 76 int iolen; 77 78 uint32_t cmd; 79 uint64_t addr; 80 int addrlen; 81 int status; 82 int offset; 83 84 void (*blk_write)(NANDFlashState *s); 85 void (*blk_erase)(NANDFlashState *s); 86 void (*blk_load)(NANDFlashState *s, uint64_t addr, int offset); 87 88 uint32_t ioaddr_vmstate; 89 }; 90 91 #define TYPE_NAND "nand" 92 93 OBJECT_DECLARE_SIMPLE_TYPE(NANDFlashState, NAND) 94 95 static void mem_and(uint8_t *dest, const uint8_t *src, size_t n) 96 { 97 /* Like memcpy() but we logical-AND the data into the destination */ 98 int i; 99 for (i = 0; i < n; i++) { 100 dest[i] &= src[i]; 101 } 102 } 103 104 # define NAND_NO_AUTOINCR 0x00000001 105 # define NAND_BUSWIDTH_16 0x00000002 106 # define NAND_NO_PADDING 0x00000004 107 # define NAND_CACHEPRG 0x00000008 108 # define NAND_COPYBACK 0x00000010 109 # define NAND_IS_AND 0x00000020 110 # define NAND_4PAGE_ARRAY 0x00000040 111 # define NAND_NO_READRDY 0x00000100 112 # define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK) 113 114 # define NAND_IO 115 116 # define PAGE(addr) ((addr) >> ADDR_SHIFT) 117 # define PAGE_START(page) (PAGE(page) * (PAGE_SIZE + OOB_SIZE)) 118 # define PAGE_MASK ((1 << ADDR_SHIFT) - 1) 119 # define OOB_SHIFT (PAGE_SHIFT - 5) 120 # define OOB_SIZE (1 << OOB_SHIFT) 121 # define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT)) 122 # define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8)) 123 124 # define PAGE_SIZE 256 125 # define PAGE_SHIFT 8 126 # define PAGE_SECTORS 1 127 # define ADDR_SHIFT 8 128 # include "nand.c" 129 # define PAGE_SIZE 512 130 # define PAGE_SHIFT 9 131 # define PAGE_SECTORS 1 132 # define ADDR_SHIFT 8 133 # include "nand.c" 134 # define PAGE_SIZE 2048 135 # define PAGE_SHIFT 11 136 # define PAGE_SECTORS 4 137 # define ADDR_SHIFT 16 138 # include "nand.c" 139 140 /* Information based on Linux drivers/mtd/nand/raw/nand_ids.c */ 141 static const struct { 142 int size; 143 int width; 144 int page_shift; 145 int erase_shift; 146 uint32_t options; 147 } nand_flash_ids[0x100] = { 148 [0 ... 0xff] = { 0 }, 149 150 [0x6b] = { 4, 8, 9, 4, 0 }, 151 [0xe3] = { 4, 8, 9, 4, 0 }, 152 [0xe5] = { 4, 8, 9, 4, 0 }, 153 [0xd6] = { 8, 8, 9, 4, 0 }, 154 [0xe6] = { 8, 8, 9, 4, 0 }, 155 156 [0x33] = { 16, 8, 9, 5, 0 }, 157 [0x73] = { 16, 8, 9, 5, 0 }, 158 [0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 }, 159 [0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 }, 160 161 [0x35] = { 32, 8, 9, 5, 0 }, 162 [0x75] = { 32, 8, 9, 5, 0 }, 163 [0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 }, 164 [0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 }, 165 166 [0x36] = { 64, 8, 9, 5, 0 }, 167 [0x76] = { 64, 8, 9, 5, 0 }, 168 [0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 }, 169 [0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 }, 170 171 [0x78] = { 128, 8, 9, 5, 0 }, 172 [0x39] = { 128, 8, 9, 5, 0 }, 173 [0x79] = { 128, 8, 9, 5, 0 }, 174 [0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 }, 175 [0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 }, 176 [0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 }, 177 [0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 }, 178 179 [0x71] = { 256, 8, 9, 5, 0 }, 180 181 /* 182 * These are the new chips with large page size. The pagesize and the 183 * erasesize is determined from the extended id bytes 184 */ 185 # define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR) 186 # define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) 187 188 /* 512 Megabit */ 189 [0xa2] = { 64, 8, 0, 0, LP_OPTIONS }, 190 [0xf2] = { 64, 8, 0, 0, LP_OPTIONS }, 191 [0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 }, 192 [0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 }, 193 194 /* 1 Gigabit */ 195 [0xa1] = { 128, 8, 0, 0, LP_OPTIONS }, 196 [0xf1] = { 128, 8, 0, 0, LP_OPTIONS }, 197 [0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 }, 198 [0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 }, 199 200 /* 2 Gigabit */ 201 [0xaa] = { 256, 8, 0, 0, LP_OPTIONS }, 202 [0xda] = { 256, 8, 0, 0, LP_OPTIONS }, 203 [0xba] = { 256, 16, 0, 0, LP_OPTIONS16 }, 204 [0xca] = { 256, 16, 0, 0, LP_OPTIONS16 }, 205 206 /* 4 Gigabit */ 207 [0xac] = { 512, 8, 0, 0, LP_OPTIONS }, 208 [0xdc] = { 512, 8, 0, 0, LP_OPTIONS }, 209 [0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 }, 210 [0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 }, 211 212 /* 8 Gigabit */ 213 [0xa3] = { 1024, 8, 0, 0, LP_OPTIONS }, 214 [0xd3] = { 1024, 8, 0, 0, LP_OPTIONS }, 215 [0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 }, 216 [0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 }, 217 218 /* 16 Gigabit */ 219 [0xa5] = { 2048, 8, 0, 0, LP_OPTIONS }, 220 [0xd5] = { 2048, 8, 0, 0, LP_OPTIONS }, 221 [0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 }, 222 [0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 }, 223 }; 224 225 static void nand_reset(DeviceState *dev) 226 { 227 NANDFlashState *s = NAND(dev); 228 s->cmd = NAND_CMD_READ0; 229 s->addr = 0; 230 s->addrlen = 0; 231 s->iolen = 0; 232 s->offset = 0; 233 s->status &= NAND_IOSTATUS_UNPROTCT; 234 s->status |= NAND_IOSTATUS_READY; 235 } 236 237 static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value) 238 { 239 s->ioaddr[s->iolen++] = value; 240 for (value = s->buswidth; --value;) { 241 s->ioaddr[s->iolen++] = 0; 242 } 243 } 244 245 static void nand_command(NANDFlashState *s) 246 { 247 unsigned int offset; 248 switch (s->cmd) { 249 case NAND_CMD_READ0: 250 s->iolen = 0; 251 break; 252 253 case NAND_CMD_READID: 254 s->ioaddr = s->io; 255 s->iolen = 0; 256 nand_pushio_byte(s, s->manf_id); 257 nand_pushio_byte(s, s->chip_id); 258 nand_pushio_byte(s, 'Q'); /* Don't-care byte (often 0xa5) */ 259 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) { 260 /* Page Size, Block Size, Spare Size; bit 6 indicates 261 * 8 vs 16 bit width NAND. 262 */ 263 nand_pushio_byte(s, (s->buswidth == 2) ? 0x55 : 0x15); 264 } else { 265 nand_pushio_byte(s, 0xc0); /* Multi-plane */ 266 } 267 break; 268 269 case NAND_CMD_RANDOMREAD2: 270 case NAND_CMD_NOSERIALREAD2: 271 if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP)) 272 break; 273 offset = s->addr & ((1 << s->addr_shift) - 1); 274 s->blk_load(s, s->addr, offset); 275 if (s->gnd) 276 s->iolen = (1 << s->page_shift) - offset; 277 else 278 s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset; 279 break; 280 281 case NAND_CMD_RESET: 282 nand_reset(DEVICE(s)); 283 break; 284 285 case NAND_CMD_PAGEPROGRAM1: 286 s->ioaddr = s->io; 287 s->iolen = 0; 288 break; 289 290 case NAND_CMD_PAGEPROGRAM2: 291 if (s->wp) { 292 s->blk_write(s); 293 } 294 break; 295 296 case NAND_CMD_BLOCKERASE1: 297 break; 298 299 case NAND_CMD_BLOCKERASE2: 300 s->addr &= (1ull << s->addrlen * 8) - 1; 301 s->addr <<= nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP ? 302 16 : 8; 303 304 if (s->wp) { 305 s->blk_erase(s); 306 } 307 break; 308 309 case NAND_CMD_READSTATUS: 310 s->ioaddr = s->io; 311 s->iolen = 0; 312 nand_pushio_byte(s, s->status); 313 break; 314 315 default: 316 printf("%s: Unknown NAND command 0x%02x\n", __func__, s->cmd); 317 } 318 } 319 320 static int nand_pre_save(void *opaque) 321 { 322 NANDFlashState *s = NAND(opaque); 323 324 s->ioaddr_vmstate = s->ioaddr - s->io; 325 326 return 0; 327 } 328 329 static int nand_post_load(void *opaque, int version_id) 330 { 331 NANDFlashState *s = NAND(opaque); 332 333 if (s->ioaddr_vmstate > sizeof(s->io)) { 334 return -EINVAL; 335 } 336 s->ioaddr = s->io + s->ioaddr_vmstate; 337 338 return 0; 339 } 340 341 static const VMStateDescription vmstate_nand = { 342 .name = "nand", 343 .version_id = 1, 344 .minimum_version_id = 1, 345 .pre_save = nand_pre_save, 346 .post_load = nand_post_load, 347 .fields = (VMStateField[]) { 348 VMSTATE_UINT8(cle, NANDFlashState), 349 VMSTATE_UINT8(ale, NANDFlashState), 350 VMSTATE_UINT8(ce, NANDFlashState), 351 VMSTATE_UINT8(wp, NANDFlashState), 352 VMSTATE_UINT8(gnd, NANDFlashState), 353 VMSTATE_BUFFER(io, NANDFlashState), 354 VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState), 355 VMSTATE_INT32(iolen, NANDFlashState), 356 VMSTATE_UINT32(cmd, NANDFlashState), 357 VMSTATE_UINT64(addr, NANDFlashState), 358 VMSTATE_INT32(addrlen, NANDFlashState), 359 VMSTATE_INT32(status, NANDFlashState), 360 VMSTATE_INT32(offset, NANDFlashState), 361 /* XXX: do we want to save s->storage too? */ 362 VMSTATE_END_OF_LIST() 363 } 364 }; 365 366 static void nand_realize(DeviceState *dev, Error **errp) 367 { 368 int pagesize; 369 NANDFlashState *s = NAND(dev); 370 int ret; 371 372 373 s->buswidth = nand_flash_ids[s->chip_id].width >> 3; 374 s->size = nand_flash_ids[s->chip_id].size << 20; 375 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) { 376 s->page_shift = 11; 377 s->erase_shift = 6; 378 } else { 379 s->page_shift = nand_flash_ids[s->chip_id].page_shift; 380 s->erase_shift = nand_flash_ids[s->chip_id].erase_shift; 381 } 382 383 switch (1 << s->page_shift) { 384 case 256: 385 nand_init_256(s); 386 break; 387 case 512: 388 nand_init_512(s); 389 break; 390 case 2048: 391 nand_init_2048(s); 392 break; 393 default: 394 error_setg(errp, "Unsupported NAND block size %#x", 395 1 << s->page_shift); 396 return; 397 } 398 399 pagesize = 1 << s->oob_shift; 400 s->mem_oob = 1; 401 if (s->blk) { 402 if (blk_is_read_only(s->blk)) { 403 error_setg(errp, "Can't use a read-only drive"); 404 return; 405 } 406 ret = blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 407 BLK_PERM_ALL, errp); 408 if (ret < 0) { 409 return; 410 } 411 if (blk_getlength(s->blk) >= 412 (s->pages << s->page_shift) + (s->pages << s->oob_shift)) { 413 pagesize = 0; 414 s->mem_oob = 0; 415 } 416 } else { 417 pagesize += 1 << s->page_shift; 418 } 419 if (pagesize) { 420 s->storage = (uint8_t *) memset(g_malloc(s->pages * pagesize), 421 0xff, s->pages * pagesize); 422 } 423 /* Give s->ioaddr a sane value in case we save state before it is used. */ 424 s->ioaddr = s->io; 425 } 426 427 static Property nand_properties[] = { 428 DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0), 429 DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0), 430 DEFINE_PROP_DRIVE("drive", NANDFlashState, blk), 431 DEFINE_PROP_END_OF_LIST(), 432 }; 433 434 static void nand_class_init(ObjectClass *klass, void *data) 435 { 436 DeviceClass *dc = DEVICE_CLASS(klass); 437 438 dc->realize = nand_realize; 439 dc->reset = nand_reset; 440 dc->vmsd = &vmstate_nand; 441 device_class_set_props(dc, nand_properties); 442 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 443 } 444 445 static const TypeInfo nand_info = { 446 .name = TYPE_NAND, 447 .parent = TYPE_DEVICE, 448 .instance_size = sizeof(NANDFlashState), 449 .class_init = nand_class_init, 450 }; 451 452 static void nand_register_types(void) 453 { 454 type_register_static(&nand_info); 455 } 456 457 /* 458 * Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins. Chip 459 * outputs are R/B and eight I/O pins. 460 * 461 * CE, WP and R/B are active low. 462 */ 463 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, 464 uint8_t ce, uint8_t wp, uint8_t gnd) 465 { 466 NANDFlashState *s = NAND(dev); 467 468 s->cle = cle; 469 s->ale = ale; 470 s->ce = ce; 471 s->wp = wp; 472 s->gnd = gnd; 473 if (wp) { 474 s->status |= NAND_IOSTATUS_UNPROTCT; 475 } else { 476 s->status &= ~NAND_IOSTATUS_UNPROTCT; 477 } 478 } 479 480 void nand_getpins(DeviceState *dev, int *rb) 481 { 482 *rb = 1; 483 } 484 485 void nand_setio(DeviceState *dev, uint32_t value) 486 { 487 int i; 488 NANDFlashState *s = NAND(dev); 489 490 if (!s->ce && s->cle) { 491 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) { 492 if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2) 493 return; 494 if (value == NAND_CMD_RANDOMREAD1) { 495 s->addr &= ~((1 << s->addr_shift) - 1); 496 s->addrlen = 0; 497 return; 498 } 499 } 500 if (value == NAND_CMD_READ0) { 501 s->offset = 0; 502 } else if (value == NAND_CMD_READ1) { 503 s->offset = 0x100; 504 value = NAND_CMD_READ0; 505 } else if (value == NAND_CMD_READ2) { 506 s->offset = 1 << s->page_shift; 507 value = NAND_CMD_READ0; 508 } 509 510 s->cmd = value; 511 512 if (s->cmd == NAND_CMD_READSTATUS || 513 s->cmd == NAND_CMD_PAGEPROGRAM2 || 514 s->cmd == NAND_CMD_BLOCKERASE1 || 515 s->cmd == NAND_CMD_BLOCKERASE2 || 516 s->cmd == NAND_CMD_NOSERIALREAD2 || 517 s->cmd == NAND_CMD_RANDOMREAD2 || 518 s->cmd == NAND_CMD_RESET) { 519 nand_command(s); 520 } 521 522 if (s->cmd != NAND_CMD_RANDOMREAD2) { 523 s->addrlen = 0; 524 } 525 } 526 527 if (s->ale) { 528 unsigned int shift = s->addrlen * 8; 529 uint64_t mask = ~(0xffull << shift); 530 uint64_t v = (uint64_t)value << shift; 531 532 s->addr = (s->addr & mask) | v; 533 s->addrlen ++; 534 535 switch (s->addrlen) { 536 case 1: 537 if (s->cmd == NAND_CMD_READID) { 538 nand_command(s); 539 } 540 break; 541 case 2: /* fix cache address as a byte address */ 542 s->addr <<= (s->buswidth - 1); 543 break; 544 case 3: 545 if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) && 546 (s->cmd == NAND_CMD_READ0 || 547 s->cmd == NAND_CMD_PAGEPROGRAM1)) { 548 nand_command(s); 549 } 550 break; 551 case 4: 552 if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) && 553 nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */ 554 (s->cmd == NAND_CMD_READ0 || 555 s->cmd == NAND_CMD_PAGEPROGRAM1)) { 556 nand_command(s); 557 } 558 break; 559 case 5: 560 if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) && 561 nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */ 562 (s->cmd == NAND_CMD_READ0 || 563 s->cmd == NAND_CMD_PAGEPROGRAM1)) { 564 nand_command(s); 565 } 566 break; 567 default: 568 break; 569 } 570 } 571 572 if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) { 573 if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) { 574 for (i = s->buswidth; i--; value >>= 8) { 575 s->io[s->iolen ++] = (uint8_t) (value & 0xff); 576 } 577 } 578 } else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) { 579 if ((s->addr & ((1 << s->addr_shift) - 1)) < 580 (1 << s->page_shift) + (1 << s->oob_shift)) { 581 for (i = s->buswidth; i--; s->addr++, value >>= 8) { 582 s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] = 583 (uint8_t) (value & 0xff); 584 } 585 } 586 } 587 } 588 589 uint32_t nand_getio(DeviceState *dev) 590 { 591 int offset; 592 uint32_t x = 0; 593 NANDFlashState *s = NAND(dev); 594 595 /* Allow sequential reading */ 596 if (!s->iolen && s->cmd == NAND_CMD_READ0) { 597 offset = (int) (s->addr & ((1 << s->addr_shift) - 1)) + s->offset; 598 s->offset = 0; 599 600 s->blk_load(s, s->addr, offset); 601 if (s->gnd) 602 s->iolen = (1 << s->page_shift) - offset; 603 else 604 s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset; 605 } 606 607 if (s->ce || s->iolen <= 0) { 608 return 0; 609 } 610 611 for (offset = s->buswidth; offset--;) { 612 x |= s->ioaddr[offset] << (offset << 3); 613 } 614 /* after receiving READ STATUS command all subsequent reads will 615 * return the status register value until another command is issued 616 */ 617 if (s->cmd != NAND_CMD_READSTATUS) { 618 s->addr += s->buswidth; 619 s->ioaddr += s->buswidth; 620 s->iolen -= s->buswidth; 621 } 622 return x; 623 } 624 625 uint32_t nand_getbuswidth(DeviceState *dev) 626 { 627 NANDFlashState *s = (NANDFlashState *) dev; 628 return s->buswidth << 3; 629 } 630 631 DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id) 632 { 633 DeviceState *dev; 634 635 if (nand_flash_ids[chip_id].size == 0) { 636 hw_error("%s: Unsupported NAND chip ID.\n", __func__); 637 } 638 dev = qdev_new(TYPE_NAND); 639 qdev_prop_set_uint8(dev, "manufacturer_id", manf_id); 640 qdev_prop_set_uint8(dev, "chip_id", chip_id); 641 if (blk) { 642 qdev_prop_set_drive_err(dev, "drive", blk, &error_fatal); 643 } 644 645 qdev_realize(dev, NULL, &error_fatal); 646 return dev; 647 } 648 649 type_init(nand_register_types) 650 651 #else 652 653 /* Program a single page */ 654 static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s) 655 { 656 uint64_t off, page, sector, soff; 657 uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200]; 658 if (PAGE(s->addr) >= s->pages) 659 return; 660 661 if (!s->blk) { 662 mem_and(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) + 663 s->offset, s->io, s->iolen); 664 } else if (s->mem_oob) { 665 sector = SECTOR(s->addr); 666 off = (s->addr & PAGE_MASK) + s->offset; 667 soff = SECTOR_OFFSET(s->addr); 668 if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf, 669 PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) { 670 printf("%s: read error in sector %" PRIu64 "\n", __func__, sector); 671 return; 672 } 673 674 mem_and(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off)); 675 if (off + s->iolen > PAGE_SIZE) { 676 page = PAGE(s->addr); 677 mem_and(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off, 678 MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE)); 679 } 680 681 if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf, 682 PAGE_SECTORS << BDRV_SECTOR_BITS, 0) < 0) { 683 printf("%s: write error in sector %" PRIu64 "\n", __func__, sector); 684 } 685 } else { 686 off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset; 687 sector = off >> 9; 688 soff = off & 0x1ff; 689 if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf, 690 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) { 691 printf("%s: read error in sector %" PRIu64 "\n", __func__, sector); 692 return; 693 } 694 695 mem_and(iobuf + soff, s->io, s->iolen); 696 697 if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf, 698 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS, 0) < 0) { 699 printf("%s: write error in sector %" PRIu64 "\n", __func__, sector); 700 } 701 } 702 s->offset = 0; 703 } 704 705 /* Erase a single block */ 706 static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s) 707 { 708 uint64_t i, page, addr; 709 uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, }; 710 addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1); 711 712 if (PAGE(addr) >= s->pages) { 713 return; 714 } 715 716 if (!s->blk) { 717 memset(s->storage + PAGE_START(addr), 718 0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift); 719 } else if (s->mem_oob) { 720 memset(s->storage + (PAGE(addr) << OOB_SHIFT), 721 0xff, OOB_SIZE << s->erase_shift); 722 i = SECTOR(addr); 723 page = SECTOR(addr + (1 << (ADDR_SHIFT + s->erase_shift))); 724 for (; i < page; i ++) 725 if (blk_pwrite(s->blk, i << BDRV_SECTOR_BITS, iobuf, 726 BDRV_SECTOR_SIZE, 0) < 0) { 727 printf("%s: write error in sector %" PRIu64 "\n", __func__, i); 728 } 729 } else { 730 addr = PAGE_START(addr); 731 page = addr >> 9; 732 if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf, 733 BDRV_SECTOR_SIZE) < 0) { 734 printf("%s: read error in sector %" PRIu64 "\n", __func__, page); 735 } 736 memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1); 737 if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf, 738 BDRV_SECTOR_SIZE, 0) < 0) { 739 printf("%s: write error in sector %" PRIu64 "\n", __func__, page); 740 } 741 742 memset(iobuf, 0xff, 0x200); 743 i = (addr & ~0x1ff) + 0x200; 744 for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200; 745 i < addr; i += 0x200) { 746 if (blk_pwrite(s->blk, i, iobuf, BDRV_SECTOR_SIZE, 0) < 0) { 747 printf("%s: write error in sector %" PRIu64 "\n", 748 __func__, i >> 9); 749 } 750 } 751 752 page = i >> 9; 753 if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf, 754 BDRV_SECTOR_SIZE) < 0) { 755 printf("%s: read error in sector %" PRIu64 "\n", __func__, page); 756 } 757 memset(iobuf, 0xff, ((addr - 1) & 0x1ff) + 1); 758 if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf, 759 BDRV_SECTOR_SIZE, 0) < 0) { 760 printf("%s: write error in sector %" PRIu64 "\n", __func__, page); 761 } 762 } 763 } 764 765 static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s, 766 uint64_t addr, int offset) 767 { 768 if (PAGE(addr) >= s->pages) { 769 return; 770 } 771 772 if (s->blk) { 773 if (s->mem_oob) { 774 if (blk_pread(s->blk, SECTOR(addr) << BDRV_SECTOR_BITS, s->io, 775 PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) { 776 printf("%s: read error in sector %" PRIu64 "\n", 777 __func__, SECTOR(addr)); 778 } 779 memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE, 780 s->storage + (PAGE(s->addr) << OOB_SHIFT), 781 OOB_SIZE); 782 s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset; 783 } else { 784 if (blk_pread(s->blk, PAGE_START(addr), s->io, 785 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) { 786 printf("%s: read error in sector %" PRIu64 "\n", 787 __func__, PAGE_START(addr) >> 9); 788 } 789 s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset; 790 } 791 } else { 792 memcpy(s->io, s->storage + PAGE_START(s->addr) + 793 offset, PAGE_SIZE + OOB_SIZE - offset); 794 s->ioaddr = s->io; 795 } 796 } 797 798 static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s) 799 { 800 s->oob_shift = PAGE_SHIFT - 5; 801 s->pages = s->size >> PAGE_SHIFT; 802 s->addr_shift = ADDR_SHIFT; 803 804 s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE); 805 s->blk_write = glue(nand_blk_write_, PAGE_SIZE); 806 s->blk_load = glue(nand_blk_load_, PAGE_SIZE); 807 } 808 809 # undef PAGE_SIZE 810 # undef PAGE_SHIFT 811 # undef PAGE_SECTORS 812 # undef ADDR_SHIFT 813 #endif /* NAND_IO */ 814