1 /* 2 * Flash NAND memory emulation. Based on "16M x 8 Bit NAND Flash 3 * Memory" datasheet for the KM29U128AT / K9F2808U0A chips from 4 * Samsung Electronic. 5 * 6 * Copyright (c) 2006 Openedhand Ltd. 7 * Written by Andrzej Zaborowski <balrog@zabor.org> 8 * 9 * Support for additional features based on "MT29F2G16ABCWP 2Gx16" 10 * datasheet from Micron Technology and "NAND02G-B2C" datasheet 11 * from ST Microelectronics. 12 * 13 * This code is licensed under the GNU GPL v2. 14 * 15 * Contributions after 2012-01-13 are licensed under the terms of the 16 * GNU GPL, version 2 or (at your option) any later version. 17 */ 18 19 #ifndef NAND_IO 20 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/block/flash.h" 25 #include "sysemu/block-backend.h" 26 #include "migration/vmstate.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "qemu/module.h" 30 #include "qom/object.h" 31 32 # define NAND_CMD_READ0 0x00 33 # define NAND_CMD_READ1 0x01 34 # define NAND_CMD_READ2 0x50 35 # define NAND_CMD_LPREAD2 0x30 36 # define NAND_CMD_NOSERIALREAD2 0x35 37 # define NAND_CMD_RANDOMREAD1 0x05 38 # define NAND_CMD_RANDOMREAD2 0xe0 39 # define NAND_CMD_READID 0x90 40 # define NAND_CMD_RESET 0xff 41 # define NAND_CMD_PAGEPROGRAM1 0x80 42 # define NAND_CMD_PAGEPROGRAM2 0x10 43 # define NAND_CMD_CACHEPROGRAM2 0x15 44 # define NAND_CMD_BLOCKERASE1 0x60 45 # define NAND_CMD_BLOCKERASE2 0xd0 46 # define NAND_CMD_READSTATUS 0x70 47 # define NAND_CMD_COPYBACKPRG1 0x85 48 49 # define NAND_IOSTATUS_ERROR (1 << 0) 50 # define NAND_IOSTATUS_PLANE0 (1 << 1) 51 # define NAND_IOSTATUS_PLANE1 (1 << 2) 52 # define NAND_IOSTATUS_PLANE2 (1 << 3) 53 # define NAND_IOSTATUS_PLANE3 (1 << 4) 54 # define NAND_IOSTATUS_READY (1 << 6) 55 # define NAND_IOSTATUS_UNPROTCT (1 << 7) 56 57 # define MAX_PAGE 0x800 58 # define MAX_OOB 0x40 59 60 typedef struct NANDFlashState NANDFlashState; 61 struct NANDFlashState { 62 DeviceState parent_obj; 63 64 uint8_t manf_id, chip_id; 65 uint8_t buswidth; /* in BYTES */ 66 int size, pages; 67 int page_shift, oob_shift, erase_shift, addr_shift; 68 uint8_t *storage; 69 BlockBackend *blk; 70 int mem_oob; 71 72 uint8_t cle, ale, ce, wp, gnd; 73 74 uint8_t io[MAX_PAGE + MAX_OOB + 0x400]; 75 uint8_t *ioaddr; 76 int iolen; 77 78 uint32_t cmd; 79 uint64_t addr; 80 int addrlen; 81 int status; 82 int offset; 83 84 void (*blk_write)(NANDFlashState *s); 85 void (*blk_erase)(NANDFlashState *s); 86 void (*blk_load)(NANDFlashState *s, uint64_t addr, int offset); 87 88 uint32_t ioaddr_vmstate; 89 }; 90 91 #define TYPE_NAND "nand" 92 93 OBJECT_DECLARE_SIMPLE_TYPE(NANDFlashState, NAND) 94 95 static void mem_and(uint8_t *dest, const uint8_t *src, size_t n) 96 { 97 /* Like memcpy() but we logical-AND the data into the destination */ 98 int i; 99 for (i = 0; i < n; i++) { 100 dest[i] &= src[i]; 101 } 102 } 103 104 # define NAND_NO_AUTOINCR 0x00000001 105 # define NAND_BUSWIDTH_16 0x00000002 106 # define NAND_NO_PADDING 0x00000004 107 # define NAND_CACHEPRG 0x00000008 108 # define NAND_COPYBACK 0x00000010 109 # define NAND_IS_AND 0x00000020 110 # define NAND_4PAGE_ARRAY 0x00000040 111 # define NAND_NO_READRDY 0x00000100 112 # define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK) 113 114 # define NAND_IO 115 116 # define PAGE(addr) ((addr) >> ADDR_SHIFT) 117 # define PAGE_START(page) (PAGE(page) * (PAGE_SIZE + OOB_SIZE)) 118 # define PAGE_MASK ((1 << ADDR_SHIFT) - 1) 119 # define OOB_SHIFT (PAGE_SHIFT - 5) 120 # define OOB_SIZE (1 << OOB_SHIFT) 121 # define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT)) 122 # define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8)) 123 124 # define PAGE_SIZE 256 125 # define PAGE_SHIFT 8 126 # define PAGE_SECTORS 1 127 # define ADDR_SHIFT 8 128 # include "nand.c" 129 # define PAGE_SIZE 512 130 # define PAGE_SHIFT 9 131 # define PAGE_SECTORS 1 132 # define ADDR_SHIFT 8 133 # include "nand.c" 134 # define PAGE_SIZE 2048 135 # define PAGE_SHIFT 11 136 # define PAGE_SECTORS 4 137 # define ADDR_SHIFT 16 138 # include "nand.c" 139 140 /* Information based on Linux drivers/mtd/nand/nand_ids.c */ 141 static const struct { 142 int size; 143 int width; 144 int page_shift; 145 int erase_shift; 146 uint32_t options; 147 } nand_flash_ids[0x100] = { 148 [0 ... 0xff] = { 0 }, 149 150 [0x6e] = { 1, 8, 8, 4, 0 }, 151 [0x64] = { 2, 8, 8, 4, 0 }, 152 [0x6b] = { 4, 8, 9, 4, 0 }, 153 [0xe8] = { 1, 8, 8, 4, 0 }, 154 [0xec] = { 1, 8, 8, 4, 0 }, 155 [0xea] = { 2, 8, 8, 4, 0 }, 156 [0xd5] = { 4, 8, 9, 4, 0 }, 157 [0xe3] = { 4, 8, 9, 4, 0 }, 158 [0xe5] = { 4, 8, 9, 4, 0 }, 159 [0xd6] = { 8, 8, 9, 4, 0 }, 160 161 [0x39] = { 8, 8, 9, 4, 0 }, 162 [0xe6] = { 8, 8, 9, 4, 0 }, 163 [0x49] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 }, 164 [0x59] = { 8, 16, 9, 4, NAND_BUSWIDTH_16 }, 165 166 [0x33] = { 16, 8, 9, 5, 0 }, 167 [0x73] = { 16, 8, 9, 5, 0 }, 168 [0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 }, 169 [0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 }, 170 171 [0x35] = { 32, 8, 9, 5, 0 }, 172 [0x75] = { 32, 8, 9, 5, 0 }, 173 [0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 }, 174 [0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 }, 175 176 [0x36] = { 64, 8, 9, 5, 0 }, 177 [0x76] = { 64, 8, 9, 5, 0 }, 178 [0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 }, 179 [0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 }, 180 181 [0x78] = { 128, 8, 9, 5, 0 }, 182 [0x39] = { 128, 8, 9, 5, 0 }, 183 [0x79] = { 128, 8, 9, 5, 0 }, 184 [0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 }, 185 [0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 }, 186 [0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 }, 187 [0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 }, 188 189 [0x71] = { 256, 8, 9, 5, 0 }, 190 191 /* 192 * These are the new chips with large page size. The pagesize and the 193 * erasesize is determined from the extended id bytes 194 */ 195 # define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR) 196 # define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) 197 198 /* 512 Megabit */ 199 [0xa2] = { 64, 8, 0, 0, LP_OPTIONS }, 200 [0xf2] = { 64, 8, 0, 0, LP_OPTIONS }, 201 [0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 }, 202 [0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 }, 203 204 /* 1 Gigabit */ 205 [0xa1] = { 128, 8, 0, 0, LP_OPTIONS }, 206 [0xf1] = { 128, 8, 0, 0, LP_OPTIONS }, 207 [0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 }, 208 [0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 }, 209 210 /* 2 Gigabit */ 211 [0xaa] = { 256, 8, 0, 0, LP_OPTIONS }, 212 [0xda] = { 256, 8, 0, 0, LP_OPTIONS }, 213 [0xba] = { 256, 16, 0, 0, LP_OPTIONS16 }, 214 [0xca] = { 256, 16, 0, 0, LP_OPTIONS16 }, 215 216 /* 4 Gigabit */ 217 [0xac] = { 512, 8, 0, 0, LP_OPTIONS }, 218 [0xdc] = { 512, 8, 0, 0, LP_OPTIONS }, 219 [0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 }, 220 [0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 }, 221 222 /* 8 Gigabit */ 223 [0xa3] = { 1024, 8, 0, 0, LP_OPTIONS }, 224 [0xd3] = { 1024, 8, 0, 0, LP_OPTIONS }, 225 [0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 }, 226 [0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 }, 227 228 /* 16 Gigabit */ 229 [0xa5] = { 2048, 8, 0, 0, LP_OPTIONS }, 230 [0xd5] = { 2048, 8, 0, 0, LP_OPTIONS }, 231 [0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 }, 232 [0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 }, 233 }; 234 235 static void nand_reset(DeviceState *dev) 236 { 237 NANDFlashState *s = NAND(dev); 238 s->cmd = NAND_CMD_READ0; 239 s->addr = 0; 240 s->addrlen = 0; 241 s->iolen = 0; 242 s->offset = 0; 243 s->status &= NAND_IOSTATUS_UNPROTCT; 244 s->status |= NAND_IOSTATUS_READY; 245 } 246 247 static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value) 248 { 249 s->ioaddr[s->iolen++] = value; 250 for (value = s->buswidth; --value;) { 251 s->ioaddr[s->iolen++] = 0; 252 } 253 } 254 255 static void nand_command(NANDFlashState *s) 256 { 257 unsigned int offset; 258 switch (s->cmd) { 259 case NAND_CMD_READ0: 260 s->iolen = 0; 261 break; 262 263 case NAND_CMD_READID: 264 s->ioaddr = s->io; 265 s->iolen = 0; 266 nand_pushio_byte(s, s->manf_id); 267 nand_pushio_byte(s, s->chip_id); 268 nand_pushio_byte(s, 'Q'); /* Don't-care byte (often 0xa5) */ 269 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) { 270 /* Page Size, Block Size, Spare Size; bit 6 indicates 271 * 8 vs 16 bit width NAND. 272 */ 273 nand_pushio_byte(s, (s->buswidth == 2) ? 0x55 : 0x15); 274 } else { 275 nand_pushio_byte(s, 0xc0); /* Multi-plane */ 276 } 277 break; 278 279 case NAND_CMD_RANDOMREAD2: 280 case NAND_CMD_NOSERIALREAD2: 281 if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP)) 282 break; 283 offset = s->addr & ((1 << s->addr_shift) - 1); 284 s->blk_load(s, s->addr, offset); 285 if (s->gnd) 286 s->iolen = (1 << s->page_shift) - offset; 287 else 288 s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset; 289 break; 290 291 case NAND_CMD_RESET: 292 nand_reset(DEVICE(s)); 293 break; 294 295 case NAND_CMD_PAGEPROGRAM1: 296 s->ioaddr = s->io; 297 s->iolen = 0; 298 break; 299 300 case NAND_CMD_PAGEPROGRAM2: 301 if (s->wp) { 302 s->blk_write(s); 303 } 304 break; 305 306 case NAND_CMD_BLOCKERASE1: 307 break; 308 309 case NAND_CMD_BLOCKERASE2: 310 s->addr &= (1ull << s->addrlen * 8) - 1; 311 s->addr <<= nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP ? 312 16 : 8; 313 314 if (s->wp) { 315 s->blk_erase(s); 316 } 317 break; 318 319 case NAND_CMD_READSTATUS: 320 s->ioaddr = s->io; 321 s->iolen = 0; 322 nand_pushio_byte(s, s->status); 323 break; 324 325 default: 326 printf("%s: Unknown NAND command 0x%02x\n", __func__, s->cmd); 327 } 328 } 329 330 static int nand_pre_save(void *opaque) 331 { 332 NANDFlashState *s = NAND(opaque); 333 334 s->ioaddr_vmstate = s->ioaddr - s->io; 335 336 return 0; 337 } 338 339 static int nand_post_load(void *opaque, int version_id) 340 { 341 NANDFlashState *s = NAND(opaque); 342 343 if (s->ioaddr_vmstate > sizeof(s->io)) { 344 return -EINVAL; 345 } 346 s->ioaddr = s->io + s->ioaddr_vmstate; 347 348 return 0; 349 } 350 351 static const VMStateDescription vmstate_nand = { 352 .name = "nand", 353 .version_id = 1, 354 .minimum_version_id = 1, 355 .pre_save = nand_pre_save, 356 .post_load = nand_post_load, 357 .fields = (VMStateField[]) { 358 VMSTATE_UINT8(cle, NANDFlashState), 359 VMSTATE_UINT8(ale, NANDFlashState), 360 VMSTATE_UINT8(ce, NANDFlashState), 361 VMSTATE_UINT8(wp, NANDFlashState), 362 VMSTATE_UINT8(gnd, NANDFlashState), 363 VMSTATE_BUFFER(io, NANDFlashState), 364 VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState), 365 VMSTATE_INT32(iolen, NANDFlashState), 366 VMSTATE_UINT32(cmd, NANDFlashState), 367 VMSTATE_UINT64(addr, NANDFlashState), 368 VMSTATE_INT32(addrlen, NANDFlashState), 369 VMSTATE_INT32(status, NANDFlashState), 370 VMSTATE_INT32(offset, NANDFlashState), 371 /* XXX: do we want to save s->storage too? */ 372 VMSTATE_END_OF_LIST() 373 } 374 }; 375 376 static void nand_realize(DeviceState *dev, Error **errp) 377 { 378 int pagesize; 379 NANDFlashState *s = NAND(dev); 380 int ret; 381 382 383 s->buswidth = nand_flash_ids[s->chip_id].width >> 3; 384 s->size = nand_flash_ids[s->chip_id].size << 20; 385 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) { 386 s->page_shift = 11; 387 s->erase_shift = 6; 388 } else { 389 s->page_shift = nand_flash_ids[s->chip_id].page_shift; 390 s->erase_shift = nand_flash_ids[s->chip_id].erase_shift; 391 } 392 393 switch (1 << s->page_shift) { 394 case 256: 395 nand_init_256(s); 396 break; 397 case 512: 398 nand_init_512(s); 399 break; 400 case 2048: 401 nand_init_2048(s); 402 break; 403 default: 404 error_setg(errp, "Unsupported NAND block size %#x", 405 1 << s->page_shift); 406 return; 407 } 408 409 pagesize = 1 << s->oob_shift; 410 s->mem_oob = 1; 411 if (s->blk) { 412 if (blk_is_read_only(s->blk)) { 413 error_setg(errp, "Can't use a read-only drive"); 414 return; 415 } 416 ret = blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 417 BLK_PERM_ALL, errp); 418 if (ret < 0) { 419 return; 420 } 421 if (blk_getlength(s->blk) >= 422 (s->pages << s->page_shift) + (s->pages << s->oob_shift)) { 423 pagesize = 0; 424 s->mem_oob = 0; 425 } 426 } else { 427 pagesize += 1 << s->page_shift; 428 } 429 if (pagesize) { 430 s->storage = (uint8_t *) memset(g_malloc(s->pages * pagesize), 431 0xff, s->pages * pagesize); 432 } 433 /* Give s->ioaddr a sane value in case we save state before it is used. */ 434 s->ioaddr = s->io; 435 } 436 437 static Property nand_properties[] = { 438 DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0), 439 DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0), 440 DEFINE_PROP_DRIVE("drive", NANDFlashState, blk), 441 DEFINE_PROP_END_OF_LIST(), 442 }; 443 444 static void nand_class_init(ObjectClass *klass, void *data) 445 { 446 DeviceClass *dc = DEVICE_CLASS(klass); 447 448 dc->realize = nand_realize; 449 dc->reset = nand_reset; 450 dc->vmsd = &vmstate_nand; 451 device_class_set_props(dc, nand_properties); 452 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 453 } 454 455 static const TypeInfo nand_info = { 456 .name = TYPE_NAND, 457 .parent = TYPE_DEVICE, 458 .instance_size = sizeof(NANDFlashState), 459 .class_init = nand_class_init, 460 }; 461 462 static void nand_register_types(void) 463 { 464 type_register_static(&nand_info); 465 } 466 467 /* 468 * Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins. Chip 469 * outputs are R/B and eight I/O pins. 470 * 471 * CE, WP and R/B are active low. 472 */ 473 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, 474 uint8_t ce, uint8_t wp, uint8_t gnd) 475 { 476 NANDFlashState *s = NAND(dev); 477 478 s->cle = cle; 479 s->ale = ale; 480 s->ce = ce; 481 s->wp = wp; 482 s->gnd = gnd; 483 if (wp) { 484 s->status |= NAND_IOSTATUS_UNPROTCT; 485 } else { 486 s->status &= ~NAND_IOSTATUS_UNPROTCT; 487 } 488 } 489 490 void nand_getpins(DeviceState *dev, int *rb) 491 { 492 *rb = 1; 493 } 494 495 void nand_setio(DeviceState *dev, uint32_t value) 496 { 497 int i; 498 NANDFlashState *s = NAND(dev); 499 500 if (!s->ce && s->cle) { 501 if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) { 502 if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2) 503 return; 504 if (value == NAND_CMD_RANDOMREAD1) { 505 s->addr &= ~((1 << s->addr_shift) - 1); 506 s->addrlen = 0; 507 return; 508 } 509 } 510 if (value == NAND_CMD_READ0) { 511 s->offset = 0; 512 } else if (value == NAND_CMD_READ1) { 513 s->offset = 0x100; 514 value = NAND_CMD_READ0; 515 } else if (value == NAND_CMD_READ2) { 516 s->offset = 1 << s->page_shift; 517 value = NAND_CMD_READ0; 518 } 519 520 s->cmd = value; 521 522 if (s->cmd == NAND_CMD_READSTATUS || 523 s->cmd == NAND_CMD_PAGEPROGRAM2 || 524 s->cmd == NAND_CMD_BLOCKERASE1 || 525 s->cmd == NAND_CMD_BLOCKERASE2 || 526 s->cmd == NAND_CMD_NOSERIALREAD2 || 527 s->cmd == NAND_CMD_RANDOMREAD2 || 528 s->cmd == NAND_CMD_RESET) { 529 nand_command(s); 530 } 531 532 if (s->cmd != NAND_CMD_RANDOMREAD2) { 533 s->addrlen = 0; 534 } 535 } 536 537 if (s->ale) { 538 unsigned int shift = s->addrlen * 8; 539 uint64_t mask = ~(0xffull << shift); 540 uint64_t v = (uint64_t)value << shift; 541 542 s->addr = (s->addr & mask) | v; 543 s->addrlen ++; 544 545 switch (s->addrlen) { 546 case 1: 547 if (s->cmd == NAND_CMD_READID) { 548 nand_command(s); 549 } 550 break; 551 case 2: /* fix cache address as a byte address */ 552 s->addr <<= (s->buswidth - 1); 553 break; 554 case 3: 555 if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) && 556 (s->cmd == NAND_CMD_READ0 || 557 s->cmd == NAND_CMD_PAGEPROGRAM1)) { 558 nand_command(s); 559 } 560 break; 561 case 4: 562 if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) && 563 nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */ 564 (s->cmd == NAND_CMD_READ0 || 565 s->cmd == NAND_CMD_PAGEPROGRAM1)) { 566 nand_command(s); 567 } 568 break; 569 case 5: 570 if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) && 571 nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */ 572 (s->cmd == NAND_CMD_READ0 || 573 s->cmd == NAND_CMD_PAGEPROGRAM1)) { 574 nand_command(s); 575 } 576 break; 577 default: 578 break; 579 } 580 } 581 582 if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) { 583 if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) { 584 for (i = s->buswidth; i--; value >>= 8) { 585 s->io[s->iolen ++] = (uint8_t) (value & 0xff); 586 } 587 } 588 } else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) { 589 if ((s->addr & ((1 << s->addr_shift) - 1)) < 590 (1 << s->page_shift) + (1 << s->oob_shift)) { 591 for (i = s->buswidth; i--; s->addr++, value >>= 8) { 592 s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] = 593 (uint8_t) (value & 0xff); 594 } 595 } 596 } 597 } 598 599 uint32_t nand_getio(DeviceState *dev) 600 { 601 int offset; 602 uint32_t x = 0; 603 NANDFlashState *s = NAND(dev); 604 605 /* Allow sequential reading */ 606 if (!s->iolen && s->cmd == NAND_CMD_READ0) { 607 offset = (int) (s->addr & ((1 << s->addr_shift) - 1)) + s->offset; 608 s->offset = 0; 609 610 s->blk_load(s, s->addr, offset); 611 if (s->gnd) 612 s->iolen = (1 << s->page_shift) - offset; 613 else 614 s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset; 615 } 616 617 if (s->ce || s->iolen <= 0) { 618 return 0; 619 } 620 621 for (offset = s->buswidth; offset--;) { 622 x |= s->ioaddr[offset] << (offset << 3); 623 } 624 /* after receiving READ STATUS command all subsequent reads will 625 * return the status register value until another command is issued 626 */ 627 if (s->cmd != NAND_CMD_READSTATUS) { 628 s->addr += s->buswidth; 629 s->ioaddr += s->buswidth; 630 s->iolen -= s->buswidth; 631 } 632 return x; 633 } 634 635 uint32_t nand_getbuswidth(DeviceState *dev) 636 { 637 NANDFlashState *s = (NANDFlashState *) dev; 638 return s->buswidth << 3; 639 } 640 641 DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id) 642 { 643 DeviceState *dev; 644 645 if (nand_flash_ids[chip_id].size == 0) { 646 hw_error("%s: Unsupported NAND chip ID.\n", __func__); 647 } 648 dev = qdev_new(TYPE_NAND); 649 qdev_prop_set_uint8(dev, "manufacturer_id", manf_id); 650 qdev_prop_set_uint8(dev, "chip_id", chip_id); 651 if (blk) { 652 qdev_prop_set_drive_err(dev, "drive", blk, &error_fatal); 653 } 654 655 qdev_realize(dev, NULL, &error_fatal); 656 return dev; 657 } 658 659 type_init(nand_register_types) 660 661 #else 662 663 /* Program a single page */ 664 static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s) 665 { 666 uint64_t off, page, sector, soff; 667 uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200]; 668 if (PAGE(s->addr) >= s->pages) 669 return; 670 671 if (!s->blk) { 672 mem_and(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) + 673 s->offset, s->io, s->iolen); 674 } else if (s->mem_oob) { 675 sector = SECTOR(s->addr); 676 off = (s->addr & PAGE_MASK) + s->offset; 677 soff = SECTOR_OFFSET(s->addr); 678 if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf, 679 PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) { 680 printf("%s: read error in sector %" PRIu64 "\n", __func__, sector); 681 return; 682 } 683 684 mem_and(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off)); 685 if (off + s->iolen > PAGE_SIZE) { 686 page = PAGE(s->addr); 687 mem_and(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off, 688 MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE)); 689 } 690 691 if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf, 692 PAGE_SECTORS << BDRV_SECTOR_BITS, 0) < 0) { 693 printf("%s: write error in sector %" PRIu64 "\n", __func__, sector); 694 } 695 } else { 696 off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset; 697 sector = off >> 9; 698 soff = off & 0x1ff; 699 if (blk_pread(s->blk, sector << BDRV_SECTOR_BITS, iobuf, 700 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) { 701 printf("%s: read error in sector %" PRIu64 "\n", __func__, sector); 702 return; 703 } 704 705 mem_and(iobuf + soff, s->io, s->iolen); 706 707 if (blk_pwrite(s->blk, sector << BDRV_SECTOR_BITS, iobuf, 708 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS, 0) < 0) { 709 printf("%s: write error in sector %" PRIu64 "\n", __func__, sector); 710 } 711 } 712 s->offset = 0; 713 } 714 715 /* Erase a single block */ 716 static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s) 717 { 718 uint64_t i, page, addr; 719 uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, }; 720 addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1); 721 722 if (PAGE(addr) >= s->pages) { 723 return; 724 } 725 726 if (!s->blk) { 727 memset(s->storage + PAGE_START(addr), 728 0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift); 729 } else if (s->mem_oob) { 730 memset(s->storage + (PAGE(addr) << OOB_SHIFT), 731 0xff, OOB_SIZE << s->erase_shift); 732 i = SECTOR(addr); 733 page = SECTOR(addr + (1 << (ADDR_SHIFT + s->erase_shift))); 734 for (; i < page; i ++) 735 if (blk_pwrite(s->blk, i << BDRV_SECTOR_BITS, iobuf, 736 BDRV_SECTOR_SIZE, 0) < 0) { 737 printf("%s: write error in sector %" PRIu64 "\n", __func__, i); 738 } 739 } else { 740 addr = PAGE_START(addr); 741 page = addr >> 9; 742 if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf, 743 BDRV_SECTOR_SIZE) < 0) { 744 printf("%s: read error in sector %" PRIu64 "\n", __func__, page); 745 } 746 memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1); 747 if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf, 748 BDRV_SECTOR_SIZE, 0) < 0) { 749 printf("%s: write error in sector %" PRIu64 "\n", __func__, page); 750 } 751 752 memset(iobuf, 0xff, 0x200); 753 i = (addr & ~0x1ff) + 0x200; 754 for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200; 755 i < addr; i += 0x200) { 756 if (blk_pwrite(s->blk, i, iobuf, BDRV_SECTOR_SIZE, 0) < 0) { 757 printf("%s: write error in sector %" PRIu64 "\n", 758 __func__, i >> 9); 759 } 760 } 761 762 page = i >> 9; 763 if (blk_pread(s->blk, page << BDRV_SECTOR_BITS, iobuf, 764 BDRV_SECTOR_SIZE) < 0) { 765 printf("%s: read error in sector %" PRIu64 "\n", __func__, page); 766 } 767 memset(iobuf, 0xff, ((addr - 1) & 0x1ff) + 1); 768 if (blk_pwrite(s->blk, page << BDRV_SECTOR_BITS, iobuf, 769 BDRV_SECTOR_SIZE, 0) < 0) { 770 printf("%s: write error in sector %" PRIu64 "\n", __func__, page); 771 } 772 } 773 } 774 775 static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s, 776 uint64_t addr, int offset) 777 { 778 if (PAGE(addr) >= s->pages) { 779 return; 780 } 781 782 if (s->blk) { 783 if (s->mem_oob) { 784 if (blk_pread(s->blk, SECTOR(addr) << BDRV_SECTOR_BITS, s->io, 785 PAGE_SECTORS << BDRV_SECTOR_BITS) < 0) { 786 printf("%s: read error in sector %" PRIu64 "\n", 787 __func__, SECTOR(addr)); 788 } 789 memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE, 790 s->storage + (PAGE(s->addr) << OOB_SHIFT), 791 OOB_SIZE); 792 s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset; 793 } else { 794 if (blk_pread(s->blk, PAGE_START(addr), s->io, 795 (PAGE_SECTORS + 2) << BDRV_SECTOR_BITS) < 0) { 796 printf("%s: read error in sector %" PRIu64 "\n", 797 __func__, PAGE_START(addr) >> 9); 798 } 799 s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset; 800 } 801 } else { 802 memcpy(s->io, s->storage + PAGE_START(s->addr) + 803 offset, PAGE_SIZE + OOB_SIZE - offset); 804 s->ioaddr = s->io; 805 } 806 } 807 808 static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s) 809 { 810 s->oob_shift = PAGE_SHIFT - 5; 811 s->pages = s->size >> PAGE_SHIFT; 812 s->addr_shift = ADDR_SHIFT; 813 814 s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE); 815 s->blk_write = glue(nand_blk_write_, PAGE_SIZE); 816 s->blk_load = glue(nand_blk_load_, PAGE_SIZE); 817 } 818 819 # undef PAGE_SIZE 820 # undef PAGE_SHIFT 821 # undef PAGE_SECTORS 822 # undef ADDR_SHIFT 823 #endif /* NAND_IO */ 824