1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/blockdev.h" 28 #include "hw/ssi/ssi.h" 29 #include "qemu/bitops.h" 30 #include "qemu/log.h" 31 #include "qapi/error.h" 32 33 #ifndef M25P80_ERR_DEBUG 34 #define M25P80_ERR_DEBUG 0 35 #endif 36 37 #define DB_PRINT_L(level, ...) do { \ 38 if (M25P80_ERR_DEBUG > (level)) { \ 39 fprintf(stderr, ": %s: ", __func__); \ 40 fprintf(stderr, ## __VA_ARGS__); \ 41 } \ 42 } while (0); 43 44 /* Fields for FlashPartInfo->flags */ 45 46 /* erase capabilities */ 47 #define ER_4K 1 48 #define ER_32K 2 49 /* set to allow the page program command to write 0s back to 1. Useful for 50 * modelling EEPROM with SPI flash command set 51 */ 52 #define EEPROM 0x100 53 54 /* 16 MiB max in 3 byte address mode */ 55 #define MAX_3BYTES_SIZE 0x1000000 56 57 #define SPI_NOR_MAX_ID_LEN 6 58 59 typedef struct FlashPartInfo { 60 const char *part_name; 61 /* 62 * This array stores the ID bytes. 63 * The first three bytes are the JEDIC ID. 64 * JEDEC ID zero means "no ID" (mostly older chips). 65 */ 66 uint8_t id[SPI_NOR_MAX_ID_LEN]; 67 uint8_t id_len; 68 /* there is confusion between manufacturers as to what a sector is. In this 69 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 70 * command (opcode 0xd8). 71 */ 72 uint32_t sector_size; 73 uint32_t n_sectors; 74 uint32_t page_size; 75 uint16_t flags; 76 } FlashPartInfo; 77 78 /* adapted from linux */ 79 /* Used when the "_ext_id" is two bytes at most */ 80 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 81 .part_name = _part_name,\ 82 .id = {\ 83 ((_jedec_id) >> 16) & 0xff,\ 84 ((_jedec_id) >> 8) & 0xff,\ 85 (_jedec_id) & 0xff,\ 86 ((_ext_id) >> 8) & 0xff,\ 87 (_ext_id) & 0xff,\ 88 },\ 89 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 90 .sector_size = (_sector_size),\ 91 .n_sectors = (_n_sectors),\ 92 .page_size = 256,\ 93 .flags = (_flags), 94 95 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 96 .part_name = _part_name,\ 97 .id = {\ 98 ((_jedec_id) >> 16) & 0xff,\ 99 ((_jedec_id) >> 8) & 0xff,\ 100 (_jedec_id) & 0xff,\ 101 ((_ext_id) >> 16) & 0xff,\ 102 ((_ext_id) >> 8) & 0xff,\ 103 (_ext_id) & 0xff,\ 104 },\ 105 .id_len = 6,\ 106 .sector_size = (_sector_size),\ 107 .n_sectors = (_n_sectors),\ 108 .page_size = 256,\ 109 .flags = (_flags),\ 110 111 #define JEDEC_NUMONYX 0x20 112 #define JEDEC_WINBOND 0xEF 113 #define JEDEC_SPANSION 0x01 114 115 /* Numonyx (Micron) Configuration register macros */ 116 #define VCFG_DUMMY 0x1 117 #define VCFG_WRAP_SEQUENTIAL 0x2 118 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 119 #define NVCFG_XIP_MODE_MASK (7 << 9) 120 #define VCFG_XIP_MODE_ENABLED (1 << 3) 121 #define CFG_DUMMY_CLK_LEN 4 122 #define NVCFG_DUMMY_CLK_POS 12 123 #define VCFG_DUMMY_CLK_POS 4 124 #define EVCFG_OUT_DRIVER_STRENGHT_DEF 7 125 #define EVCFG_VPP_ACCELERATOR (1 << 3) 126 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 127 #define NVCFG_DUAL_IO_MASK (1 << 2) 128 #define EVCFG_DUAL_IO_ENABLED (1 << 6) 129 #define NVCFG_QUAD_IO_MASK (1 << 3) 130 #define EVCFG_QUAD_IO_ENABLED (1 << 7) 131 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 132 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 133 134 /* Numonyx (Micron) Flag Status Register macros */ 135 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 136 #define FSR_FLASH_READY (1 << 7) 137 138 /* Spansion configuration registers macros. */ 139 #define SPANSION_QUAD_CFG_POS 0 140 #define SPANSION_QUAD_CFG_LEN 1 141 #define SPANSION_DUMMY_CLK_POS 0 142 #define SPANSION_DUMMY_CLK_LEN 4 143 #define SPANSION_ADDR_LEN_POS 7 144 #define SPANSION_ADDR_LEN_LEN 1 145 146 /* 147 * Spansion read mode command length in bytes, 148 * the mode is currently not supported. 149 */ 150 151 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 152 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 153 154 static const FlashPartInfo known_devices[] = { 155 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 156 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 157 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 158 159 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 160 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 161 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 162 163 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 164 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 165 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 166 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 167 168 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 169 170 /* Atmel EEPROMS - it is assumed, that don't care bit in command 171 * is set to 0. Block protection is not supported. 172 */ 173 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 174 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 175 176 /* EON -- en25xxx */ 177 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 178 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 179 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 180 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 181 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 182 183 /* GigaDevice */ 184 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 185 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 186 187 /* Intel/Numonyx -- xxxs33b */ 188 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 189 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 190 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 191 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 192 193 /* Macronix */ 194 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 195 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 196 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 197 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 198 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 199 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 200 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 201 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 202 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) }, 203 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 204 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 205 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 206 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 207 208 /* Micron */ 209 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 210 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 211 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 212 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 213 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 214 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 215 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 216 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 217 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 218 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 219 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 220 { INFO("mt25ql01g", 0x20ba21, 0, 64 << 10, 2048, ER_4K) }, 221 { INFO("mt25qu01g", 0x20bb21, 0, 64 << 10, 2048, ER_4K) }, 222 223 /* Spansion -- single (large) sector size only, at least 224 * for the chips listed here (without boot sectors). 225 */ 226 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 227 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 228 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 229 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 230 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 231 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 232 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 233 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 234 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 235 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 236 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 237 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 238 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 239 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 240 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 241 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 242 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 243 244 /* Spansion -- boot sectors support */ 245 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 246 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 247 248 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 249 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 250 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 251 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 252 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 253 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 254 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 255 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 256 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 257 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 258 259 /* ST Microelectronics -- newer production may have feature updates */ 260 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 261 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 262 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 263 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 264 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 265 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 266 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 267 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 268 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 269 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 270 271 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 272 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 273 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 274 275 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 276 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 277 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 278 279 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 280 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 281 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 282 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 283 284 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 285 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 286 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 287 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 288 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 289 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 290 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 291 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 292 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 293 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 294 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 295 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 296 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 297 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, 298 }; 299 300 typedef enum { 301 NOP = 0, 302 WRSR = 0x1, 303 WRDI = 0x4, 304 RDSR = 0x5, 305 WREN = 0x6, 306 JEDEC_READ = 0x9f, 307 BULK_ERASE = 0xc7, 308 READ_FSR = 0x70, 309 RDCR = 0x15, 310 311 READ = 0x03, 312 READ4 = 0x13, 313 FAST_READ = 0x0b, 314 FAST_READ4 = 0x0c, 315 DOR = 0x3b, 316 DOR4 = 0x3c, 317 QOR = 0x6b, 318 QOR4 = 0x6c, 319 DIOR = 0xbb, 320 DIOR4 = 0xbc, 321 QIOR = 0xeb, 322 QIOR4 = 0xec, 323 324 PP = 0x02, 325 PP4 = 0x12, 326 PP4_4 = 0x3e, 327 DPP = 0xa2, 328 QPP = 0x32, 329 330 ERASE_4K = 0x20, 331 ERASE4_4K = 0x21, 332 ERASE_32K = 0x52, 333 ERASE4_32K = 0x5c, 334 ERASE_SECTOR = 0xd8, 335 ERASE4_SECTOR = 0xdc, 336 337 EN_4BYTE_ADDR = 0xB7, 338 EX_4BYTE_ADDR = 0xE9, 339 340 EXTEND_ADDR_READ = 0xC8, 341 EXTEND_ADDR_WRITE = 0xC5, 342 343 RESET_ENABLE = 0x66, 344 RESET_MEMORY = 0x99, 345 346 /* 347 * Micron: 0x35 - enable QPI 348 * Spansion: 0x35 - read control register 349 */ 350 RDCR_EQIO = 0x35, 351 RSTQIO = 0xf5, 352 353 RNVCR = 0xB5, 354 WNVCR = 0xB1, 355 356 RVCR = 0x85, 357 WVCR = 0x81, 358 359 REVCR = 0x65, 360 WEVCR = 0x61, 361 } FlashCMD; 362 363 typedef enum { 364 STATE_IDLE, 365 STATE_PAGE_PROGRAM, 366 STATE_READ, 367 STATE_COLLECTING_DATA, 368 STATE_COLLECTING_VAR_LEN_DATA, 369 STATE_READING_DATA, 370 } CMDState; 371 372 typedef enum { 373 MAN_SPANSION, 374 MAN_MACRONIX, 375 MAN_NUMONYX, 376 MAN_WINBOND, 377 MAN_GENERIC, 378 } Manufacturer; 379 380 typedef struct Flash { 381 SSISlave parent_obj; 382 383 BlockBackend *blk; 384 385 uint8_t *storage; 386 uint32_t size; 387 int page_size; 388 389 uint8_t state; 390 uint8_t data[16]; 391 uint32_t len; 392 uint32_t pos; 393 uint8_t needed_bytes; 394 uint8_t cmd_in_progress; 395 uint32_t cur_addr; 396 uint32_t nonvolatile_cfg; 397 /* Configuration register for Macronix */ 398 uint32_t volatile_cfg; 399 uint32_t enh_volatile_cfg; 400 /* Spansion cfg registers. */ 401 uint8_t spansion_cr1nv; 402 uint8_t spansion_cr2nv; 403 uint8_t spansion_cr3nv; 404 uint8_t spansion_cr4nv; 405 uint8_t spansion_cr1v; 406 uint8_t spansion_cr2v; 407 uint8_t spansion_cr3v; 408 uint8_t spansion_cr4v; 409 bool write_enable; 410 bool four_bytes_address_mode; 411 bool reset_enable; 412 bool quad_enable; 413 uint8_t ear; 414 415 int64_t dirty_page; 416 417 const FlashPartInfo *pi; 418 419 } Flash; 420 421 typedef struct M25P80Class { 422 SSISlaveClass parent_class; 423 FlashPartInfo *pi; 424 } M25P80Class; 425 426 #define TYPE_M25P80 "m25p80-generic" 427 #define M25P80(obj) \ 428 OBJECT_CHECK(Flash, (obj), TYPE_M25P80) 429 #define M25P80_CLASS(klass) \ 430 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80) 431 #define M25P80_GET_CLASS(obj) \ 432 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80) 433 434 static inline Manufacturer get_man(Flash *s) 435 { 436 switch (s->pi->id[0]) { 437 case 0x20: 438 return MAN_NUMONYX; 439 case 0xEF: 440 return MAN_WINBOND; 441 case 0x01: 442 return MAN_SPANSION; 443 case 0xC2: 444 return MAN_MACRONIX; 445 default: 446 return MAN_GENERIC; 447 } 448 } 449 450 static void blk_sync_complete(void *opaque, int ret) 451 { 452 QEMUIOVector *iov = opaque; 453 454 qemu_iovec_destroy(iov); 455 g_free(iov); 456 457 /* do nothing. Masters do not directly interact with the backing store, 458 * only the working copy so no mutexing required. 459 */ 460 } 461 462 static void flash_sync_page(Flash *s, int page) 463 { 464 QEMUIOVector *iov; 465 466 if (!s->blk || blk_is_read_only(s->blk)) { 467 return; 468 } 469 470 iov = g_new(QEMUIOVector, 1); 471 qemu_iovec_init(iov, 1); 472 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 473 s->pi->page_size); 474 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 475 blk_sync_complete, iov); 476 } 477 478 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 479 { 480 QEMUIOVector *iov; 481 482 if (!s->blk || blk_is_read_only(s->blk)) { 483 return; 484 } 485 486 assert(!(len % BDRV_SECTOR_SIZE)); 487 iov = g_new(QEMUIOVector, 1); 488 qemu_iovec_init(iov, 1); 489 qemu_iovec_add(iov, s->storage + off, len); 490 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 491 } 492 493 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 494 { 495 uint32_t len; 496 uint8_t capa_to_assert = 0; 497 498 switch (cmd) { 499 case ERASE_4K: 500 case ERASE4_4K: 501 len = 4 << 10; 502 capa_to_assert = ER_4K; 503 break; 504 case ERASE_32K: 505 case ERASE4_32K: 506 len = 32 << 10; 507 capa_to_assert = ER_32K; 508 break; 509 case ERASE_SECTOR: 510 case ERASE4_SECTOR: 511 len = s->pi->sector_size; 512 break; 513 case BULK_ERASE: 514 len = s->size; 515 break; 516 default: 517 abort(); 518 } 519 520 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len); 521 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 522 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 523 " device\n", len); 524 } 525 526 if (!s->write_enable) { 527 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 528 return; 529 } 530 memset(s->storage + offset, 0xff, len); 531 flash_sync_area(s, offset, len); 532 } 533 534 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 535 { 536 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 537 flash_sync_page(s, s->dirty_page); 538 s->dirty_page = newpage; 539 } 540 } 541 542 static inline 543 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 544 { 545 uint32_t page = addr / s->pi->page_size; 546 uint8_t prev = s->storage[s->cur_addr]; 547 548 if (!s->write_enable) { 549 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 550 } 551 552 if ((prev ^ data) & data) { 553 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8 554 " -> %" PRIx8 "\n", addr, prev, data); 555 } 556 557 if (s->pi->flags & EEPROM) { 558 s->storage[s->cur_addr] = data; 559 } else { 560 s->storage[s->cur_addr] &= data; 561 } 562 563 flash_sync_dirty(s, page); 564 s->dirty_page = page; 565 } 566 567 static inline int get_addr_length(Flash *s) 568 { 569 /* check if eeprom is in use */ 570 if (s->pi->flags == EEPROM) { 571 return 2; 572 } 573 574 switch (s->cmd_in_progress) { 575 case PP4: 576 case PP4_4: 577 case READ4: 578 case QIOR4: 579 case ERASE4_4K: 580 case ERASE4_32K: 581 case ERASE4_SECTOR: 582 case FAST_READ4: 583 case DOR4: 584 case QOR4: 585 case DIOR4: 586 return 4; 587 default: 588 return s->four_bytes_address_mode ? 4 : 3; 589 } 590 } 591 592 static void complete_collecting_data(Flash *s) 593 { 594 int i, n; 595 596 n = get_addr_length(s); 597 s->cur_addr = (n == 3 ? s->ear : 0); 598 for (i = 0; i < n; ++i) { 599 s->cur_addr <<= 8; 600 s->cur_addr |= s->data[i]; 601 } 602 603 s->cur_addr &= s->size - 1; 604 605 s->state = STATE_IDLE; 606 607 switch (s->cmd_in_progress) { 608 case DPP: 609 case QPP: 610 case PP: 611 case PP4: 612 case PP4_4: 613 s->state = STATE_PAGE_PROGRAM; 614 break; 615 case READ: 616 case READ4: 617 case FAST_READ: 618 case FAST_READ4: 619 case DOR: 620 case DOR4: 621 case QOR: 622 case QOR4: 623 case DIOR: 624 case DIOR4: 625 case QIOR: 626 case QIOR4: 627 s->state = STATE_READ; 628 break; 629 case ERASE_4K: 630 case ERASE4_4K: 631 case ERASE_32K: 632 case ERASE4_32K: 633 case ERASE_SECTOR: 634 case ERASE4_SECTOR: 635 flash_erase(s, s->cur_addr, s->cmd_in_progress); 636 break; 637 case WRSR: 638 switch (get_man(s)) { 639 case MAN_SPANSION: 640 s->quad_enable = !!(s->data[1] & 0x02); 641 break; 642 case MAN_MACRONIX: 643 s->quad_enable = extract32(s->data[0], 6, 1); 644 if (s->len > 1) { 645 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 646 } 647 break; 648 default: 649 break; 650 } 651 if (s->write_enable) { 652 s->write_enable = false; 653 } 654 break; 655 case EXTEND_ADDR_WRITE: 656 s->ear = s->data[0]; 657 break; 658 case WNVCR: 659 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 660 break; 661 case WVCR: 662 s->volatile_cfg = s->data[0]; 663 break; 664 case WEVCR: 665 s->enh_volatile_cfg = s->data[0]; 666 break; 667 default: 668 break; 669 } 670 } 671 672 static void reset_memory(Flash *s) 673 { 674 s->cmd_in_progress = NOP; 675 s->cur_addr = 0; 676 s->ear = 0; 677 s->four_bytes_address_mode = false; 678 s->len = 0; 679 s->needed_bytes = 0; 680 s->pos = 0; 681 s->state = STATE_IDLE; 682 s->write_enable = false; 683 s->reset_enable = false; 684 s->quad_enable = false; 685 686 switch (get_man(s)) { 687 case MAN_NUMONYX: 688 s->volatile_cfg = 0; 689 s->volatile_cfg |= VCFG_DUMMY; 690 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 691 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 692 != NVCFG_XIP_MODE_DISABLED) { 693 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED; 694 } 695 s->volatile_cfg |= deposit32(s->volatile_cfg, 696 VCFG_DUMMY_CLK_POS, 697 CFG_DUMMY_CLK_LEN, 698 extract32(s->nonvolatile_cfg, 699 NVCFG_DUMMY_CLK_POS, 700 CFG_DUMMY_CLK_LEN) 701 ); 702 703 s->enh_volatile_cfg = 0; 704 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF; 705 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 706 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 707 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 708 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; 709 } 710 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 711 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; 712 } 713 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 714 s->four_bytes_address_mode = true; 715 } 716 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 717 s->ear = s->size / MAX_3BYTES_SIZE - 1; 718 } 719 break; 720 case MAN_MACRONIX: 721 s->volatile_cfg = 0x7; 722 break; 723 case MAN_SPANSION: 724 s->spansion_cr1v = s->spansion_cr1nv; 725 s->spansion_cr2v = s->spansion_cr2nv; 726 s->spansion_cr3v = s->spansion_cr3nv; 727 s->spansion_cr4v = s->spansion_cr4nv; 728 s->quad_enable = extract32(s->spansion_cr1v, 729 SPANSION_QUAD_CFG_POS, 730 SPANSION_QUAD_CFG_LEN 731 ); 732 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 733 SPANSION_ADDR_LEN_POS, 734 SPANSION_ADDR_LEN_LEN 735 ); 736 break; 737 default: 738 break; 739 } 740 741 DB_PRINT_L(0, "Reset done.\n"); 742 } 743 744 static void decode_fast_read_cmd(Flash *s) 745 { 746 s->needed_bytes = get_addr_length(s); 747 switch (get_man(s)) { 748 /* Dummy cycles - modeled with bytes writes instead of bits */ 749 case MAN_WINBOND: 750 s->needed_bytes += 8; 751 break; 752 case MAN_NUMONYX: 753 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 754 break; 755 case MAN_MACRONIX: 756 if (extract32(s->volatile_cfg, 6, 2) == 1) { 757 s->needed_bytes += 6; 758 } else { 759 s->needed_bytes += 8; 760 } 761 break; 762 case MAN_SPANSION: 763 s->needed_bytes += extract32(s->spansion_cr2v, 764 SPANSION_DUMMY_CLK_POS, 765 SPANSION_DUMMY_CLK_LEN 766 ); 767 break; 768 default: 769 break; 770 } 771 s->pos = 0; 772 s->len = 0; 773 s->state = STATE_COLLECTING_DATA; 774 } 775 776 static void decode_dio_read_cmd(Flash *s) 777 { 778 s->needed_bytes = get_addr_length(s); 779 /* Dummy cycles modeled with bytes writes instead of bits */ 780 switch (get_man(s)) { 781 case MAN_WINBOND: 782 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 783 break; 784 case MAN_SPANSION: 785 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 786 s->needed_bytes += extract32(s->spansion_cr2v, 787 SPANSION_DUMMY_CLK_POS, 788 SPANSION_DUMMY_CLK_LEN 789 ); 790 break; 791 case MAN_NUMONYX: 792 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 793 break; 794 case MAN_MACRONIX: 795 switch (extract32(s->volatile_cfg, 6, 2)) { 796 case 1: 797 s->needed_bytes += 6; 798 break; 799 case 2: 800 s->needed_bytes += 8; 801 break; 802 default: 803 s->needed_bytes += 4; 804 break; 805 } 806 break; 807 default: 808 break; 809 } 810 s->pos = 0; 811 s->len = 0; 812 s->state = STATE_COLLECTING_DATA; 813 } 814 815 static void decode_qio_read_cmd(Flash *s) 816 { 817 s->needed_bytes = get_addr_length(s); 818 /* Dummy cycles modeled with bytes writes instead of bits */ 819 switch (get_man(s)) { 820 case MAN_WINBOND: 821 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 822 s->needed_bytes += 4; 823 break; 824 case MAN_SPANSION: 825 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 826 s->needed_bytes += extract32(s->spansion_cr2v, 827 SPANSION_DUMMY_CLK_POS, 828 SPANSION_DUMMY_CLK_LEN 829 ); 830 break; 831 case MAN_NUMONYX: 832 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 833 break; 834 case MAN_MACRONIX: 835 switch (extract32(s->volatile_cfg, 6, 2)) { 836 case 1: 837 s->needed_bytes += 4; 838 break; 839 case 2: 840 s->needed_bytes += 8; 841 break; 842 default: 843 s->needed_bytes += 6; 844 break; 845 } 846 break; 847 default: 848 break; 849 } 850 s->pos = 0; 851 s->len = 0; 852 s->state = STATE_COLLECTING_DATA; 853 } 854 855 static void decode_new_cmd(Flash *s, uint32_t value) 856 { 857 s->cmd_in_progress = value; 858 int i; 859 DB_PRINT_L(0, "decoded new command:%x\n", value); 860 861 if (value != RESET_MEMORY) { 862 s->reset_enable = false; 863 } 864 865 switch (value) { 866 867 case ERASE_4K: 868 case ERASE4_4K: 869 case ERASE_32K: 870 case ERASE4_32K: 871 case ERASE_SECTOR: 872 case ERASE4_SECTOR: 873 case READ: 874 case READ4: 875 case DPP: 876 case QPP: 877 case PP: 878 case PP4: 879 case PP4_4: 880 s->needed_bytes = get_addr_length(s); 881 s->pos = 0; 882 s->len = 0; 883 s->state = STATE_COLLECTING_DATA; 884 break; 885 886 case FAST_READ: 887 case FAST_READ4: 888 case DOR: 889 case DOR4: 890 case QOR: 891 case QOR4: 892 decode_fast_read_cmd(s); 893 break; 894 895 case DIOR: 896 case DIOR4: 897 decode_dio_read_cmd(s); 898 break; 899 900 case QIOR: 901 case QIOR4: 902 decode_qio_read_cmd(s); 903 break; 904 905 case WRSR: 906 if (s->write_enable) { 907 switch (get_man(s)) { 908 case MAN_SPANSION: 909 s->needed_bytes = 2; 910 s->state = STATE_COLLECTING_DATA; 911 break; 912 case MAN_MACRONIX: 913 s->needed_bytes = 2; 914 s->state = STATE_COLLECTING_VAR_LEN_DATA; 915 break; 916 default: 917 s->needed_bytes = 1; 918 s->state = STATE_COLLECTING_DATA; 919 } 920 s->pos = 0; 921 } 922 break; 923 924 case WRDI: 925 s->write_enable = false; 926 break; 927 case WREN: 928 s->write_enable = true; 929 break; 930 931 case RDSR: 932 s->data[0] = (!!s->write_enable) << 1; 933 if (get_man(s) == MAN_MACRONIX) { 934 s->data[0] |= (!!s->quad_enable) << 6; 935 } 936 s->pos = 0; 937 s->len = 1; 938 s->state = STATE_READING_DATA; 939 break; 940 941 case READ_FSR: 942 s->data[0] = FSR_FLASH_READY; 943 if (s->four_bytes_address_mode) { 944 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 945 } 946 s->pos = 0; 947 s->len = 1; 948 s->state = STATE_READING_DATA; 949 break; 950 951 case JEDEC_READ: 952 DB_PRINT_L(0, "populated jedec code\n"); 953 for (i = 0; i < s->pi->id_len; i++) { 954 s->data[i] = s->pi->id[i]; 955 } 956 957 s->len = s->pi->id_len; 958 s->pos = 0; 959 s->state = STATE_READING_DATA; 960 break; 961 962 case RDCR: 963 s->data[0] = s->volatile_cfg & 0xFF; 964 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 965 s->pos = 0; 966 s->len = 1; 967 s->state = STATE_READING_DATA; 968 break; 969 970 case BULK_ERASE: 971 if (s->write_enable) { 972 DB_PRINT_L(0, "chip erase\n"); 973 flash_erase(s, 0, BULK_ERASE); 974 } else { 975 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 976 "protect!\n"); 977 } 978 break; 979 case NOP: 980 break; 981 case EN_4BYTE_ADDR: 982 s->four_bytes_address_mode = true; 983 break; 984 case EX_4BYTE_ADDR: 985 s->four_bytes_address_mode = false; 986 break; 987 case EXTEND_ADDR_READ: 988 s->data[0] = s->ear; 989 s->pos = 0; 990 s->len = 1; 991 s->state = STATE_READING_DATA; 992 break; 993 case EXTEND_ADDR_WRITE: 994 if (s->write_enable) { 995 s->needed_bytes = 1; 996 s->pos = 0; 997 s->len = 0; 998 s->state = STATE_COLLECTING_DATA; 999 } 1000 break; 1001 case RNVCR: 1002 s->data[0] = s->nonvolatile_cfg & 0xFF; 1003 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1004 s->pos = 0; 1005 s->len = 2; 1006 s->state = STATE_READING_DATA; 1007 break; 1008 case WNVCR: 1009 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1010 s->needed_bytes = 2; 1011 s->pos = 0; 1012 s->len = 0; 1013 s->state = STATE_COLLECTING_DATA; 1014 } 1015 break; 1016 case RVCR: 1017 s->data[0] = s->volatile_cfg & 0xFF; 1018 s->pos = 0; 1019 s->len = 1; 1020 s->state = STATE_READING_DATA; 1021 break; 1022 case WVCR: 1023 if (s->write_enable) { 1024 s->needed_bytes = 1; 1025 s->pos = 0; 1026 s->len = 0; 1027 s->state = STATE_COLLECTING_DATA; 1028 } 1029 break; 1030 case REVCR: 1031 s->data[0] = s->enh_volatile_cfg & 0xFF; 1032 s->pos = 0; 1033 s->len = 1; 1034 s->state = STATE_READING_DATA; 1035 break; 1036 case WEVCR: 1037 if (s->write_enable) { 1038 s->needed_bytes = 1; 1039 s->pos = 0; 1040 s->len = 0; 1041 s->state = STATE_COLLECTING_DATA; 1042 } 1043 break; 1044 case RESET_ENABLE: 1045 s->reset_enable = true; 1046 break; 1047 case RESET_MEMORY: 1048 if (s->reset_enable) { 1049 reset_memory(s); 1050 } 1051 break; 1052 case RDCR_EQIO: 1053 switch (get_man(s)) { 1054 case MAN_SPANSION: 1055 s->data[0] = (!!s->quad_enable) << 1; 1056 s->pos = 0; 1057 s->len = 1; 1058 s->state = STATE_READING_DATA; 1059 break; 1060 case MAN_MACRONIX: 1061 s->quad_enable = true; 1062 break; 1063 default: 1064 break; 1065 } 1066 break; 1067 case RSTQIO: 1068 s->quad_enable = false; 1069 break; 1070 default: 1071 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1072 break; 1073 } 1074 } 1075 1076 static int m25p80_cs(SSISlave *ss, bool select) 1077 { 1078 Flash *s = M25P80(ss); 1079 1080 if (select) { 1081 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1082 complete_collecting_data(s); 1083 } 1084 s->len = 0; 1085 s->pos = 0; 1086 s->state = STATE_IDLE; 1087 flash_sync_dirty(s, -1); 1088 } 1089 1090 DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); 1091 1092 return 0; 1093 } 1094 1095 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) 1096 { 1097 Flash *s = M25P80(ss); 1098 uint32_t r = 0; 1099 1100 switch (s->state) { 1101 1102 case STATE_PAGE_PROGRAM: 1103 DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n", 1104 s->cur_addr, (uint8_t)tx); 1105 flash_write8(s, s->cur_addr, (uint8_t)tx); 1106 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1107 break; 1108 1109 case STATE_READ: 1110 r = s->storage[s->cur_addr]; 1111 DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr, 1112 (uint8_t)r); 1113 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1114 break; 1115 1116 case STATE_COLLECTING_DATA: 1117 case STATE_COLLECTING_VAR_LEN_DATA: 1118 s->data[s->len] = (uint8_t)tx; 1119 s->len++; 1120 1121 if (s->len == s->needed_bytes) { 1122 complete_collecting_data(s); 1123 } 1124 break; 1125 1126 case STATE_READING_DATA: 1127 r = s->data[s->pos]; 1128 s->pos++; 1129 if (s->pos == s->len) { 1130 s->pos = 0; 1131 s->state = STATE_IDLE; 1132 } 1133 break; 1134 1135 default: 1136 case STATE_IDLE: 1137 decode_new_cmd(s, (uint8_t)tx); 1138 break; 1139 } 1140 1141 return r; 1142 } 1143 1144 static void m25p80_realize(SSISlave *ss, Error **errp) 1145 { 1146 Flash *s = M25P80(ss); 1147 M25P80Class *mc = M25P80_GET_CLASS(s); 1148 1149 s->pi = mc->pi; 1150 1151 s->size = s->pi->sector_size * s->pi->n_sectors; 1152 s->dirty_page = -1; 1153 1154 if (s->blk) { 1155 DB_PRINT_L(0, "Binding to IF_MTD drive\n"); 1156 s->storage = blk_blockalign(s->blk, s->size); 1157 1158 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) { 1159 error_setg(errp, "failed to read the initial flash content"); 1160 return; 1161 } 1162 } else { 1163 DB_PRINT_L(0, "No BDRV - binding to RAM\n"); 1164 s->storage = blk_blockalign(NULL, s->size); 1165 memset(s->storage, 0xFF, s->size); 1166 } 1167 } 1168 1169 static void m25p80_reset(DeviceState *d) 1170 { 1171 Flash *s = M25P80(d); 1172 1173 reset_memory(s); 1174 } 1175 1176 static void m25p80_pre_save(void *opaque) 1177 { 1178 flash_sync_dirty((Flash *)opaque, -1); 1179 } 1180 1181 static Property m25p80_properties[] = { 1182 /* This is default value for Micron flash */ 1183 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1184 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1185 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1186 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1187 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1188 DEFINE_PROP_DRIVE("drive", Flash, blk), 1189 DEFINE_PROP_END_OF_LIST(), 1190 }; 1191 1192 static const VMStateDescription vmstate_m25p80 = { 1193 .name = "m25p80", 1194 .version_id = 0, 1195 .minimum_version_id = 0, 1196 .pre_save = m25p80_pre_save, 1197 .fields = (VMStateField[]) { 1198 VMSTATE_UINT8(state, Flash), 1199 VMSTATE_UINT8_ARRAY(data, Flash, 16), 1200 VMSTATE_UINT32(len, Flash), 1201 VMSTATE_UINT32(pos, Flash), 1202 VMSTATE_UINT8(needed_bytes, Flash), 1203 VMSTATE_UINT8(cmd_in_progress, Flash), 1204 VMSTATE_UINT32(cur_addr, Flash), 1205 VMSTATE_BOOL(write_enable, Flash), 1206 VMSTATE_BOOL(reset_enable, Flash), 1207 VMSTATE_UINT8(ear, Flash), 1208 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1209 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1210 VMSTATE_UINT32(volatile_cfg, Flash), 1211 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1212 VMSTATE_BOOL(quad_enable, Flash), 1213 VMSTATE_UINT8(spansion_cr1nv, Flash), 1214 VMSTATE_UINT8(spansion_cr2nv, Flash), 1215 VMSTATE_UINT8(spansion_cr3nv, Flash), 1216 VMSTATE_UINT8(spansion_cr4nv, Flash), 1217 VMSTATE_END_OF_LIST() 1218 } 1219 }; 1220 1221 static void m25p80_class_init(ObjectClass *klass, void *data) 1222 { 1223 DeviceClass *dc = DEVICE_CLASS(klass); 1224 SSISlaveClass *k = SSI_SLAVE_CLASS(klass); 1225 M25P80Class *mc = M25P80_CLASS(klass); 1226 1227 k->realize = m25p80_realize; 1228 k->transfer = m25p80_transfer8; 1229 k->set_cs = m25p80_cs; 1230 k->cs_polarity = SSI_CS_LOW; 1231 dc->vmsd = &vmstate_m25p80; 1232 dc->props = m25p80_properties; 1233 dc->reset = m25p80_reset; 1234 mc->pi = data; 1235 } 1236 1237 static const TypeInfo m25p80_info = { 1238 .name = TYPE_M25P80, 1239 .parent = TYPE_SSI_SLAVE, 1240 .instance_size = sizeof(Flash), 1241 .class_size = sizeof(M25P80Class), 1242 .abstract = true, 1243 }; 1244 1245 static void m25p80_register_types(void) 1246 { 1247 int i; 1248 1249 type_register_static(&m25p80_info); 1250 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1251 TypeInfo ti = { 1252 .name = known_devices[i].part_name, 1253 .parent = TYPE_M25P80, 1254 .class_init = m25p80_class_init, 1255 .class_data = (void *)&known_devices[i], 1256 }; 1257 type_register(&ti); 1258 } 1259 } 1260 1261 type_init(m25p80_register_types) 1262