1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/block/block.h" 28 #include "hw/block/flash.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/qdev-properties-system.h" 31 #include "hw/ssi/ssi.h" 32 #include "migration/vmstate.h" 33 #include "qemu/bitops.h" 34 #include "qemu/log.h" 35 #include "qemu/module.h" 36 #include "qemu/error-report.h" 37 #include "qapi/error.h" 38 #include "trace.h" 39 #include "qom/object.h" 40 #include "m25p80_sfdp.h" 41 42 /* 16 MiB max in 3 byte address mode */ 43 #define MAX_3BYTES_SIZE 0x1000000 44 #define SPI_NOR_MAX_ID_LEN 6 45 46 /* Fields for FlashPartInfo->flags */ 47 enum spi_flash_option_flags { 48 ER_4K = BIT(0), 49 ER_32K = BIT(1), 50 EEPROM = BIT(2), 51 HAS_SR_TB = BIT(3), 52 HAS_SR_BP3_BIT6 = BIT(4), 53 }; 54 55 typedef struct FlashPartInfo { 56 const char *part_name; 57 /* 58 * This array stores the ID bytes. 59 * The first three bytes are the JEDIC ID. 60 * JEDEC ID zero means "no ID" (mostly older chips). 61 */ 62 uint8_t id[SPI_NOR_MAX_ID_LEN]; 63 uint8_t id_len; 64 /* there is confusion between manufacturers as to what a sector is. In this 65 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 66 * command (opcode 0xd8). 67 */ 68 uint32_t sector_size; 69 uint32_t n_sectors; 70 uint32_t page_size; 71 uint16_t flags; 72 /* 73 * Big sized spi nor are often stacked devices, thus sometime 74 * replace chip erase with die erase. 75 * This field inform how many die is in the chip. 76 */ 77 uint8_t die_cnt; 78 uint8_t (*sfdp_read)(uint32_t sfdp_addr); 79 } FlashPartInfo; 80 81 /* adapted from linux */ 82 /* Used when the "_ext_id" is two bytes at most */ 83 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 84 .part_name = _part_name,\ 85 .id = {\ 86 ((_jedec_id) >> 16) & 0xff,\ 87 ((_jedec_id) >> 8) & 0xff,\ 88 (_jedec_id) & 0xff,\ 89 ((_ext_id) >> 8) & 0xff,\ 90 (_ext_id) & 0xff,\ 91 },\ 92 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 93 .sector_size = (_sector_size),\ 94 .n_sectors = (_n_sectors),\ 95 .page_size = 256,\ 96 .flags = (_flags),\ 97 .die_cnt = 0 98 99 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 100 .part_name = _part_name,\ 101 .id = {\ 102 ((_jedec_id) >> 16) & 0xff,\ 103 ((_jedec_id) >> 8) & 0xff,\ 104 (_jedec_id) & 0xff,\ 105 ((_ext_id) >> 16) & 0xff,\ 106 ((_ext_id) >> 8) & 0xff,\ 107 (_ext_id) & 0xff,\ 108 },\ 109 .id_len = 6,\ 110 .sector_size = (_sector_size),\ 111 .n_sectors = (_n_sectors),\ 112 .page_size = 256,\ 113 .flags = (_flags),\ 114 .die_cnt = 0 115 116 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ 117 _flags, _die_cnt)\ 118 .part_name = _part_name,\ 119 .id = {\ 120 ((_jedec_id) >> 16) & 0xff,\ 121 ((_jedec_id) >> 8) & 0xff,\ 122 (_jedec_id) & 0xff,\ 123 ((_ext_id) >> 8) & 0xff,\ 124 (_ext_id) & 0xff,\ 125 },\ 126 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 127 .sector_size = (_sector_size),\ 128 .n_sectors = (_n_sectors),\ 129 .page_size = 256,\ 130 .flags = (_flags),\ 131 .die_cnt = _die_cnt 132 133 #define JEDEC_NUMONYX 0x20 134 #define JEDEC_WINBOND 0xEF 135 #define JEDEC_SPANSION 0x01 136 137 /* Numonyx (Micron) Configuration register macros */ 138 #define VCFG_DUMMY 0x1 139 #define VCFG_WRAP_SEQUENTIAL 0x2 140 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 141 #define NVCFG_XIP_MODE_MASK (7 << 9) 142 #define VCFG_XIP_MODE_DISABLED (1 << 3) 143 #define CFG_DUMMY_CLK_LEN 4 144 #define NVCFG_DUMMY_CLK_POS 12 145 #define VCFG_DUMMY_CLK_POS 4 146 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 147 #define EVCFG_VPP_ACCELERATOR (1 << 3) 148 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 149 #define NVCFG_DUAL_IO_MASK (1 << 2) 150 #define EVCFG_DUAL_IO_DISABLED (1 << 6) 151 #define NVCFG_QUAD_IO_MASK (1 << 3) 152 #define EVCFG_QUAD_IO_DISABLED (1 << 7) 153 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 154 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 155 156 /* Numonyx (Micron) Flag Status Register macros */ 157 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 158 #define FSR_FLASH_READY (1 << 7) 159 160 /* Spansion configuration registers macros. */ 161 #define SPANSION_QUAD_CFG_POS 0 162 #define SPANSION_QUAD_CFG_LEN 1 163 #define SPANSION_DUMMY_CLK_POS 0 164 #define SPANSION_DUMMY_CLK_LEN 4 165 #define SPANSION_ADDR_LEN_POS 7 166 #define SPANSION_ADDR_LEN_LEN 1 167 168 /* 169 * Spansion read mode command length in bytes, 170 * the mode is currently not supported. 171 */ 172 173 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 174 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 175 176 static const FlashPartInfo known_devices[] = { 177 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 178 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 179 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 180 181 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 182 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 183 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 184 185 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 186 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 187 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 188 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 189 190 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 191 192 /* Atmel EEPROMS - it is assumed, that don't care bit in command 193 * is set to 0. Block protection is not supported. 194 */ 195 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 196 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 197 198 /* EON -- en25xxx */ 199 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 200 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 201 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 202 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 203 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 204 205 /* GigaDevice */ 206 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 207 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 208 209 /* Intel/Numonyx -- xxxs33b */ 210 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 211 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 212 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 213 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 214 215 /* ISSI */ 216 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, 217 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, 218 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, 219 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, 220 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, 221 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, 222 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) }, 223 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) }, 224 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) }, 225 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) }, 226 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K), 227 .sfdp_read = m25p80_sfdp_is25wp256 }, 228 229 /* Macronix */ 230 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 231 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 232 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 233 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 234 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 235 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 236 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 237 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 238 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 239 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e }, 240 { INFO6("mx25l25635f", 0xc22019, 0xc22019, 64 << 10, 512, 241 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f }, 242 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 243 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 244 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 245 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 246 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K), 247 .sfdp_read = m25p80_sfdp_mx66l1g45g }, 248 249 /* Micron */ 250 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 251 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 252 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 253 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 254 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 255 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 256 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 257 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K), 258 .sfdp_read = m25p80_sfdp_n25q256a }, 259 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, 260 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 261 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 262 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, 263 ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB), 264 .sfdp_read = m25p80_sfdp_n25q256a }, 265 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 266 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, 267 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, 268 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024, 269 ER_4K | ER_32K, 2) }, 270 { INFO_STACKED("mt35xu02gbba", 0x2c5b1c, 0x104100, 128 << 10, 2048, 271 ER_4K | ER_32K, 4), 272 .sfdp_read = m25p80_sfdp_mt35xu02g }, 273 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 274 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 275 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 276 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 277 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 278 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 279 280 /* Spansion -- single (large) sector size only, at least 281 * for the chips listed here (without boot sectors). 282 */ 283 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 284 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 285 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 286 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 287 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 288 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 289 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 290 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 291 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 292 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 293 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 294 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 295 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 296 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 297 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 298 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 299 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 300 301 /* Spansion -- boot sectors support */ 302 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 303 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 304 305 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 306 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 307 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 308 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 309 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 310 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 311 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 312 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 313 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 314 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 315 316 /* ST Microelectronics -- newer production may have feature updates */ 317 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 318 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 319 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 320 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 321 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 322 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 323 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 324 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 325 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 326 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 327 328 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 329 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 330 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 331 332 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 333 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 334 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 335 336 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 337 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 338 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 339 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 340 341 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 342 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 343 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 344 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 345 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 346 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 347 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 348 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 349 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 350 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 351 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 352 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 353 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 354 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K), 355 .sfdp_read = m25p80_sfdp_w25q256 }, 356 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K), 357 .sfdp_read = m25p80_sfdp_w25q512jv }, 358 { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K), 359 .sfdp_read = m25p80_sfdp_w25q01jvq }, 360 }; 361 362 typedef enum { 363 NOP = 0, 364 WRSR = 0x1, 365 WRDI = 0x4, 366 RDSR = 0x5, 367 WREN = 0x6, 368 BRRD = 0x16, 369 BRWR = 0x17, 370 JEDEC_READ = 0x9f, 371 BULK_ERASE_60 = 0x60, 372 BULK_ERASE = 0xc7, 373 READ_FSR = 0x70, 374 RDCR = 0x15, 375 RDSFDP = 0x5a, 376 377 READ = 0x03, 378 READ4 = 0x13, 379 FAST_READ = 0x0b, 380 FAST_READ4 = 0x0c, 381 DOR = 0x3b, 382 DOR4 = 0x3c, 383 QOR = 0x6b, 384 QOR4 = 0x6c, 385 DIOR = 0xbb, 386 DIOR4 = 0xbc, 387 QIOR = 0xeb, 388 QIOR4 = 0xec, 389 390 PP = 0x02, 391 PP4 = 0x12, 392 PP4_4 = 0x3e, 393 DPP = 0xa2, 394 QPP = 0x32, 395 QPP_4 = 0x34, 396 RDID_90 = 0x90, 397 RDID_AB = 0xab, 398 AAI_WP = 0xad, 399 400 ERASE_4K = 0x20, 401 ERASE4_4K = 0x21, 402 ERASE_32K = 0x52, 403 ERASE4_32K = 0x5c, 404 ERASE_SECTOR = 0xd8, 405 ERASE4_SECTOR = 0xdc, 406 407 EN_4BYTE_ADDR = 0xB7, 408 EX_4BYTE_ADDR = 0xE9, 409 410 EXTEND_ADDR_READ = 0xC8, 411 EXTEND_ADDR_WRITE = 0xC5, 412 413 RESET_ENABLE = 0x66, 414 RESET_MEMORY = 0x99, 415 416 /* 417 * Micron: 0x35 - enable QPI 418 * Spansion: 0x35 - read control register 419 */ 420 RDCR_EQIO = 0x35, 421 RSTQIO = 0xf5, 422 423 RNVCR = 0xB5, 424 WNVCR = 0xB1, 425 426 RVCR = 0x85, 427 WVCR = 0x81, 428 429 REVCR = 0x65, 430 WEVCR = 0x61, 431 432 DIE_ERASE = 0xC4, 433 } FlashCMD; 434 435 typedef enum { 436 STATE_IDLE, 437 STATE_PAGE_PROGRAM, 438 STATE_READ, 439 STATE_COLLECTING_DATA, 440 STATE_COLLECTING_VAR_LEN_DATA, 441 STATE_READING_DATA, 442 STATE_READING_SFDP, 443 } CMDState; 444 445 typedef enum { 446 MAN_SPANSION, 447 MAN_MACRONIX, 448 MAN_NUMONYX, 449 MAN_WINBOND, 450 MAN_SST, 451 MAN_ISSI, 452 MAN_GENERIC, 453 } Manufacturer; 454 455 typedef enum { 456 MODE_STD = 0, 457 MODE_DIO = 1, 458 MODE_QIO = 2 459 } SPIMode; 460 461 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 462 463 struct Flash { 464 SSIPeripheral parent_obj; 465 466 BlockBackend *blk; 467 468 uint8_t *storage; 469 uint32_t size; 470 int page_size; 471 472 uint8_t state; 473 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 474 uint32_t len; 475 uint32_t pos; 476 bool data_read_loop; 477 uint8_t needed_bytes; 478 uint8_t cmd_in_progress; 479 uint32_t cur_addr; 480 uint32_t nonvolatile_cfg; 481 /* Configuration register for Macronix */ 482 uint32_t volatile_cfg; 483 uint32_t enh_volatile_cfg; 484 /* Spansion cfg registers. */ 485 uint8_t spansion_cr1nv; 486 uint8_t spansion_cr2nv; 487 uint8_t spansion_cr3nv; 488 uint8_t spansion_cr4nv; 489 uint8_t spansion_cr1v; 490 uint8_t spansion_cr2v; 491 uint8_t spansion_cr3v; 492 uint8_t spansion_cr4v; 493 bool wp_level; 494 bool write_enable; 495 bool four_bytes_address_mode; 496 bool reset_enable; 497 bool quad_enable; 498 bool aai_enable; 499 bool block_protect0; 500 bool block_protect1; 501 bool block_protect2; 502 bool block_protect3; 503 bool top_bottom_bit; 504 bool status_register_write_disabled; 505 uint8_t ear; 506 507 int64_t dirty_page; 508 509 const FlashPartInfo *pi; 510 511 }; 512 513 struct M25P80Class { 514 SSIPeripheralClass parent_class; 515 FlashPartInfo *pi; 516 }; 517 518 #define TYPE_M25P80 "m25p80-generic" 519 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) 520 521 static inline Manufacturer get_man(Flash *s) 522 { 523 switch (s->pi->id[0]) { 524 case 0x20: 525 return MAN_NUMONYX; 526 case 0xEF: 527 return MAN_WINBOND; 528 case 0x01: 529 return MAN_SPANSION; 530 case 0xC2: 531 return MAN_MACRONIX; 532 case 0xBF: 533 return MAN_SST; 534 case 0x9D: 535 return MAN_ISSI; 536 default: 537 return MAN_GENERIC; 538 } 539 } 540 541 static void blk_sync_complete(void *opaque, int ret) 542 { 543 QEMUIOVector *iov = opaque; 544 545 qemu_iovec_destroy(iov); 546 g_free(iov); 547 548 /* do nothing. Masters do not directly interact with the backing store, 549 * only the working copy so no mutexing required. 550 */ 551 } 552 553 static void flash_sync_page(Flash *s, int page) 554 { 555 QEMUIOVector *iov; 556 557 if (!s->blk || !blk_is_writable(s->blk)) { 558 return; 559 } 560 561 iov = g_new(QEMUIOVector, 1); 562 qemu_iovec_init(iov, 1); 563 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 564 s->pi->page_size); 565 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 566 blk_sync_complete, iov); 567 } 568 569 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 570 { 571 QEMUIOVector *iov; 572 573 if (!s->blk || !blk_is_writable(s->blk)) { 574 return; 575 } 576 577 assert(!(len % BDRV_SECTOR_SIZE)); 578 iov = g_new(QEMUIOVector, 1); 579 qemu_iovec_init(iov, 1); 580 qemu_iovec_add(iov, s->storage + off, len); 581 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 582 } 583 584 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 585 { 586 uint32_t len; 587 uint8_t capa_to_assert = 0; 588 589 switch (cmd) { 590 case ERASE_4K: 591 case ERASE4_4K: 592 len = 4 * KiB; 593 capa_to_assert = ER_4K; 594 break; 595 case ERASE_32K: 596 case ERASE4_32K: 597 len = 32 * KiB; 598 capa_to_assert = ER_32K; 599 break; 600 case ERASE_SECTOR: 601 case ERASE4_SECTOR: 602 len = s->pi->sector_size; 603 break; 604 case BULK_ERASE: 605 len = s->size; 606 break; 607 case DIE_ERASE: 608 if (s->pi->die_cnt) { 609 len = s->size / s->pi->die_cnt; 610 offset = offset & (~(len - 1)); 611 } else { 612 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" 613 " by device\n"); 614 return; 615 } 616 break; 617 default: 618 abort(); 619 } 620 621 trace_m25p80_flash_erase(s, offset, len); 622 623 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 624 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 625 " device\n", len); 626 } 627 628 if (!s->write_enable) { 629 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 630 return; 631 } 632 memset(s->storage + offset, 0xff, len); 633 flash_sync_area(s, offset, len); 634 } 635 636 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 637 { 638 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 639 flash_sync_page(s, s->dirty_page); 640 s->dirty_page = newpage; 641 } 642 } 643 644 static inline 645 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 646 { 647 uint32_t page = addr / s->pi->page_size; 648 uint8_t prev = s->storage[s->cur_addr]; 649 uint32_t block_protect_value = (s->block_protect3 << 3) | 650 (s->block_protect2 << 2) | 651 (s->block_protect1 << 1) | 652 (s->block_protect0 << 0); 653 654 if (!s->write_enable) { 655 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 656 return; 657 } 658 659 if (block_protect_value > 0) { 660 uint32_t num_protected_sectors = 1 << (block_protect_value - 1); 661 uint32_t sector = addr / s->pi->sector_size; 662 663 /* top_bottom_bit == 0 means TOP */ 664 if (!s->top_bottom_bit) { 665 if (s->pi->n_sectors <= sector + num_protected_sectors) { 666 qemu_log_mask(LOG_GUEST_ERROR, 667 "M25P80: write with write protect!\n"); 668 return; 669 } 670 } else { 671 if (sector < num_protected_sectors) { 672 qemu_log_mask(LOG_GUEST_ERROR, 673 "M25P80: write with write protect!\n"); 674 return; 675 } 676 } 677 } 678 679 if ((prev ^ data) & data) { 680 trace_m25p80_programming_zero_to_one(s, addr, prev, data); 681 } 682 683 if (s->pi->flags & EEPROM) { 684 s->storage[s->cur_addr] = data; 685 } else { 686 s->storage[s->cur_addr] &= data; 687 } 688 689 flash_sync_dirty(s, page); 690 s->dirty_page = page; 691 } 692 693 static inline int get_addr_length(Flash *s) 694 { 695 /* check if eeprom is in use */ 696 if (s->pi->flags == EEPROM) { 697 return 2; 698 } 699 700 switch (s->cmd_in_progress) { 701 case RDSFDP: 702 return 3; 703 case PP4: 704 case PP4_4: 705 case QPP_4: 706 case READ4: 707 case QIOR4: 708 case ERASE4_4K: 709 case ERASE4_32K: 710 case ERASE4_SECTOR: 711 case FAST_READ4: 712 case DOR4: 713 case QOR4: 714 case DIOR4: 715 return 4; 716 default: 717 return s->four_bytes_address_mode ? 4 : 3; 718 } 719 } 720 721 static void complete_collecting_data(Flash *s) 722 { 723 int i, n; 724 725 n = get_addr_length(s); 726 s->cur_addr = (n == 3 ? s->ear : 0); 727 for (i = 0; i < n; ++i) { 728 s->cur_addr <<= 8; 729 s->cur_addr |= s->data[i]; 730 } 731 732 s->cur_addr &= s->size - 1; 733 734 s->state = STATE_IDLE; 735 736 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, 737 s->cur_addr); 738 739 switch (s->cmd_in_progress) { 740 case DPP: 741 case QPP: 742 case QPP_4: 743 case PP: 744 case PP4: 745 case PP4_4: 746 s->state = STATE_PAGE_PROGRAM; 747 break; 748 case AAI_WP: 749 /* AAI programming starts from the even address */ 750 s->cur_addr &= ~BIT(0); 751 s->state = STATE_PAGE_PROGRAM; 752 break; 753 case READ: 754 case READ4: 755 case FAST_READ: 756 case FAST_READ4: 757 case DOR: 758 case DOR4: 759 case QOR: 760 case QOR4: 761 case DIOR: 762 case DIOR4: 763 case QIOR: 764 case QIOR4: 765 s->state = STATE_READ; 766 break; 767 case ERASE_4K: 768 case ERASE4_4K: 769 case ERASE_32K: 770 case ERASE4_32K: 771 case ERASE_SECTOR: 772 case ERASE4_SECTOR: 773 case DIE_ERASE: 774 flash_erase(s, s->cur_addr, s->cmd_in_progress); 775 break; 776 case WRSR: 777 s->status_register_write_disabled = extract32(s->data[0], 7, 1); 778 s->block_protect0 = extract32(s->data[0], 2, 1); 779 s->block_protect1 = extract32(s->data[0], 3, 1); 780 s->block_protect2 = extract32(s->data[0], 4, 1); 781 if (s->pi->flags & HAS_SR_TB) { 782 s->top_bottom_bit = extract32(s->data[0], 5, 1); 783 } 784 if (s->pi->flags & HAS_SR_BP3_BIT6) { 785 s->block_protect3 = extract32(s->data[0], 6, 1); 786 } 787 788 switch (get_man(s)) { 789 case MAN_SPANSION: 790 s->quad_enable = !!(s->data[1] & 0x02); 791 break; 792 case MAN_ISSI: 793 s->quad_enable = extract32(s->data[0], 6, 1); 794 break; 795 case MAN_MACRONIX: 796 s->quad_enable = extract32(s->data[0], 6, 1); 797 if (s->len > 1) { 798 s->volatile_cfg = s->data[1]; 799 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 800 } 801 break; 802 default: 803 break; 804 } 805 if (s->write_enable) { 806 s->write_enable = false; 807 } 808 break; 809 case BRWR: 810 case EXTEND_ADDR_WRITE: 811 s->ear = s->data[0]; 812 break; 813 case WNVCR: 814 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 815 break; 816 case WVCR: 817 s->volatile_cfg = s->data[0]; 818 break; 819 case WEVCR: 820 s->enh_volatile_cfg = s->data[0]; 821 break; 822 case RDID_90: 823 case RDID_AB: 824 if (get_man(s) == MAN_SST) { 825 if (s->cur_addr <= 1) { 826 if (s->cur_addr) { 827 s->data[0] = s->pi->id[2]; 828 s->data[1] = s->pi->id[0]; 829 } else { 830 s->data[0] = s->pi->id[0]; 831 s->data[1] = s->pi->id[2]; 832 } 833 s->pos = 0; 834 s->len = 2; 835 s->data_read_loop = true; 836 s->state = STATE_READING_DATA; 837 } else { 838 qemu_log_mask(LOG_GUEST_ERROR, 839 "M25P80: Invalid read id address\n"); 840 } 841 } else { 842 qemu_log_mask(LOG_GUEST_ERROR, 843 "M25P80: Read id (command 0x90/0xAB) is not supported" 844 " by device\n"); 845 } 846 break; 847 848 case RDSFDP: 849 s->state = STATE_READING_SFDP; 850 break; 851 852 default: 853 break; 854 } 855 } 856 857 static void reset_memory(Flash *s) 858 { 859 s->cmd_in_progress = NOP; 860 s->cur_addr = 0; 861 s->ear = 0; 862 s->four_bytes_address_mode = false; 863 s->len = 0; 864 s->needed_bytes = 0; 865 s->pos = 0; 866 s->state = STATE_IDLE; 867 s->write_enable = false; 868 s->reset_enable = false; 869 s->quad_enable = false; 870 s->aai_enable = false; 871 872 switch (get_man(s)) { 873 case MAN_NUMONYX: 874 s->volatile_cfg = 0; 875 s->volatile_cfg |= VCFG_DUMMY; 876 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 877 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 878 == NVCFG_XIP_MODE_DISABLED) { 879 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; 880 } 881 s->volatile_cfg |= deposit32(s->volatile_cfg, 882 VCFG_DUMMY_CLK_POS, 883 CFG_DUMMY_CLK_LEN, 884 extract32(s->nonvolatile_cfg, 885 NVCFG_DUMMY_CLK_POS, 886 CFG_DUMMY_CLK_LEN) 887 ); 888 889 s->enh_volatile_cfg = 0; 890 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; 891 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 892 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 893 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 894 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; 895 } 896 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 897 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; 898 } 899 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 900 s->four_bytes_address_mode = true; 901 } 902 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 903 s->ear = s->size / MAX_3BYTES_SIZE - 1; 904 } 905 break; 906 case MAN_MACRONIX: 907 s->volatile_cfg = 0x7; 908 break; 909 case MAN_SPANSION: 910 s->spansion_cr1v = s->spansion_cr1nv; 911 s->spansion_cr2v = s->spansion_cr2nv; 912 s->spansion_cr3v = s->spansion_cr3nv; 913 s->spansion_cr4v = s->spansion_cr4nv; 914 s->quad_enable = extract32(s->spansion_cr1v, 915 SPANSION_QUAD_CFG_POS, 916 SPANSION_QUAD_CFG_LEN 917 ); 918 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 919 SPANSION_ADDR_LEN_POS, 920 SPANSION_ADDR_LEN_LEN 921 ); 922 break; 923 default: 924 break; 925 } 926 927 trace_m25p80_reset_done(s); 928 } 929 930 static uint8_t numonyx_mode(Flash *s) 931 { 932 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { 933 return MODE_QIO; 934 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { 935 return MODE_DIO; 936 } else { 937 return MODE_STD; 938 } 939 } 940 941 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s) 942 { 943 uint8_t num_dummies; 944 uint8_t mode; 945 assert(get_man(s) == MAN_NUMONYX); 946 947 mode = numonyx_mode(s); 948 num_dummies = extract32(s->volatile_cfg, 4, 4); 949 950 if (num_dummies == 0x0 || num_dummies == 0xf) { 951 switch (s->cmd_in_progress) { 952 case QIOR: 953 case QIOR4: 954 num_dummies = 10; 955 break; 956 default: 957 num_dummies = (mode == MODE_QIO) ? 10 : 8; 958 break; 959 } 960 } 961 962 return num_dummies; 963 } 964 965 static void decode_fast_read_cmd(Flash *s) 966 { 967 s->needed_bytes = get_addr_length(s); 968 switch (get_man(s)) { 969 /* Dummy cycles - modeled with bytes writes instead of bits */ 970 case MAN_SST: 971 s->needed_bytes += 1; 972 break; 973 case MAN_WINBOND: 974 s->needed_bytes += 8; 975 break; 976 case MAN_NUMONYX: 977 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 978 break; 979 case MAN_MACRONIX: 980 if (extract32(s->volatile_cfg, 6, 2) == 1) { 981 s->needed_bytes += 6; 982 } else { 983 s->needed_bytes += 8; 984 } 985 break; 986 case MAN_SPANSION: 987 s->needed_bytes += extract32(s->spansion_cr2v, 988 SPANSION_DUMMY_CLK_POS, 989 SPANSION_DUMMY_CLK_LEN 990 ); 991 break; 992 case MAN_ISSI: 993 /* 994 * The Fast Read instruction code is followed by address bytes and 995 * dummy cycles, transmitted via the SI line. 996 * 997 * The number of dummy cycles is configurable but this is currently 998 * unmodeled, hence the default value 8 is used. 999 * 1000 * QPI (Quad Peripheral Interface) mode has different default value 1001 * of dummy cycles, but this is unsupported at the time being. 1002 */ 1003 s->needed_bytes += 1; 1004 break; 1005 default: 1006 break; 1007 } 1008 s->pos = 0; 1009 s->len = 0; 1010 s->state = STATE_COLLECTING_DATA; 1011 } 1012 1013 static void decode_dio_read_cmd(Flash *s) 1014 { 1015 s->needed_bytes = get_addr_length(s); 1016 /* Dummy cycles modeled with bytes writes instead of bits */ 1017 switch (get_man(s)) { 1018 case MAN_WINBOND: 1019 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1020 break; 1021 case MAN_SPANSION: 1022 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1023 s->needed_bytes += extract32(s->spansion_cr2v, 1024 SPANSION_DUMMY_CLK_POS, 1025 SPANSION_DUMMY_CLK_LEN 1026 ); 1027 break; 1028 case MAN_NUMONYX: 1029 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1030 break; 1031 case MAN_MACRONIX: 1032 switch (extract32(s->volatile_cfg, 6, 2)) { 1033 case 1: 1034 s->needed_bytes += 6; 1035 break; 1036 case 2: 1037 s->needed_bytes += 8; 1038 break; 1039 default: 1040 s->needed_bytes += 4; 1041 break; 1042 } 1043 break; 1044 case MAN_ISSI: 1045 /* 1046 * The Fast Read Dual I/O instruction code is followed by address bytes 1047 * and dummy cycles, transmitted via the IO1 and IO0 line. 1048 * 1049 * The number of dummy cycles is configurable but this is currently 1050 * unmodeled, hence the default value 4 is used. 1051 */ 1052 s->needed_bytes += 1; 1053 break; 1054 default: 1055 break; 1056 } 1057 s->pos = 0; 1058 s->len = 0; 1059 s->state = STATE_COLLECTING_DATA; 1060 } 1061 1062 static void decode_qio_read_cmd(Flash *s) 1063 { 1064 s->needed_bytes = get_addr_length(s); 1065 /* Dummy cycles modeled with bytes writes instead of bits */ 1066 switch (get_man(s)) { 1067 case MAN_WINBOND: 1068 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1069 s->needed_bytes += 4; 1070 break; 1071 case MAN_SPANSION: 1072 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1073 s->needed_bytes += extract32(s->spansion_cr2v, 1074 SPANSION_DUMMY_CLK_POS, 1075 SPANSION_DUMMY_CLK_LEN 1076 ); 1077 break; 1078 case MAN_NUMONYX: 1079 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1080 break; 1081 case MAN_MACRONIX: 1082 switch (extract32(s->volatile_cfg, 6, 2)) { 1083 case 1: 1084 s->needed_bytes += 4; 1085 break; 1086 case 2: 1087 s->needed_bytes += 8; 1088 break; 1089 default: 1090 s->needed_bytes += 6; 1091 break; 1092 } 1093 break; 1094 case MAN_ISSI: 1095 /* 1096 * The Fast Read Quad I/O instruction code is followed by address bytes 1097 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line. 1098 * 1099 * The number of dummy cycles is configurable but this is currently 1100 * unmodeled, hence the default value 6 is used. 1101 * 1102 * QPI (Quad Peripheral Interface) mode has different default value 1103 * of dummy cycles, but this is unsupported at the time being. 1104 */ 1105 s->needed_bytes += 3; 1106 break; 1107 default: 1108 break; 1109 } 1110 s->pos = 0; 1111 s->len = 0; 1112 s->state = STATE_COLLECTING_DATA; 1113 } 1114 1115 static bool is_valid_aai_cmd(uint32_t cmd) 1116 { 1117 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR; 1118 } 1119 1120 static void decode_new_cmd(Flash *s, uint32_t value) 1121 { 1122 int i; 1123 1124 s->cmd_in_progress = value; 1125 trace_m25p80_command_decoded(s, value); 1126 1127 if (value != RESET_MEMORY) { 1128 s->reset_enable = false; 1129 } 1130 1131 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) { 1132 qemu_log_mask(LOG_GUEST_ERROR, 1133 "M25P80: Invalid cmd within AAI programming sequence"); 1134 } 1135 1136 switch (value) { 1137 1138 case ERASE_4K: 1139 case ERASE4_4K: 1140 case ERASE_32K: 1141 case ERASE4_32K: 1142 case ERASE_SECTOR: 1143 case ERASE4_SECTOR: 1144 case PP: 1145 case PP4: 1146 case DIE_ERASE: 1147 case RDID_90: 1148 case RDID_AB: 1149 s->needed_bytes = get_addr_length(s); 1150 s->pos = 0; 1151 s->len = 0; 1152 s->state = STATE_COLLECTING_DATA; 1153 break; 1154 case READ: 1155 case READ4: 1156 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1157 s->needed_bytes = get_addr_length(s); 1158 s->pos = 0; 1159 s->len = 0; 1160 s->state = STATE_COLLECTING_DATA; 1161 } else { 1162 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1163 "DIO or QIO mode\n", s->cmd_in_progress); 1164 } 1165 break; 1166 case DPP: 1167 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1168 s->needed_bytes = get_addr_length(s); 1169 s->pos = 0; 1170 s->len = 0; 1171 s->state = STATE_COLLECTING_DATA; 1172 } else { 1173 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1174 "QIO mode\n", s->cmd_in_progress); 1175 } 1176 break; 1177 case QPP: 1178 case QPP_4: 1179 case PP4_4: 1180 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1181 s->needed_bytes = get_addr_length(s); 1182 s->pos = 0; 1183 s->len = 0; 1184 s->state = STATE_COLLECTING_DATA; 1185 } else { 1186 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1187 "DIO mode\n", s->cmd_in_progress); 1188 } 1189 break; 1190 1191 case FAST_READ: 1192 case FAST_READ4: 1193 decode_fast_read_cmd(s); 1194 break; 1195 case DOR: 1196 case DOR4: 1197 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1198 decode_fast_read_cmd(s); 1199 } else { 1200 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1201 "QIO mode\n", s->cmd_in_progress); 1202 } 1203 break; 1204 case QOR: 1205 case QOR4: 1206 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1207 decode_fast_read_cmd(s); 1208 } else { 1209 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1210 "DIO mode\n", s->cmd_in_progress); 1211 } 1212 break; 1213 1214 case DIOR: 1215 case DIOR4: 1216 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1217 decode_dio_read_cmd(s); 1218 } else { 1219 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1220 "QIO mode\n", s->cmd_in_progress); 1221 } 1222 break; 1223 1224 case QIOR: 1225 case QIOR4: 1226 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1227 decode_qio_read_cmd(s); 1228 } else { 1229 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1230 "DIO mode\n", s->cmd_in_progress); 1231 } 1232 break; 1233 1234 case WRSR: 1235 /* 1236 * If WP# is low and status_register_write_disabled is high, 1237 * status register writes are disabled. 1238 * This is also called "hardware protected mode" (HPM). All other 1239 * combinations of the two states are called "software protected mode" 1240 * (SPM), and status register writes are permitted. 1241 */ 1242 if ((s->wp_level == 0 && s->status_register_write_disabled) 1243 || !s->write_enable) { 1244 qemu_log_mask(LOG_GUEST_ERROR, 1245 "M25P80: Status register write is disabled!\n"); 1246 break; 1247 } 1248 1249 switch (get_man(s)) { 1250 case MAN_SPANSION: 1251 s->needed_bytes = 2; 1252 s->state = STATE_COLLECTING_DATA; 1253 break; 1254 case MAN_MACRONIX: 1255 s->needed_bytes = 2; 1256 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1257 break; 1258 default: 1259 s->needed_bytes = 1; 1260 s->state = STATE_COLLECTING_DATA; 1261 } 1262 s->pos = 0; 1263 break; 1264 1265 case WRDI: 1266 s->write_enable = false; 1267 if (get_man(s) == MAN_SST) { 1268 s->aai_enable = false; 1269 } 1270 break; 1271 case WREN: 1272 s->write_enable = true; 1273 break; 1274 1275 case RDSR: 1276 s->data[0] = (!!s->write_enable) << 1; 1277 s->data[0] |= (!!s->status_register_write_disabled) << 7; 1278 s->data[0] |= (!!s->block_protect0) << 2; 1279 s->data[0] |= (!!s->block_protect1) << 3; 1280 s->data[0] |= (!!s->block_protect2) << 4; 1281 if (s->pi->flags & HAS_SR_TB) { 1282 s->data[0] |= (!!s->top_bottom_bit) << 5; 1283 } 1284 if (s->pi->flags & HAS_SR_BP3_BIT6) { 1285 s->data[0] |= (!!s->block_protect3) << 6; 1286 } 1287 1288 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) { 1289 s->data[0] |= (!!s->quad_enable) << 6; 1290 } 1291 if (get_man(s) == MAN_SST) { 1292 s->data[0] |= (!!s->aai_enable) << 6; 1293 } 1294 1295 s->pos = 0; 1296 s->len = 1; 1297 s->data_read_loop = true; 1298 s->state = STATE_READING_DATA; 1299 break; 1300 1301 case READ_FSR: 1302 s->data[0] = FSR_FLASH_READY; 1303 if (s->four_bytes_address_mode) { 1304 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 1305 } 1306 s->pos = 0; 1307 s->len = 1; 1308 s->data_read_loop = true; 1309 s->state = STATE_READING_DATA; 1310 break; 1311 1312 case JEDEC_READ: 1313 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1314 trace_m25p80_populated_jedec(s); 1315 for (i = 0; i < s->pi->id_len; i++) { 1316 s->data[i] = s->pi->id[i]; 1317 } 1318 for (; i < SPI_NOR_MAX_ID_LEN; i++) { 1319 s->data[i] = 0; 1320 } 1321 1322 s->len = SPI_NOR_MAX_ID_LEN; 1323 s->pos = 0; 1324 s->state = STATE_READING_DATA; 1325 } else { 1326 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read " 1327 "in DIO or QIO mode\n"); 1328 } 1329 break; 1330 1331 case RDCR: 1332 s->data[0] = s->volatile_cfg & 0xFF; 1333 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 1334 s->pos = 0; 1335 s->len = 1; 1336 s->state = STATE_READING_DATA; 1337 break; 1338 1339 case BULK_ERASE_60: 1340 case BULK_ERASE: 1341 if (s->write_enable) { 1342 trace_m25p80_chip_erase(s); 1343 flash_erase(s, 0, BULK_ERASE); 1344 } else { 1345 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 1346 "protect!\n"); 1347 } 1348 break; 1349 case NOP: 1350 break; 1351 case EN_4BYTE_ADDR: 1352 s->four_bytes_address_mode = true; 1353 break; 1354 case EX_4BYTE_ADDR: 1355 s->four_bytes_address_mode = false; 1356 break; 1357 case BRRD: 1358 case EXTEND_ADDR_READ: 1359 s->data[0] = s->ear; 1360 s->pos = 0; 1361 s->len = 1; 1362 s->state = STATE_READING_DATA; 1363 break; 1364 case BRWR: 1365 case EXTEND_ADDR_WRITE: 1366 if (s->write_enable) { 1367 s->needed_bytes = 1; 1368 s->pos = 0; 1369 s->len = 0; 1370 s->state = STATE_COLLECTING_DATA; 1371 } 1372 break; 1373 case RNVCR: 1374 s->data[0] = s->nonvolatile_cfg & 0xFF; 1375 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1376 s->pos = 0; 1377 s->len = 2; 1378 s->state = STATE_READING_DATA; 1379 break; 1380 case WNVCR: 1381 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1382 s->needed_bytes = 2; 1383 s->pos = 0; 1384 s->len = 0; 1385 s->state = STATE_COLLECTING_DATA; 1386 } 1387 break; 1388 case RVCR: 1389 s->data[0] = s->volatile_cfg & 0xFF; 1390 s->pos = 0; 1391 s->len = 1; 1392 s->state = STATE_READING_DATA; 1393 break; 1394 case WVCR: 1395 if (s->write_enable) { 1396 s->needed_bytes = 1; 1397 s->pos = 0; 1398 s->len = 0; 1399 s->state = STATE_COLLECTING_DATA; 1400 } 1401 break; 1402 case REVCR: 1403 s->data[0] = s->enh_volatile_cfg & 0xFF; 1404 s->pos = 0; 1405 s->len = 1; 1406 s->state = STATE_READING_DATA; 1407 break; 1408 case WEVCR: 1409 if (s->write_enable) { 1410 s->needed_bytes = 1; 1411 s->pos = 0; 1412 s->len = 0; 1413 s->state = STATE_COLLECTING_DATA; 1414 } 1415 break; 1416 case RESET_ENABLE: 1417 s->reset_enable = true; 1418 break; 1419 case RESET_MEMORY: 1420 if (s->reset_enable) { 1421 reset_memory(s); 1422 } 1423 break; 1424 case RDCR_EQIO: 1425 switch (get_man(s)) { 1426 case MAN_SPANSION: 1427 s->data[0] = (!!s->quad_enable) << 1; 1428 s->pos = 0; 1429 s->len = 1; 1430 s->state = STATE_READING_DATA; 1431 break; 1432 case MAN_MACRONIX: 1433 s->quad_enable = true; 1434 break; 1435 default: 1436 break; 1437 } 1438 break; 1439 case RSTQIO: 1440 s->quad_enable = false; 1441 break; 1442 case AAI_WP: 1443 if (get_man(s) == MAN_SST) { 1444 if (s->write_enable) { 1445 if (s->aai_enable) { 1446 s->state = STATE_PAGE_PROGRAM; 1447 } else { 1448 s->aai_enable = true; 1449 s->needed_bytes = get_addr_length(s); 1450 s->state = STATE_COLLECTING_DATA; 1451 } 1452 } else { 1453 qemu_log_mask(LOG_GUEST_ERROR, 1454 "M25P80: AAI_WP with write protect\n"); 1455 } 1456 } else { 1457 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1458 } 1459 break; 1460 case RDSFDP: 1461 if (s->pi->sfdp_read) { 1462 s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */ 1463 s->pos = 0; 1464 s->len = 0; 1465 s->state = STATE_COLLECTING_DATA; 1466 break; 1467 } 1468 /* Fallthrough */ 1469 1470 default: 1471 s->pos = 0; 1472 s->len = 1; 1473 s->state = STATE_READING_DATA; 1474 s->data_read_loop = true; 1475 s->data[0] = 0; 1476 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1477 break; 1478 } 1479 } 1480 1481 static int m25p80_cs(SSIPeripheral *ss, bool select) 1482 { 1483 Flash *s = M25P80(ss); 1484 1485 if (select) { 1486 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1487 complete_collecting_data(s); 1488 } 1489 s->len = 0; 1490 s->pos = 0; 1491 s->state = STATE_IDLE; 1492 flash_sync_dirty(s, -1); 1493 s->data_read_loop = false; 1494 } 1495 1496 trace_m25p80_select(s, select ? "de" : ""); 1497 1498 return 0; 1499 } 1500 1501 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) 1502 { 1503 Flash *s = M25P80(ss); 1504 uint32_t r = 0; 1505 1506 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, 1507 s->cur_addr, (uint8_t)tx); 1508 1509 switch (s->state) { 1510 1511 case STATE_PAGE_PROGRAM: 1512 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); 1513 flash_write8(s, s->cur_addr, (uint8_t)tx); 1514 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1515 1516 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) { 1517 /* 1518 * There is no wrap mode during AAI programming once the highest 1519 * unprotected memory address is reached. The Write-Enable-Latch 1520 * bit is automatically reset, and AAI programming mode aborts. 1521 */ 1522 s->write_enable = false; 1523 s->aai_enable = false; 1524 } 1525 1526 break; 1527 1528 case STATE_READ: 1529 r = s->storage[s->cur_addr]; 1530 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); 1531 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1532 break; 1533 1534 case STATE_COLLECTING_DATA: 1535 case STATE_COLLECTING_VAR_LEN_DATA: 1536 1537 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1538 qemu_log_mask(LOG_GUEST_ERROR, 1539 "M25P80: Write overrun internal data buffer. " 1540 "SPI controller (QEMU emulator or guest driver) " 1541 "is misbehaving\n"); 1542 s->len = s->pos = 0; 1543 s->state = STATE_IDLE; 1544 break; 1545 } 1546 1547 s->data[s->len] = (uint8_t)tx; 1548 s->len++; 1549 1550 if (s->len == s->needed_bytes) { 1551 complete_collecting_data(s); 1552 } 1553 break; 1554 1555 case STATE_READING_DATA: 1556 1557 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1558 qemu_log_mask(LOG_GUEST_ERROR, 1559 "M25P80: Read overrun internal data buffer. " 1560 "SPI controller (QEMU emulator or guest driver) " 1561 "is misbehaving\n"); 1562 s->len = s->pos = 0; 1563 s->state = STATE_IDLE; 1564 break; 1565 } 1566 1567 r = s->data[s->pos]; 1568 trace_m25p80_read_data(s, s->pos, (uint8_t)r); 1569 s->pos++; 1570 if (s->pos == s->len) { 1571 s->pos = 0; 1572 if (!s->data_read_loop) { 1573 s->state = STATE_IDLE; 1574 } 1575 } 1576 break; 1577 case STATE_READING_SFDP: 1578 assert(s->pi->sfdp_read); 1579 r = s->pi->sfdp_read(s->cur_addr); 1580 trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r); 1581 s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1); 1582 break; 1583 1584 default: 1585 case STATE_IDLE: 1586 decode_new_cmd(s, (uint8_t)tx); 1587 break; 1588 } 1589 1590 return r; 1591 } 1592 1593 static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level) 1594 { 1595 Flash *s = M25P80(opaque); 1596 /* WP# is just a single pin. */ 1597 assert(n == 0); 1598 s->wp_level = !!level; 1599 } 1600 1601 static void m25p80_realize(SSIPeripheral *ss, Error **errp) 1602 { 1603 Flash *s = M25P80(ss); 1604 M25P80Class *mc = M25P80_GET_CLASS(s); 1605 int ret; 1606 1607 s->pi = mc->pi; 1608 1609 s->size = s->pi->sector_size * s->pi->n_sectors; 1610 s->dirty_page = -1; 1611 1612 if (s->blk) { 1613 uint64_t perm = BLK_PERM_CONSISTENT_READ | 1614 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0); 1615 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); 1616 if (ret < 0) { 1617 return; 1618 } 1619 1620 trace_m25p80_binding(s); 1621 s->storage = blk_blockalign(s->blk, s->size); 1622 1623 if (!blk_check_size_and_read_all(s->blk, DEVICE(s), 1624 s->storage, s->size, errp)) { 1625 return; 1626 } 1627 } else { 1628 trace_m25p80_binding_no_bdrv(s); 1629 s->storage = blk_blockalign(NULL, s->size); 1630 memset(s->storage, 0xFF, s->size); 1631 } 1632 1633 qdev_init_gpio_in_named(DEVICE(s), 1634 m25p80_write_protect_pin_irq_handler, "WP#", 1); 1635 } 1636 1637 static void m25p80_reset(DeviceState *d) 1638 { 1639 Flash *s = M25P80(d); 1640 1641 s->wp_level = true; 1642 s->status_register_write_disabled = false; 1643 s->block_protect0 = false; 1644 s->block_protect1 = false; 1645 s->block_protect2 = false; 1646 s->block_protect3 = false; 1647 s->top_bottom_bit = false; 1648 1649 reset_memory(s); 1650 } 1651 1652 static int m25p80_pre_save(void *opaque) 1653 { 1654 flash_sync_dirty((Flash *)opaque, -1); 1655 1656 return 0; 1657 } 1658 1659 static Property m25p80_properties[] = { 1660 /* This is default value for Micron flash */ 1661 DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false), 1662 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1663 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1664 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1665 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1666 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1667 DEFINE_PROP_DRIVE("drive", Flash, blk), 1668 DEFINE_PROP_END_OF_LIST(), 1669 }; 1670 1671 static int m25p80_pre_load(void *opaque) 1672 { 1673 Flash *s = (Flash *)opaque; 1674 1675 s->data_read_loop = false; 1676 return 0; 1677 } 1678 1679 static bool m25p80_data_read_loop_needed(void *opaque) 1680 { 1681 Flash *s = (Flash *)opaque; 1682 1683 return s->data_read_loop; 1684 } 1685 1686 static const VMStateDescription vmstate_m25p80_data_read_loop = { 1687 .name = "m25p80/data_read_loop", 1688 .version_id = 1, 1689 .minimum_version_id = 1, 1690 .needed = m25p80_data_read_loop_needed, 1691 .fields = (const VMStateField[]) { 1692 VMSTATE_BOOL(data_read_loop, Flash), 1693 VMSTATE_END_OF_LIST() 1694 } 1695 }; 1696 1697 static bool m25p80_aai_enable_needed(void *opaque) 1698 { 1699 Flash *s = (Flash *)opaque; 1700 1701 return s->aai_enable; 1702 } 1703 1704 static const VMStateDescription vmstate_m25p80_aai_enable = { 1705 .name = "m25p80/aai_enable", 1706 .version_id = 1, 1707 .minimum_version_id = 1, 1708 .needed = m25p80_aai_enable_needed, 1709 .fields = (const VMStateField[]) { 1710 VMSTATE_BOOL(aai_enable, Flash), 1711 VMSTATE_END_OF_LIST() 1712 } 1713 }; 1714 1715 static bool m25p80_wp_level_srwd_needed(void *opaque) 1716 { 1717 Flash *s = (Flash *)opaque; 1718 1719 return !s->wp_level || s->status_register_write_disabled; 1720 } 1721 1722 static const VMStateDescription vmstate_m25p80_write_protect = { 1723 .name = "m25p80/write_protect", 1724 .version_id = 1, 1725 .minimum_version_id = 1, 1726 .needed = m25p80_wp_level_srwd_needed, 1727 .fields = (const VMStateField[]) { 1728 VMSTATE_BOOL(wp_level, Flash), 1729 VMSTATE_BOOL(status_register_write_disabled, Flash), 1730 VMSTATE_END_OF_LIST() 1731 } 1732 }; 1733 1734 static bool m25p80_block_protect_needed(void *opaque) 1735 { 1736 Flash *s = (Flash *)opaque; 1737 1738 return s->block_protect0 || 1739 s->block_protect1 || 1740 s->block_protect2 || 1741 s->block_protect3 || 1742 s->top_bottom_bit; 1743 } 1744 1745 static const VMStateDescription vmstate_m25p80_block_protect = { 1746 .name = "m25p80/block_protect", 1747 .version_id = 1, 1748 .minimum_version_id = 1, 1749 .needed = m25p80_block_protect_needed, 1750 .fields = (const VMStateField[]) { 1751 VMSTATE_BOOL(block_protect0, Flash), 1752 VMSTATE_BOOL(block_protect1, Flash), 1753 VMSTATE_BOOL(block_protect2, Flash), 1754 VMSTATE_BOOL(block_protect3, Flash), 1755 VMSTATE_BOOL(top_bottom_bit, Flash), 1756 VMSTATE_END_OF_LIST() 1757 } 1758 }; 1759 1760 static const VMStateDescription vmstate_m25p80 = { 1761 .name = "m25p80", 1762 .version_id = 0, 1763 .minimum_version_id = 0, 1764 .pre_save = m25p80_pre_save, 1765 .pre_load = m25p80_pre_load, 1766 .fields = (const VMStateField[]) { 1767 VMSTATE_UINT8(state, Flash), 1768 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1769 VMSTATE_UINT32(len, Flash), 1770 VMSTATE_UINT32(pos, Flash), 1771 VMSTATE_UINT8(needed_bytes, Flash), 1772 VMSTATE_UINT8(cmd_in_progress, Flash), 1773 VMSTATE_UINT32(cur_addr, Flash), 1774 VMSTATE_BOOL(write_enable, Flash), 1775 VMSTATE_BOOL(reset_enable, Flash), 1776 VMSTATE_UINT8(ear, Flash), 1777 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1778 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1779 VMSTATE_UINT32(volatile_cfg, Flash), 1780 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1781 VMSTATE_BOOL(quad_enable, Flash), 1782 VMSTATE_UINT8(spansion_cr1nv, Flash), 1783 VMSTATE_UINT8(spansion_cr2nv, Flash), 1784 VMSTATE_UINT8(spansion_cr3nv, Flash), 1785 VMSTATE_UINT8(spansion_cr4nv, Flash), 1786 VMSTATE_END_OF_LIST() 1787 }, 1788 .subsections = (const VMStateDescription * const []) { 1789 &vmstate_m25p80_data_read_loop, 1790 &vmstate_m25p80_aai_enable, 1791 &vmstate_m25p80_write_protect, 1792 &vmstate_m25p80_block_protect, 1793 NULL 1794 } 1795 }; 1796 1797 static void m25p80_class_init(ObjectClass *klass, void *data) 1798 { 1799 DeviceClass *dc = DEVICE_CLASS(klass); 1800 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); 1801 M25P80Class *mc = M25P80_CLASS(klass); 1802 1803 k->realize = m25p80_realize; 1804 k->transfer = m25p80_transfer8; 1805 k->set_cs = m25p80_cs; 1806 k->cs_polarity = SSI_CS_LOW; 1807 dc->vmsd = &vmstate_m25p80; 1808 device_class_set_props(dc, m25p80_properties); 1809 dc->reset = m25p80_reset; 1810 mc->pi = data; 1811 } 1812 1813 static const TypeInfo m25p80_info = { 1814 .name = TYPE_M25P80, 1815 .parent = TYPE_SSI_PERIPHERAL, 1816 .instance_size = sizeof(Flash), 1817 .class_size = sizeof(M25P80Class), 1818 .abstract = true, 1819 }; 1820 1821 static void m25p80_register_types(void) 1822 { 1823 int i; 1824 1825 type_register_static(&m25p80_info); 1826 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1827 TypeInfo ti = { 1828 .name = known_devices[i].part_name, 1829 .parent = TYPE_M25P80, 1830 .class_init = m25p80_class_init, 1831 .class_data = (void *)&known_devices[i], 1832 }; 1833 type_register(&ti); 1834 } 1835 } 1836 1837 type_init(m25p80_register_types) 1838 1839 BlockBackend *m25p80_get_blk(DeviceState *dev) 1840 { 1841 return M25P80(dev)->blk; 1842 } 1843