1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/block/block.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/qdev-properties-system.h" 30 #include "hw/ssi/ssi.h" 31 #include "migration/vmstate.h" 32 #include "qemu/bitops.h" 33 #include "qemu/log.h" 34 #include "qemu/module.h" 35 #include "qemu/error-report.h" 36 #include "qapi/error.h" 37 #include "trace.h" 38 #include "qom/object.h" 39 #include "m25p80_sfdp.h" 40 41 /* 16 MiB max in 3 byte address mode */ 42 #define MAX_3BYTES_SIZE 0x1000000 43 #define SPI_NOR_MAX_ID_LEN 6 44 45 /* Fields for FlashPartInfo->flags */ 46 enum spi_flash_option_flags { 47 ER_4K = BIT(0), 48 ER_32K = BIT(1), 49 EEPROM = BIT(2), 50 HAS_SR_TB = BIT(3), 51 HAS_SR_BP3_BIT6 = BIT(4), 52 }; 53 54 typedef struct FlashPartInfo { 55 const char *part_name; 56 /* 57 * This array stores the ID bytes. 58 * The first three bytes are the JEDIC ID. 59 * JEDEC ID zero means "no ID" (mostly older chips). 60 */ 61 uint8_t id[SPI_NOR_MAX_ID_LEN]; 62 uint8_t id_len; 63 /* there is confusion between manufacturers as to what a sector is. In this 64 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 65 * command (opcode 0xd8). 66 */ 67 uint32_t sector_size; 68 uint32_t n_sectors; 69 uint32_t page_size; 70 uint16_t flags; 71 /* 72 * Big sized spi nor are often stacked devices, thus sometime 73 * replace chip erase with die erase. 74 * This field inform how many die is in the chip. 75 */ 76 uint8_t die_cnt; 77 uint8_t (*sfdp_read)(uint32_t sfdp_addr); 78 } FlashPartInfo; 79 80 /* adapted from linux */ 81 /* Used when the "_ext_id" is two bytes at most */ 82 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 83 .part_name = _part_name,\ 84 .id = {\ 85 ((_jedec_id) >> 16) & 0xff,\ 86 ((_jedec_id) >> 8) & 0xff,\ 87 (_jedec_id) & 0xff,\ 88 ((_ext_id) >> 8) & 0xff,\ 89 (_ext_id) & 0xff,\ 90 },\ 91 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 92 .sector_size = (_sector_size),\ 93 .n_sectors = (_n_sectors),\ 94 .page_size = 256,\ 95 .flags = (_flags),\ 96 .die_cnt = 0 97 98 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 99 .part_name = _part_name,\ 100 .id = {\ 101 ((_jedec_id) >> 16) & 0xff,\ 102 ((_jedec_id) >> 8) & 0xff,\ 103 (_jedec_id) & 0xff,\ 104 ((_ext_id) >> 16) & 0xff,\ 105 ((_ext_id) >> 8) & 0xff,\ 106 (_ext_id) & 0xff,\ 107 },\ 108 .id_len = 6,\ 109 .sector_size = (_sector_size),\ 110 .n_sectors = (_n_sectors),\ 111 .page_size = 256,\ 112 .flags = (_flags),\ 113 .die_cnt = 0 114 115 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ 116 _flags, _die_cnt)\ 117 .part_name = _part_name,\ 118 .id = {\ 119 ((_jedec_id) >> 16) & 0xff,\ 120 ((_jedec_id) >> 8) & 0xff,\ 121 (_jedec_id) & 0xff,\ 122 ((_ext_id) >> 8) & 0xff,\ 123 (_ext_id) & 0xff,\ 124 },\ 125 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 126 .sector_size = (_sector_size),\ 127 .n_sectors = (_n_sectors),\ 128 .page_size = 256,\ 129 .flags = (_flags),\ 130 .die_cnt = _die_cnt 131 132 #define JEDEC_NUMONYX 0x20 133 #define JEDEC_WINBOND 0xEF 134 #define JEDEC_SPANSION 0x01 135 136 /* Numonyx (Micron) Configuration register macros */ 137 #define VCFG_DUMMY 0x1 138 #define VCFG_WRAP_SEQUENTIAL 0x2 139 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 140 #define NVCFG_XIP_MODE_MASK (7 << 9) 141 #define VCFG_XIP_MODE_DISABLED (1 << 3) 142 #define CFG_DUMMY_CLK_LEN 4 143 #define NVCFG_DUMMY_CLK_POS 12 144 #define VCFG_DUMMY_CLK_POS 4 145 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 146 #define EVCFG_VPP_ACCELERATOR (1 << 3) 147 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 148 #define NVCFG_DUAL_IO_MASK (1 << 2) 149 #define EVCFG_DUAL_IO_DISABLED (1 << 6) 150 #define NVCFG_QUAD_IO_MASK (1 << 3) 151 #define EVCFG_QUAD_IO_DISABLED (1 << 7) 152 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 153 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 154 155 /* Numonyx (Micron) Flag Status Register macros */ 156 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 157 #define FSR_FLASH_READY (1 << 7) 158 159 /* Spansion configuration registers macros. */ 160 #define SPANSION_QUAD_CFG_POS 0 161 #define SPANSION_QUAD_CFG_LEN 1 162 #define SPANSION_DUMMY_CLK_POS 0 163 #define SPANSION_DUMMY_CLK_LEN 4 164 #define SPANSION_ADDR_LEN_POS 7 165 #define SPANSION_ADDR_LEN_LEN 1 166 167 /* 168 * Spansion read mode command length in bytes, 169 * the mode is currently not supported. 170 */ 171 172 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 173 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 174 175 static const FlashPartInfo known_devices[] = { 176 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 177 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 178 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 179 180 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 181 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 182 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 183 184 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 185 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 186 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 187 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 188 189 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 190 191 /* Atmel EEPROMS - it is assumed, that don't care bit in command 192 * is set to 0. Block protection is not supported. 193 */ 194 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 195 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 196 197 /* EON -- en25xxx */ 198 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 199 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 200 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 201 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 202 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 203 204 /* GigaDevice */ 205 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 206 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 207 208 /* Intel/Numonyx -- xxxs33b */ 209 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 210 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 211 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 212 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 213 214 /* ISSI */ 215 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, 216 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, 217 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, 218 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, 219 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, 220 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, 221 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) }, 222 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) }, 223 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) }, 224 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) }, 225 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K), 226 .sfdp_read = m25p80_sfdp_is25wp256 }, 227 228 /* Macronix */ 229 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 230 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 231 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 232 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 233 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 234 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 235 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 236 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 237 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 238 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e }, 239 { INFO6("mx25l25635f", 0xc22019, 0xc22019, 64 << 10, 512, 240 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f }, 241 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 242 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 243 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 244 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 245 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K), 246 .sfdp_read = m25p80_sfdp_mx66l1g45g }, 247 248 /* Micron */ 249 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 250 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 251 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 252 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 253 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 254 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 255 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 256 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K), 257 .sfdp_read = m25p80_sfdp_n25q256a }, 258 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, 259 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 260 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 261 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, 262 ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB), 263 .sfdp_read = m25p80_sfdp_n25q256a }, 264 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 265 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, 266 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, 267 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024, 268 ER_4K | ER_32K, 2) }, 269 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 270 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 271 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 272 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 273 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 274 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 275 276 /* Spansion -- single (large) sector size only, at least 277 * for the chips listed here (without boot sectors). 278 */ 279 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 280 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 281 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 282 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 283 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 284 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 285 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 286 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 287 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 288 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 289 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 290 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 291 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 292 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 293 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 294 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 295 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 296 297 /* Spansion -- boot sectors support */ 298 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 299 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 300 301 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 302 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 303 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 304 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 305 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 306 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 307 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 308 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 309 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 310 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 311 312 /* ST Microelectronics -- newer production may have feature updates */ 313 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 314 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 315 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 316 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 317 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 318 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 319 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 320 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 321 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 322 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 323 324 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 325 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 326 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 327 328 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 329 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 330 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 331 332 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 333 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 334 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 335 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 336 337 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 338 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 339 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 340 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 341 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 342 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 343 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 344 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 345 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 346 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 347 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 348 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 349 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 350 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K), 351 .sfdp_read = m25p80_sfdp_w25q256 }, 352 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K), 353 .sfdp_read = m25p80_sfdp_w25q512jv }, 354 { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K), 355 .sfdp_read = m25p80_sfdp_w25q01jvq }, 356 }; 357 358 typedef enum { 359 NOP = 0, 360 WRSR = 0x1, 361 WRDI = 0x4, 362 RDSR = 0x5, 363 WREN = 0x6, 364 BRRD = 0x16, 365 BRWR = 0x17, 366 JEDEC_READ = 0x9f, 367 BULK_ERASE_60 = 0x60, 368 BULK_ERASE = 0xc7, 369 READ_FSR = 0x70, 370 RDCR = 0x15, 371 RDSFDP = 0x5a, 372 373 READ = 0x03, 374 READ4 = 0x13, 375 FAST_READ = 0x0b, 376 FAST_READ4 = 0x0c, 377 DOR = 0x3b, 378 DOR4 = 0x3c, 379 QOR = 0x6b, 380 QOR4 = 0x6c, 381 DIOR = 0xbb, 382 DIOR4 = 0xbc, 383 QIOR = 0xeb, 384 QIOR4 = 0xec, 385 386 PP = 0x02, 387 PP4 = 0x12, 388 PP4_4 = 0x3e, 389 DPP = 0xa2, 390 QPP = 0x32, 391 QPP_4 = 0x34, 392 RDID_90 = 0x90, 393 RDID_AB = 0xab, 394 AAI_WP = 0xad, 395 396 ERASE_4K = 0x20, 397 ERASE4_4K = 0x21, 398 ERASE_32K = 0x52, 399 ERASE4_32K = 0x5c, 400 ERASE_SECTOR = 0xd8, 401 ERASE4_SECTOR = 0xdc, 402 403 EN_4BYTE_ADDR = 0xB7, 404 EX_4BYTE_ADDR = 0xE9, 405 406 EXTEND_ADDR_READ = 0xC8, 407 EXTEND_ADDR_WRITE = 0xC5, 408 409 RESET_ENABLE = 0x66, 410 RESET_MEMORY = 0x99, 411 412 /* 413 * Micron: 0x35 - enable QPI 414 * Spansion: 0x35 - read control register 415 */ 416 RDCR_EQIO = 0x35, 417 RSTQIO = 0xf5, 418 419 RNVCR = 0xB5, 420 WNVCR = 0xB1, 421 422 RVCR = 0x85, 423 WVCR = 0x81, 424 425 REVCR = 0x65, 426 WEVCR = 0x61, 427 428 DIE_ERASE = 0xC4, 429 } FlashCMD; 430 431 typedef enum { 432 STATE_IDLE, 433 STATE_PAGE_PROGRAM, 434 STATE_READ, 435 STATE_COLLECTING_DATA, 436 STATE_COLLECTING_VAR_LEN_DATA, 437 STATE_READING_DATA, 438 STATE_READING_SFDP, 439 } CMDState; 440 441 typedef enum { 442 MAN_SPANSION, 443 MAN_MACRONIX, 444 MAN_NUMONYX, 445 MAN_WINBOND, 446 MAN_SST, 447 MAN_ISSI, 448 MAN_GENERIC, 449 } Manufacturer; 450 451 typedef enum { 452 MODE_STD = 0, 453 MODE_DIO = 1, 454 MODE_QIO = 2 455 } SPIMode; 456 457 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 458 459 struct Flash { 460 SSIPeripheral parent_obj; 461 462 BlockBackend *blk; 463 464 uint8_t *storage; 465 uint32_t size; 466 int page_size; 467 468 uint8_t state; 469 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 470 uint32_t len; 471 uint32_t pos; 472 bool data_read_loop; 473 uint8_t needed_bytes; 474 uint8_t cmd_in_progress; 475 uint32_t cur_addr; 476 uint32_t nonvolatile_cfg; 477 /* Configuration register for Macronix */ 478 uint32_t volatile_cfg; 479 uint32_t enh_volatile_cfg; 480 /* Spansion cfg registers. */ 481 uint8_t spansion_cr1nv; 482 uint8_t spansion_cr2nv; 483 uint8_t spansion_cr3nv; 484 uint8_t spansion_cr4nv; 485 uint8_t spansion_cr1v; 486 uint8_t spansion_cr2v; 487 uint8_t spansion_cr3v; 488 uint8_t spansion_cr4v; 489 bool wp_level; 490 bool write_enable; 491 bool four_bytes_address_mode; 492 bool reset_enable; 493 bool quad_enable; 494 bool aai_enable; 495 bool block_protect0; 496 bool block_protect1; 497 bool block_protect2; 498 bool block_protect3; 499 bool top_bottom_bit; 500 bool status_register_write_disabled; 501 uint8_t ear; 502 503 int64_t dirty_page; 504 505 const FlashPartInfo *pi; 506 507 }; 508 509 struct M25P80Class { 510 SSIPeripheralClass parent_class; 511 FlashPartInfo *pi; 512 }; 513 514 #define TYPE_M25P80 "m25p80-generic" 515 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) 516 517 static inline Manufacturer get_man(Flash *s) 518 { 519 switch (s->pi->id[0]) { 520 case 0x20: 521 return MAN_NUMONYX; 522 case 0xEF: 523 return MAN_WINBOND; 524 case 0x01: 525 return MAN_SPANSION; 526 case 0xC2: 527 return MAN_MACRONIX; 528 case 0xBF: 529 return MAN_SST; 530 case 0x9D: 531 return MAN_ISSI; 532 default: 533 return MAN_GENERIC; 534 } 535 } 536 537 static void blk_sync_complete(void *opaque, int ret) 538 { 539 QEMUIOVector *iov = opaque; 540 541 qemu_iovec_destroy(iov); 542 g_free(iov); 543 544 /* do nothing. Masters do not directly interact with the backing store, 545 * only the working copy so no mutexing required. 546 */ 547 } 548 549 static void flash_sync_page(Flash *s, int page) 550 { 551 QEMUIOVector *iov; 552 553 if (!s->blk || !blk_is_writable(s->blk)) { 554 return; 555 } 556 557 iov = g_new(QEMUIOVector, 1); 558 qemu_iovec_init(iov, 1); 559 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 560 s->pi->page_size); 561 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 562 blk_sync_complete, iov); 563 } 564 565 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 566 { 567 QEMUIOVector *iov; 568 569 if (!s->blk || !blk_is_writable(s->blk)) { 570 return; 571 } 572 573 assert(!(len % BDRV_SECTOR_SIZE)); 574 iov = g_new(QEMUIOVector, 1); 575 qemu_iovec_init(iov, 1); 576 qemu_iovec_add(iov, s->storage + off, len); 577 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 578 } 579 580 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 581 { 582 uint32_t len; 583 uint8_t capa_to_assert = 0; 584 585 switch (cmd) { 586 case ERASE_4K: 587 case ERASE4_4K: 588 len = 4 * KiB; 589 capa_to_assert = ER_4K; 590 break; 591 case ERASE_32K: 592 case ERASE4_32K: 593 len = 32 * KiB; 594 capa_to_assert = ER_32K; 595 break; 596 case ERASE_SECTOR: 597 case ERASE4_SECTOR: 598 len = s->pi->sector_size; 599 break; 600 case BULK_ERASE: 601 len = s->size; 602 break; 603 case DIE_ERASE: 604 if (s->pi->die_cnt) { 605 len = s->size / s->pi->die_cnt; 606 offset = offset & (~(len - 1)); 607 } else { 608 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" 609 " by device\n"); 610 return; 611 } 612 break; 613 default: 614 abort(); 615 } 616 617 trace_m25p80_flash_erase(s, offset, len); 618 619 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 620 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 621 " device\n", len); 622 } 623 624 if (!s->write_enable) { 625 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 626 return; 627 } 628 memset(s->storage + offset, 0xff, len); 629 flash_sync_area(s, offset, len); 630 } 631 632 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 633 { 634 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 635 flash_sync_page(s, s->dirty_page); 636 s->dirty_page = newpage; 637 } 638 } 639 640 static inline 641 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 642 { 643 uint32_t page = addr / s->pi->page_size; 644 uint8_t prev = s->storage[s->cur_addr]; 645 uint32_t block_protect_value = (s->block_protect3 << 3) | 646 (s->block_protect2 << 2) | 647 (s->block_protect1 << 1) | 648 (s->block_protect0 << 0); 649 650 if (!s->write_enable) { 651 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 652 return; 653 } 654 655 if (block_protect_value > 0) { 656 uint32_t num_protected_sectors = 1 << (block_protect_value - 1); 657 uint32_t sector = addr / s->pi->sector_size; 658 659 /* top_bottom_bit == 0 means TOP */ 660 if (!s->top_bottom_bit) { 661 if (s->pi->n_sectors <= sector + num_protected_sectors) { 662 qemu_log_mask(LOG_GUEST_ERROR, 663 "M25P80: write with write protect!\n"); 664 return; 665 } 666 } else { 667 if (sector < num_protected_sectors) { 668 qemu_log_mask(LOG_GUEST_ERROR, 669 "M25P80: write with write protect!\n"); 670 return; 671 } 672 } 673 } 674 675 if ((prev ^ data) & data) { 676 trace_m25p80_programming_zero_to_one(s, addr, prev, data); 677 } 678 679 if (s->pi->flags & EEPROM) { 680 s->storage[s->cur_addr] = data; 681 } else { 682 s->storage[s->cur_addr] &= data; 683 } 684 685 flash_sync_dirty(s, page); 686 s->dirty_page = page; 687 } 688 689 static inline int get_addr_length(Flash *s) 690 { 691 /* check if eeprom is in use */ 692 if (s->pi->flags == EEPROM) { 693 return 2; 694 } 695 696 switch (s->cmd_in_progress) { 697 case RDSFDP: 698 return 3; 699 case PP4: 700 case PP4_4: 701 case QPP_4: 702 case READ4: 703 case QIOR4: 704 case ERASE4_4K: 705 case ERASE4_32K: 706 case ERASE4_SECTOR: 707 case FAST_READ4: 708 case DOR4: 709 case QOR4: 710 case DIOR4: 711 return 4; 712 default: 713 return s->four_bytes_address_mode ? 4 : 3; 714 } 715 } 716 717 static void complete_collecting_data(Flash *s) 718 { 719 int i, n; 720 721 n = get_addr_length(s); 722 s->cur_addr = (n == 3 ? s->ear : 0); 723 for (i = 0; i < n; ++i) { 724 s->cur_addr <<= 8; 725 s->cur_addr |= s->data[i]; 726 } 727 728 s->cur_addr &= s->size - 1; 729 730 s->state = STATE_IDLE; 731 732 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, 733 s->cur_addr); 734 735 switch (s->cmd_in_progress) { 736 case DPP: 737 case QPP: 738 case QPP_4: 739 case PP: 740 case PP4: 741 case PP4_4: 742 s->state = STATE_PAGE_PROGRAM; 743 break; 744 case AAI_WP: 745 /* AAI programming starts from the even address */ 746 s->cur_addr &= ~BIT(0); 747 s->state = STATE_PAGE_PROGRAM; 748 break; 749 case READ: 750 case READ4: 751 case FAST_READ: 752 case FAST_READ4: 753 case DOR: 754 case DOR4: 755 case QOR: 756 case QOR4: 757 case DIOR: 758 case DIOR4: 759 case QIOR: 760 case QIOR4: 761 s->state = STATE_READ; 762 break; 763 case ERASE_4K: 764 case ERASE4_4K: 765 case ERASE_32K: 766 case ERASE4_32K: 767 case ERASE_SECTOR: 768 case ERASE4_SECTOR: 769 case DIE_ERASE: 770 flash_erase(s, s->cur_addr, s->cmd_in_progress); 771 break; 772 case WRSR: 773 s->status_register_write_disabled = extract32(s->data[0], 7, 1); 774 s->block_protect0 = extract32(s->data[0], 2, 1); 775 s->block_protect1 = extract32(s->data[0], 3, 1); 776 s->block_protect2 = extract32(s->data[0], 4, 1); 777 if (s->pi->flags & HAS_SR_TB) { 778 s->top_bottom_bit = extract32(s->data[0], 5, 1); 779 } 780 if (s->pi->flags & HAS_SR_BP3_BIT6) { 781 s->block_protect3 = extract32(s->data[0], 6, 1); 782 } 783 784 switch (get_man(s)) { 785 case MAN_SPANSION: 786 s->quad_enable = !!(s->data[1] & 0x02); 787 break; 788 case MAN_ISSI: 789 s->quad_enable = extract32(s->data[0], 6, 1); 790 break; 791 case MAN_MACRONIX: 792 s->quad_enable = extract32(s->data[0], 6, 1); 793 if (s->len > 1) { 794 s->volatile_cfg = s->data[1]; 795 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 796 } 797 break; 798 default: 799 break; 800 } 801 if (s->write_enable) { 802 s->write_enable = false; 803 } 804 break; 805 case BRWR: 806 case EXTEND_ADDR_WRITE: 807 s->ear = s->data[0]; 808 break; 809 case WNVCR: 810 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 811 break; 812 case WVCR: 813 s->volatile_cfg = s->data[0]; 814 break; 815 case WEVCR: 816 s->enh_volatile_cfg = s->data[0]; 817 break; 818 case RDID_90: 819 case RDID_AB: 820 if (get_man(s) == MAN_SST) { 821 if (s->cur_addr <= 1) { 822 if (s->cur_addr) { 823 s->data[0] = s->pi->id[2]; 824 s->data[1] = s->pi->id[0]; 825 } else { 826 s->data[0] = s->pi->id[0]; 827 s->data[1] = s->pi->id[2]; 828 } 829 s->pos = 0; 830 s->len = 2; 831 s->data_read_loop = true; 832 s->state = STATE_READING_DATA; 833 } else { 834 qemu_log_mask(LOG_GUEST_ERROR, 835 "M25P80: Invalid read id address\n"); 836 } 837 } else { 838 qemu_log_mask(LOG_GUEST_ERROR, 839 "M25P80: Read id (command 0x90/0xAB) is not supported" 840 " by device\n"); 841 } 842 break; 843 844 case RDSFDP: 845 s->state = STATE_READING_SFDP; 846 break; 847 848 default: 849 break; 850 } 851 } 852 853 static void reset_memory(Flash *s) 854 { 855 s->cmd_in_progress = NOP; 856 s->cur_addr = 0; 857 s->ear = 0; 858 s->four_bytes_address_mode = false; 859 s->len = 0; 860 s->needed_bytes = 0; 861 s->pos = 0; 862 s->state = STATE_IDLE; 863 s->write_enable = false; 864 s->reset_enable = false; 865 s->quad_enable = false; 866 s->aai_enable = false; 867 868 switch (get_man(s)) { 869 case MAN_NUMONYX: 870 s->volatile_cfg = 0; 871 s->volatile_cfg |= VCFG_DUMMY; 872 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 873 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 874 == NVCFG_XIP_MODE_DISABLED) { 875 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; 876 } 877 s->volatile_cfg |= deposit32(s->volatile_cfg, 878 VCFG_DUMMY_CLK_POS, 879 CFG_DUMMY_CLK_LEN, 880 extract32(s->nonvolatile_cfg, 881 NVCFG_DUMMY_CLK_POS, 882 CFG_DUMMY_CLK_LEN) 883 ); 884 885 s->enh_volatile_cfg = 0; 886 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; 887 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 888 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 889 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 890 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; 891 } 892 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 893 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; 894 } 895 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 896 s->four_bytes_address_mode = true; 897 } 898 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 899 s->ear = s->size / MAX_3BYTES_SIZE - 1; 900 } 901 break; 902 case MAN_MACRONIX: 903 s->volatile_cfg = 0x7; 904 break; 905 case MAN_SPANSION: 906 s->spansion_cr1v = s->spansion_cr1nv; 907 s->spansion_cr2v = s->spansion_cr2nv; 908 s->spansion_cr3v = s->spansion_cr3nv; 909 s->spansion_cr4v = s->spansion_cr4nv; 910 s->quad_enable = extract32(s->spansion_cr1v, 911 SPANSION_QUAD_CFG_POS, 912 SPANSION_QUAD_CFG_LEN 913 ); 914 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 915 SPANSION_ADDR_LEN_POS, 916 SPANSION_ADDR_LEN_LEN 917 ); 918 break; 919 default: 920 break; 921 } 922 923 trace_m25p80_reset_done(s); 924 } 925 926 static uint8_t numonyx_mode(Flash *s) 927 { 928 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { 929 return MODE_QIO; 930 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { 931 return MODE_DIO; 932 } else { 933 return MODE_STD; 934 } 935 } 936 937 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s) 938 { 939 uint8_t num_dummies; 940 uint8_t mode; 941 assert(get_man(s) == MAN_NUMONYX); 942 943 mode = numonyx_mode(s); 944 num_dummies = extract32(s->volatile_cfg, 4, 4); 945 946 if (num_dummies == 0x0 || num_dummies == 0xf) { 947 switch (s->cmd_in_progress) { 948 case QIOR: 949 case QIOR4: 950 num_dummies = 10; 951 break; 952 default: 953 num_dummies = (mode == MODE_QIO) ? 10 : 8; 954 break; 955 } 956 } 957 958 return num_dummies; 959 } 960 961 static void decode_fast_read_cmd(Flash *s) 962 { 963 s->needed_bytes = get_addr_length(s); 964 switch (get_man(s)) { 965 /* Dummy cycles - modeled with bytes writes instead of bits */ 966 case MAN_SST: 967 s->needed_bytes += 1; 968 break; 969 case MAN_WINBOND: 970 s->needed_bytes += 8; 971 break; 972 case MAN_NUMONYX: 973 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 974 break; 975 case MAN_MACRONIX: 976 if (extract32(s->volatile_cfg, 6, 2) == 1) { 977 s->needed_bytes += 6; 978 } else { 979 s->needed_bytes += 8; 980 } 981 break; 982 case MAN_SPANSION: 983 s->needed_bytes += extract32(s->spansion_cr2v, 984 SPANSION_DUMMY_CLK_POS, 985 SPANSION_DUMMY_CLK_LEN 986 ); 987 break; 988 case MAN_ISSI: 989 /* 990 * The Fast Read instruction code is followed by address bytes and 991 * dummy cycles, transmitted via the SI line. 992 * 993 * The number of dummy cycles is configurable but this is currently 994 * unmodeled, hence the default value 8 is used. 995 * 996 * QPI (Quad Peripheral Interface) mode has different default value 997 * of dummy cycles, but this is unsupported at the time being. 998 */ 999 s->needed_bytes += 1; 1000 break; 1001 default: 1002 break; 1003 } 1004 s->pos = 0; 1005 s->len = 0; 1006 s->state = STATE_COLLECTING_DATA; 1007 } 1008 1009 static void decode_dio_read_cmd(Flash *s) 1010 { 1011 s->needed_bytes = get_addr_length(s); 1012 /* Dummy cycles modeled with bytes writes instead of bits */ 1013 switch (get_man(s)) { 1014 case MAN_WINBOND: 1015 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1016 break; 1017 case MAN_SPANSION: 1018 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1019 s->needed_bytes += extract32(s->spansion_cr2v, 1020 SPANSION_DUMMY_CLK_POS, 1021 SPANSION_DUMMY_CLK_LEN 1022 ); 1023 break; 1024 case MAN_NUMONYX: 1025 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1026 break; 1027 case MAN_MACRONIX: 1028 switch (extract32(s->volatile_cfg, 6, 2)) { 1029 case 1: 1030 s->needed_bytes += 6; 1031 break; 1032 case 2: 1033 s->needed_bytes += 8; 1034 break; 1035 default: 1036 s->needed_bytes += 4; 1037 break; 1038 } 1039 break; 1040 case MAN_ISSI: 1041 /* 1042 * The Fast Read Dual I/O instruction code is followed by address bytes 1043 * and dummy cycles, transmitted via the IO1 and IO0 line. 1044 * 1045 * The number of dummy cycles is configurable but this is currently 1046 * unmodeled, hence the default value 4 is used. 1047 */ 1048 s->needed_bytes += 1; 1049 break; 1050 default: 1051 break; 1052 } 1053 s->pos = 0; 1054 s->len = 0; 1055 s->state = STATE_COLLECTING_DATA; 1056 } 1057 1058 static void decode_qio_read_cmd(Flash *s) 1059 { 1060 s->needed_bytes = get_addr_length(s); 1061 /* Dummy cycles modeled with bytes writes instead of bits */ 1062 switch (get_man(s)) { 1063 case MAN_WINBOND: 1064 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1065 s->needed_bytes += 4; 1066 break; 1067 case MAN_SPANSION: 1068 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1069 s->needed_bytes += extract32(s->spansion_cr2v, 1070 SPANSION_DUMMY_CLK_POS, 1071 SPANSION_DUMMY_CLK_LEN 1072 ); 1073 break; 1074 case MAN_NUMONYX: 1075 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1076 break; 1077 case MAN_MACRONIX: 1078 switch (extract32(s->volatile_cfg, 6, 2)) { 1079 case 1: 1080 s->needed_bytes += 4; 1081 break; 1082 case 2: 1083 s->needed_bytes += 8; 1084 break; 1085 default: 1086 s->needed_bytes += 6; 1087 break; 1088 } 1089 break; 1090 case MAN_ISSI: 1091 /* 1092 * The Fast Read Quad I/O instruction code is followed by address bytes 1093 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line. 1094 * 1095 * The number of dummy cycles is configurable but this is currently 1096 * unmodeled, hence the default value 6 is used. 1097 * 1098 * QPI (Quad Peripheral Interface) mode has different default value 1099 * of dummy cycles, but this is unsupported at the time being. 1100 */ 1101 s->needed_bytes += 3; 1102 break; 1103 default: 1104 break; 1105 } 1106 s->pos = 0; 1107 s->len = 0; 1108 s->state = STATE_COLLECTING_DATA; 1109 } 1110 1111 static bool is_valid_aai_cmd(uint32_t cmd) 1112 { 1113 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR; 1114 } 1115 1116 static void decode_new_cmd(Flash *s, uint32_t value) 1117 { 1118 int i; 1119 1120 s->cmd_in_progress = value; 1121 trace_m25p80_command_decoded(s, value); 1122 1123 if (value != RESET_MEMORY) { 1124 s->reset_enable = false; 1125 } 1126 1127 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) { 1128 qemu_log_mask(LOG_GUEST_ERROR, 1129 "M25P80: Invalid cmd within AAI programming sequence"); 1130 } 1131 1132 switch (value) { 1133 1134 case ERASE_4K: 1135 case ERASE4_4K: 1136 case ERASE_32K: 1137 case ERASE4_32K: 1138 case ERASE_SECTOR: 1139 case ERASE4_SECTOR: 1140 case PP: 1141 case PP4: 1142 case DIE_ERASE: 1143 case RDID_90: 1144 case RDID_AB: 1145 s->needed_bytes = get_addr_length(s); 1146 s->pos = 0; 1147 s->len = 0; 1148 s->state = STATE_COLLECTING_DATA; 1149 break; 1150 case READ: 1151 case READ4: 1152 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1153 s->needed_bytes = get_addr_length(s); 1154 s->pos = 0; 1155 s->len = 0; 1156 s->state = STATE_COLLECTING_DATA; 1157 } else { 1158 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1159 "DIO or QIO mode\n", s->cmd_in_progress); 1160 } 1161 break; 1162 case DPP: 1163 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1164 s->needed_bytes = get_addr_length(s); 1165 s->pos = 0; 1166 s->len = 0; 1167 s->state = STATE_COLLECTING_DATA; 1168 } else { 1169 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1170 "QIO mode\n", s->cmd_in_progress); 1171 } 1172 break; 1173 case QPP: 1174 case QPP_4: 1175 case PP4_4: 1176 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1177 s->needed_bytes = get_addr_length(s); 1178 s->pos = 0; 1179 s->len = 0; 1180 s->state = STATE_COLLECTING_DATA; 1181 } else { 1182 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1183 "DIO mode\n", s->cmd_in_progress); 1184 } 1185 break; 1186 1187 case FAST_READ: 1188 case FAST_READ4: 1189 decode_fast_read_cmd(s); 1190 break; 1191 case DOR: 1192 case DOR4: 1193 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1194 decode_fast_read_cmd(s); 1195 } else { 1196 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1197 "QIO mode\n", s->cmd_in_progress); 1198 } 1199 break; 1200 case QOR: 1201 case QOR4: 1202 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1203 decode_fast_read_cmd(s); 1204 } else { 1205 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1206 "DIO mode\n", s->cmd_in_progress); 1207 } 1208 break; 1209 1210 case DIOR: 1211 case DIOR4: 1212 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1213 decode_dio_read_cmd(s); 1214 } else { 1215 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1216 "QIO mode\n", s->cmd_in_progress); 1217 } 1218 break; 1219 1220 case QIOR: 1221 case QIOR4: 1222 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1223 decode_qio_read_cmd(s); 1224 } else { 1225 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1226 "DIO mode\n", s->cmd_in_progress); 1227 } 1228 break; 1229 1230 case WRSR: 1231 /* 1232 * If WP# is low and status_register_write_disabled is high, 1233 * status register writes are disabled. 1234 * This is also called "hardware protected mode" (HPM). All other 1235 * combinations of the two states are called "software protected mode" 1236 * (SPM), and status register writes are permitted. 1237 */ 1238 if ((s->wp_level == 0 && s->status_register_write_disabled) 1239 || !s->write_enable) { 1240 qemu_log_mask(LOG_GUEST_ERROR, 1241 "M25P80: Status register write is disabled!\n"); 1242 break; 1243 } 1244 1245 switch (get_man(s)) { 1246 case MAN_SPANSION: 1247 s->needed_bytes = 2; 1248 s->state = STATE_COLLECTING_DATA; 1249 break; 1250 case MAN_MACRONIX: 1251 s->needed_bytes = 2; 1252 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1253 break; 1254 default: 1255 s->needed_bytes = 1; 1256 s->state = STATE_COLLECTING_DATA; 1257 } 1258 s->pos = 0; 1259 break; 1260 1261 case WRDI: 1262 s->write_enable = false; 1263 if (get_man(s) == MAN_SST) { 1264 s->aai_enable = false; 1265 } 1266 break; 1267 case WREN: 1268 s->write_enable = true; 1269 break; 1270 1271 case RDSR: 1272 s->data[0] = (!!s->write_enable) << 1; 1273 s->data[0] |= (!!s->status_register_write_disabled) << 7; 1274 s->data[0] |= (!!s->block_protect0) << 2; 1275 s->data[0] |= (!!s->block_protect1) << 3; 1276 s->data[0] |= (!!s->block_protect2) << 4; 1277 if (s->pi->flags & HAS_SR_TB) { 1278 s->data[0] |= (!!s->top_bottom_bit) << 5; 1279 } 1280 if (s->pi->flags & HAS_SR_BP3_BIT6) { 1281 s->data[0] |= (!!s->block_protect3) << 6; 1282 } 1283 1284 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) { 1285 s->data[0] |= (!!s->quad_enable) << 6; 1286 } 1287 if (get_man(s) == MAN_SST) { 1288 s->data[0] |= (!!s->aai_enable) << 6; 1289 } 1290 1291 s->pos = 0; 1292 s->len = 1; 1293 s->data_read_loop = true; 1294 s->state = STATE_READING_DATA; 1295 break; 1296 1297 case READ_FSR: 1298 s->data[0] = FSR_FLASH_READY; 1299 if (s->four_bytes_address_mode) { 1300 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 1301 } 1302 s->pos = 0; 1303 s->len = 1; 1304 s->data_read_loop = true; 1305 s->state = STATE_READING_DATA; 1306 break; 1307 1308 case JEDEC_READ: 1309 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1310 trace_m25p80_populated_jedec(s); 1311 for (i = 0; i < s->pi->id_len; i++) { 1312 s->data[i] = s->pi->id[i]; 1313 } 1314 for (; i < SPI_NOR_MAX_ID_LEN; i++) { 1315 s->data[i] = 0; 1316 } 1317 1318 s->len = SPI_NOR_MAX_ID_LEN; 1319 s->pos = 0; 1320 s->state = STATE_READING_DATA; 1321 } else { 1322 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read " 1323 "in DIO or QIO mode\n"); 1324 } 1325 break; 1326 1327 case RDCR: 1328 s->data[0] = s->volatile_cfg & 0xFF; 1329 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 1330 s->pos = 0; 1331 s->len = 1; 1332 s->state = STATE_READING_DATA; 1333 break; 1334 1335 case BULK_ERASE_60: 1336 case BULK_ERASE: 1337 if (s->write_enable) { 1338 trace_m25p80_chip_erase(s); 1339 flash_erase(s, 0, BULK_ERASE); 1340 } else { 1341 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 1342 "protect!\n"); 1343 } 1344 break; 1345 case NOP: 1346 break; 1347 case EN_4BYTE_ADDR: 1348 s->four_bytes_address_mode = true; 1349 break; 1350 case EX_4BYTE_ADDR: 1351 s->four_bytes_address_mode = false; 1352 break; 1353 case BRRD: 1354 case EXTEND_ADDR_READ: 1355 s->data[0] = s->ear; 1356 s->pos = 0; 1357 s->len = 1; 1358 s->state = STATE_READING_DATA; 1359 break; 1360 case BRWR: 1361 case EXTEND_ADDR_WRITE: 1362 if (s->write_enable) { 1363 s->needed_bytes = 1; 1364 s->pos = 0; 1365 s->len = 0; 1366 s->state = STATE_COLLECTING_DATA; 1367 } 1368 break; 1369 case RNVCR: 1370 s->data[0] = s->nonvolatile_cfg & 0xFF; 1371 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1372 s->pos = 0; 1373 s->len = 2; 1374 s->state = STATE_READING_DATA; 1375 break; 1376 case WNVCR: 1377 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1378 s->needed_bytes = 2; 1379 s->pos = 0; 1380 s->len = 0; 1381 s->state = STATE_COLLECTING_DATA; 1382 } 1383 break; 1384 case RVCR: 1385 s->data[0] = s->volatile_cfg & 0xFF; 1386 s->pos = 0; 1387 s->len = 1; 1388 s->state = STATE_READING_DATA; 1389 break; 1390 case WVCR: 1391 if (s->write_enable) { 1392 s->needed_bytes = 1; 1393 s->pos = 0; 1394 s->len = 0; 1395 s->state = STATE_COLLECTING_DATA; 1396 } 1397 break; 1398 case REVCR: 1399 s->data[0] = s->enh_volatile_cfg & 0xFF; 1400 s->pos = 0; 1401 s->len = 1; 1402 s->state = STATE_READING_DATA; 1403 break; 1404 case WEVCR: 1405 if (s->write_enable) { 1406 s->needed_bytes = 1; 1407 s->pos = 0; 1408 s->len = 0; 1409 s->state = STATE_COLLECTING_DATA; 1410 } 1411 break; 1412 case RESET_ENABLE: 1413 s->reset_enable = true; 1414 break; 1415 case RESET_MEMORY: 1416 if (s->reset_enable) { 1417 reset_memory(s); 1418 } 1419 break; 1420 case RDCR_EQIO: 1421 switch (get_man(s)) { 1422 case MAN_SPANSION: 1423 s->data[0] = (!!s->quad_enable) << 1; 1424 s->pos = 0; 1425 s->len = 1; 1426 s->state = STATE_READING_DATA; 1427 break; 1428 case MAN_MACRONIX: 1429 s->quad_enable = true; 1430 break; 1431 default: 1432 break; 1433 } 1434 break; 1435 case RSTQIO: 1436 s->quad_enable = false; 1437 break; 1438 case AAI_WP: 1439 if (get_man(s) == MAN_SST) { 1440 if (s->write_enable) { 1441 if (s->aai_enable) { 1442 s->state = STATE_PAGE_PROGRAM; 1443 } else { 1444 s->aai_enable = true; 1445 s->needed_bytes = get_addr_length(s); 1446 s->state = STATE_COLLECTING_DATA; 1447 } 1448 } else { 1449 qemu_log_mask(LOG_GUEST_ERROR, 1450 "M25P80: AAI_WP with write protect\n"); 1451 } 1452 } else { 1453 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1454 } 1455 break; 1456 case RDSFDP: 1457 if (s->pi->sfdp_read) { 1458 s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */ 1459 s->pos = 0; 1460 s->len = 0; 1461 s->state = STATE_COLLECTING_DATA; 1462 break; 1463 } 1464 /* Fallthrough */ 1465 1466 default: 1467 s->pos = 0; 1468 s->len = 1; 1469 s->state = STATE_READING_DATA; 1470 s->data_read_loop = true; 1471 s->data[0] = 0; 1472 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1473 break; 1474 } 1475 } 1476 1477 static int m25p80_cs(SSIPeripheral *ss, bool select) 1478 { 1479 Flash *s = M25P80(ss); 1480 1481 if (select) { 1482 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1483 complete_collecting_data(s); 1484 } 1485 s->len = 0; 1486 s->pos = 0; 1487 s->state = STATE_IDLE; 1488 flash_sync_dirty(s, -1); 1489 s->data_read_loop = false; 1490 } 1491 1492 trace_m25p80_select(s, select ? "de" : ""); 1493 1494 return 0; 1495 } 1496 1497 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) 1498 { 1499 Flash *s = M25P80(ss); 1500 uint32_t r = 0; 1501 1502 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, 1503 s->cur_addr, (uint8_t)tx); 1504 1505 switch (s->state) { 1506 1507 case STATE_PAGE_PROGRAM: 1508 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); 1509 flash_write8(s, s->cur_addr, (uint8_t)tx); 1510 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1511 1512 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) { 1513 /* 1514 * There is no wrap mode during AAI programming once the highest 1515 * unprotected memory address is reached. The Write-Enable-Latch 1516 * bit is automatically reset, and AAI programming mode aborts. 1517 */ 1518 s->write_enable = false; 1519 s->aai_enable = false; 1520 } 1521 1522 break; 1523 1524 case STATE_READ: 1525 r = s->storage[s->cur_addr]; 1526 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); 1527 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1528 break; 1529 1530 case STATE_COLLECTING_DATA: 1531 case STATE_COLLECTING_VAR_LEN_DATA: 1532 1533 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1534 qemu_log_mask(LOG_GUEST_ERROR, 1535 "M25P80: Write overrun internal data buffer. " 1536 "SPI controller (QEMU emulator or guest driver) " 1537 "is misbehaving\n"); 1538 s->len = s->pos = 0; 1539 s->state = STATE_IDLE; 1540 break; 1541 } 1542 1543 s->data[s->len] = (uint8_t)tx; 1544 s->len++; 1545 1546 if (s->len == s->needed_bytes) { 1547 complete_collecting_data(s); 1548 } 1549 break; 1550 1551 case STATE_READING_DATA: 1552 1553 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1554 qemu_log_mask(LOG_GUEST_ERROR, 1555 "M25P80: Read overrun internal data buffer. " 1556 "SPI controller (QEMU emulator or guest driver) " 1557 "is misbehaving\n"); 1558 s->len = s->pos = 0; 1559 s->state = STATE_IDLE; 1560 break; 1561 } 1562 1563 r = s->data[s->pos]; 1564 trace_m25p80_read_data(s, s->pos, (uint8_t)r); 1565 s->pos++; 1566 if (s->pos == s->len) { 1567 s->pos = 0; 1568 if (!s->data_read_loop) { 1569 s->state = STATE_IDLE; 1570 } 1571 } 1572 break; 1573 case STATE_READING_SFDP: 1574 assert(s->pi->sfdp_read); 1575 r = s->pi->sfdp_read(s->cur_addr); 1576 trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r); 1577 s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1); 1578 break; 1579 1580 default: 1581 case STATE_IDLE: 1582 decode_new_cmd(s, (uint8_t)tx); 1583 break; 1584 } 1585 1586 return r; 1587 } 1588 1589 static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level) 1590 { 1591 Flash *s = M25P80(opaque); 1592 /* WP# is just a single pin. */ 1593 assert(n == 0); 1594 s->wp_level = !!level; 1595 } 1596 1597 static void m25p80_realize(SSIPeripheral *ss, Error **errp) 1598 { 1599 Flash *s = M25P80(ss); 1600 M25P80Class *mc = M25P80_GET_CLASS(s); 1601 int ret; 1602 1603 s->pi = mc->pi; 1604 1605 s->size = s->pi->sector_size * s->pi->n_sectors; 1606 s->dirty_page = -1; 1607 1608 if (s->blk) { 1609 uint64_t perm = BLK_PERM_CONSISTENT_READ | 1610 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0); 1611 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); 1612 if (ret < 0) { 1613 return; 1614 } 1615 1616 trace_m25p80_binding(s); 1617 s->storage = blk_blockalign(s->blk, s->size); 1618 1619 if (!blk_check_size_and_read_all(s->blk, s->storage, s->size, errp)) { 1620 return; 1621 } 1622 } else { 1623 trace_m25p80_binding_no_bdrv(s); 1624 s->storage = blk_blockalign(NULL, s->size); 1625 memset(s->storage, 0xFF, s->size); 1626 } 1627 1628 qdev_init_gpio_in_named(DEVICE(s), 1629 m25p80_write_protect_pin_irq_handler, "WP#", 1); 1630 } 1631 1632 static void m25p80_reset(DeviceState *d) 1633 { 1634 Flash *s = M25P80(d); 1635 1636 s->wp_level = true; 1637 s->status_register_write_disabled = false; 1638 s->block_protect0 = false; 1639 s->block_protect1 = false; 1640 s->block_protect2 = false; 1641 s->block_protect3 = false; 1642 s->top_bottom_bit = false; 1643 1644 reset_memory(s); 1645 } 1646 1647 static int m25p80_pre_save(void *opaque) 1648 { 1649 flash_sync_dirty((Flash *)opaque, -1); 1650 1651 return 0; 1652 } 1653 1654 static Property m25p80_properties[] = { 1655 /* This is default value for Micron flash */ 1656 DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false), 1657 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1658 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1659 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1660 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1661 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1662 DEFINE_PROP_DRIVE("drive", Flash, blk), 1663 DEFINE_PROP_END_OF_LIST(), 1664 }; 1665 1666 static int m25p80_pre_load(void *opaque) 1667 { 1668 Flash *s = (Flash *)opaque; 1669 1670 s->data_read_loop = false; 1671 return 0; 1672 } 1673 1674 static bool m25p80_data_read_loop_needed(void *opaque) 1675 { 1676 Flash *s = (Flash *)opaque; 1677 1678 return s->data_read_loop; 1679 } 1680 1681 static const VMStateDescription vmstate_m25p80_data_read_loop = { 1682 .name = "m25p80/data_read_loop", 1683 .version_id = 1, 1684 .minimum_version_id = 1, 1685 .needed = m25p80_data_read_loop_needed, 1686 .fields = (VMStateField[]) { 1687 VMSTATE_BOOL(data_read_loop, Flash), 1688 VMSTATE_END_OF_LIST() 1689 } 1690 }; 1691 1692 static bool m25p80_aai_enable_needed(void *opaque) 1693 { 1694 Flash *s = (Flash *)opaque; 1695 1696 return s->aai_enable; 1697 } 1698 1699 static const VMStateDescription vmstate_m25p80_aai_enable = { 1700 .name = "m25p80/aai_enable", 1701 .version_id = 1, 1702 .minimum_version_id = 1, 1703 .needed = m25p80_aai_enable_needed, 1704 .fields = (VMStateField[]) { 1705 VMSTATE_BOOL(aai_enable, Flash), 1706 VMSTATE_END_OF_LIST() 1707 } 1708 }; 1709 1710 static bool m25p80_wp_level_srwd_needed(void *opaque) 1711 { 1712 Flash *s = (Flash *)opaque; 1713 1714 return !s->wp_level || s->status_register_write_disabled; 1715 } 1716 1717 static const VMStateDescription vmstate_m25p80_write_protect = { 1718 .name = "m25p80/write_protect", 1719 .version_id = 1, 1720 .minimum_version_id = 1, 1721 .needed = m25p80_wp_level_srwd_needed, 1722 .fields = (VMStateField[]) { 1723 VMSTATE_BOOL(wp_level, Flash), 1724 VMSTATE_BOOL(status_register_write_disabled, Flash), 1725 VMSTATE_END_OF_LIST() 1726 } 1727 }; 1728 1729 static bool m25p80_block_protect_needed(void *opaque) 1730 { 1731 Flash *s = (Flash *)opaque; 1732 1733 return s->block_protect0 || 1734 s->block_protect1 || 1735 s->block_protect2 || 1736 s->block_protect3 || 1737 s->top_bottom_bit; 1738 } 1739 1740 static const VMStateDescription vmstate_m25p80_block_protect = { 1741 .name = "m25p80/block_protect", 1742 .version_id = 1, 1743 .minimum_version_id = 1, 1744 .needed = m25p80_block_protect_needed, 1745 .fields = (VMStateField[]) { 1746 VMSTATE_BOOL(block_protect0, Flash), 1747 VMSTATE_BOOL(block_protect1, Flash), 1748 VMSTATE_BOOL(block_protect2, Flash), 1749 VMSTATE_BOOL(block_protect3, Flash), 1750 VMSTATE_BOOL(top_bottom_bit, Flash), 1751 VMSTATE_END_OF_LIST() 1752 } 1753 }; 1754 1755 static const VMStateDescription vmstate_m25p80 = { 1756 .name = "m25p80", 1757 .version_id = 0, 1758 .minimum_version_id = 0, 1759 .pre_save = m25p80_pre_save, 1760 .pre_load = m25p80_pre_load, 1761 .fields = (VMStateField[]) { 1762 VMSTATE_UINT8(state, Flash), 1763 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1764 VMSTATE_UINT32(len, Flash), 1765 VMSTATE_UINT32(pos, Flash), 1766 VMSTATE_UINT8(needed_bytes, Flash), 1767 VMSTATE_UINT8(cmd_in_progress, Flash), 1768 VMSTATE_UINT32(cur_addr, Flash), 1769 VMSTATE_BOOL(write_enable, Flash), 1770 VMSTATE_BOOL(reset_enable, Flash), 1771 VMSTATE_UINT8(ear, Flash), 1772 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1773 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1774 VMSTATE_UINT32(volatile_cfg, Flash), 1775 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1776 VMSTATE_BOOL(quad_enable, Flash), 1777 VMSTATE_UINT8(spansion_cr1nv, Flash), 1778 VMSTATE_UINT8(spansion_cr2nv, Flash), 1779 VMSTATE_UINT8(spansion_cr3nv, Flash), 1780 VMSTATE_UINT8(spansion_cr4nv, Flash), 1781 VMSTATE_END_OF_LIST() 1782 }, 1783 .subsections = (const VMStateDescription * []) { 1784 &vmstate_m25p80_data_read_loop, 1785 &vmstate_m25p80_aai_enable, 1786 &vmstate_m25p80_write_protect, 1787 &vmstate_m25p80_block_protect, 1788 NULL 1789 } 1790 }; 1791 1792 static void m25p80_class_init(ObjectClass *klass, void *data) 1793 { 1794 DeviceClass *dc = DEVICE_CLASS(klass); 1795 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); 1796 M25P80Class *mc = M25P80_CLASS(klass); 1797 1798 k->realize = m25p80_realize; 1799 k->transfer = m25p80_transfer8; 1800 k->set_cs = m25p80_cs; 1801 k->cs_polarity = SSI_CS_LOW; 1802 dc->vmsd = &vmstate_m25p80; 1803 device_class_set_props(dc, m25p80_properties); 1804 dc->reset = m25p80_reset; 1805 mc->pi = data; 1806 } 1807 1808 static const TypeInfo m25p80_info = { 1809 .name = TYPE_M25P80, 1810 .parent = TYPE_SSI_PERIPHERAL, 1811 .instance_size = sizeof(Flash), 1812 .class_size = sizeof(M25P80Class), 1813 .abstract = true, 1814 }; 1815 1816 static void m25p80_register_types(void) 1817 { 1818 int i; 1819 1820 type_register_static(&m25p80_info); 1821 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1822 TypeInfo ti = { 1823 .name = known_devices[i].part_name, 1824 .parent = TYPE_M25P80, 1825 .class_init = m25p80_class_init, 1826 .class_data = (void *)&known_devices[i], 1827 }; 1828 type_register(&ti); 1829 } 1830 } 1831 1832 type_init(m25p80_register_types) 1833