1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/qdev-properties-system.h" 29 #include "hw/ssi/ssi.h" 30 #include "migration/vmstate.h" 31 #include "qemu/bitops.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 #include "qemu/error-report.h" 35 #include "qapi/error.h" 36 #include "trace.h" 37 #include "qom/object.h" 38 39 /* Fields for FlashPartInfo->flags */ 40 41 /* erase capabilities */ 42 #define ER_4K 1 43 #define ER_32K 2 44 /* set to allow the page program command to write 0s back to 1. Useful for 45 * modelling EEPROM with SPI flash command set 46 */ 47 #define EEPROM 0x100 48 49 /* 16 MiB max in 3 byte address mode */ 50 #define MAX_3BYTES_SIZE 0x1000000 51 52 #define SPI_NOR_MAX_ID_LEN 6 53 54 typedef struct FlashPartInfo { 55 const char *part_name; 56 /* 57 * This array stores the ID bytes. 58 * The first three bytes are the JEDIC ID. 59 * JEDEC ID zero means "no ID" (mostly older chips). 60 */ 61 uint8_t id[SPI_NOR_MAX_ID_LEN]; 62 uint8_t id_len; 63 /* there is confusion between manufacturers as to what a sector is. In this 64 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 65 * command (opcode 0xd8). 66 */ 67 uint32_t sector_size; 68 uint32_t n_sectors; 69 uint32_t page_size; 70 uint16_t flags; 71 /* 72 * Big sized spi nor are often stacked devices, thus sometime 73 * replace chip erase with die erase. 74 * This field inform how many die is in the chip. 75 */ 76 uint8_t die_cnt; 77 } FlashPartInfo; 78 79 /* adapted from linux */ 80 /* Used when the "_ext_id" is two bytes at most */ 81 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 82 .part_name = _part_name,\ 83 .id = {\ 84 ((_jedec_id) >> 16) & 0xff,\ 85 ((_jedec_id) >> 8) & 0xff,\ 86 (_jedec_id) & 0xff,\ 87 ((_ext_id) >> 8) & 0xff,\ 88 (_ext_id) & 0xff,\ 89 },\ 90 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 91 .sector_size = (_sector_size),\ 92 .n_sectors = (_n_sectors),\ 93 .page_size = 256,\ 94 .flags = (_flags),\ 95 .die_cnt = 0 96 97 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 98 .part_name = _part_name,\ 99 .id = {\ 100 ((_jedec_id) >> 16) & 0xff,\ 101 ((_jedec_id) >> 8) & 0xff,\ 102 (_jedec_id) & 0xff,\ 103 ((_ext_id) >> 16) & 0xff,\ 104 ((_ext_id) >> 8) & 0xff,\ 105 (_ext_id) & 0xff,\ 106 },\ 107 .id_len = 6,\ 108 .sector_size = (_sector_size),\ 109 .n_sectors = (_n_sectors),\ 110 .page_size = 256,\ 111 .flags = (_flags),\ 112 .die_cnt = 0 113 114 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ 115 _flags, _die_cnt)\ 116 .part_name = _part_name,\ 117 .id = {\ 118 ((_jedec_id) >> 16) & 0xff,\ 119 ((_jedec_id) >> 8) & 0xff,\ 120 (_jedec_id) & 0xff,\ 121 ((_ext_id) >> 8) & 0xff,\ 122 (_ext_id) & 0xff,\ 123 },\ 124 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 125 .sector_size = (_sector_size),\ 126 .n_sectors = (_n_sectors),\ 127 .page_size = 256,\ 128 .flags = (_flags),\ 129 .die_cnt = _die_cnt 130 131 #define JEDEC_NUMONYX 0x20 132 #define JEDEC_WINBOND 0xEF 133 #define JEDEC_SPANSION 0x01 134 135 /* Numonyx (Micron) Configuration register macros */ 136 #define VCFG_DUMMY 0x1 137 #define VCFG_WRAP_SEQUENTIAL 0x2 138 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 139 #define NVCFG_XIP_MODE_MASK (7 << 9) 140 #define VCFG_XIP_MODE_DISABLED (1 << 3) 141 #define CFG_DUMMY_CLK_LEN 4 142 #define NVCFG_DUMMY_CLK_POS 12 143 #define VCFG_DUMMY_CLK_POS 4 144 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 145 #define EVCFG_VPP_ACCELERATOR (1 << 3) 146 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 147 #define NVCFG_DUAL_IO_MASK (1 << 2) 148 #define EVCFG_DUAL_IO_DISABLED (1 << 6) 149 #define NVCFG_QUAD_IO_MASK (1 << 3) 150 #define EVCFG_QUAD_IO_DISABLED (1 << 7) 151 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 152 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 153 154 /* Numonyx (Micron) Flag Status Register macros */ 155 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 156 #define FSR_FLASH_READY (1 << 7) 157 158 /* Spansion configuration registers macros. */ 159 #define SPANSION_QUAD_CFG_POS 0 160 #define SPANSION_QUAD_CFG_LEN 1 161 #define SPANSION_DUMMY_CLK_POS 0 162 #define SPANSION_DUMMY_CLK_LEN 4 163 #define SPANSION_ADDR_LEN_POS 7 164 #define SPANSION_ADDR_LEN_LEN 1 165 166 /* 167 * Spansion read mode command length in bytes, 168 * the mode is currently not supported. 169 */ 170 171 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 172 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 173 174 static const FlashPartInfo known_devices[] = { 175 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 176 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 177 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 178 179 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 180 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 181 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 182 183 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 184 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 185 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 186 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 187 188 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 189 190 /* Atmel EEPROMS - it is assumed, that don't care bit in command 191 * is set to 0. Block protection is not supported. 192 */ 193 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 194 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 195 196 /* EON -- en25xxx */ 197 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 198 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 199 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 200 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 201 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 202 203 /* GigaDevice */ 204 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 205 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 206 207 /* Intel/Numonyx -- xxxs33b */ 208 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 209 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 210 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 211 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 212 213 /* Macronix */ 214 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 215 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 216 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 217 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 218 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 219 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 220 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 221 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 222 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) }, 223 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 224 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 225 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 226 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 227 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 228 229 /* Micron */ 230 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 231 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 232 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 233 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 234 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 235 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 236 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 237 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 238 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, 239 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 240 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 241 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 242 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 243 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, 244 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, 245 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 246 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 247 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 248 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 249 250 /* Spansion -- single (large) sector size only, at least 251 * for the chips listed here (without boot sectors). 252 */ 253 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 254 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 255 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 256 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 257 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 258 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 259 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 260 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 261 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 262 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 263 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 264 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 265 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 266 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 267 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 268 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 269 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 270 271 /* Spansion -- boot sectors support */ 272 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 273 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 274 275 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 276 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 277 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 278 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 279 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 280 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 281 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 282 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 283 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 284 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 285 286 /* ST Microelectronics -- newer production may have feature updates */ 287 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 288 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 289 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 290 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 291 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 292 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 293 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 294 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 295 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 296 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 297 298 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 299 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 300 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 301 302 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 303 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 304 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 305 306 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 307 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 308 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 309 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 310 311 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 312 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 313 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 314 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 315 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 316 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 317 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 318 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 319 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 320 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 321 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 322 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 323 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 324 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, 325 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) }, 326 }; 327 328 typedef enum { 329 NOP = 0, 330 WRSR = 0x1, 331 WRDI = 0x4, 332 RDSR = 0x5, 333 WREN = 0x6, 334 BRRD = 0x16, 335 BRWR = 0x17, 336 JEDEC_READ = 0x9f, 337 BULK_ERASE_60 = 0x60, 338 BULK_ERASE = 0xc7, 339 READ_FSR = 0x70, 340 RDCR = 0x15, 341 342 READ = 0x03, 343 READ4 = 0x13, 344 FAST_READ = 0x0b, 345 FAST_READ4 = 0x0c, 346 DOR = 0x3b, 347 DOR4 = 0x3c, 348 QOR = 0x6b, 349 QOR4 = 0x6c, 350 DIOR = 0xbb, 351 DIOR4 = 0xbc, 352 QIOR = 0xeb, 353 QIOR4 = 0xec, 354 355 PP = 0x02, 356 PP4 = 0x12, 357 PP4_4 = 0x3e, 358 DPP = 0xa2, 359 QPP = 0x32, 360 QPP_4 = 0x34, 361 RDID_90 = 0x90, 362 RDID_AB = 0xab, 363 364 ERASE_4K = 0x20, 365 ERASE4_4K = 0x21, 366 ERASE_32K = 0x52, 367 ERASE4_32K = 0x5c, 368 ERASE_SECTOR = 0xd8, 369 ERASE4_SECTOR = 0xdc, 370 371 EN_4BYTE_ADDR = 0xB7, 372 EX_4BYTE_ADDR = 0xE9, 373 374 EXTEND_ADDR_READ = 0xC8, 375 EXTEND_ADDR_WRITE = 0xC5, 376 377 RESET_ENABLE = 0x66, 378 RESET_MEMORY = 0x99, 379 380 /* 381 * Micron: 0x35 - enable QPI 382 * Spansion: 0x35 - read control register 383 */ 384 RDCR_EQIO = 0x35, 385 RSTQIO = 0xf5, 386 387 RNVCR = 0xB5, 388 WNVCR = 0xB1, 389 390 RVCR = 0x85, 391 WVCR = 0x81, 392 393 REVCR = 0x65, 394 WEVCR = 0x61, 395 396 DIE_ERASE = 0xC4, 397 } FlashCMD; 398 399 typedef enum { 400 STATE_IDLE, 401 STATE_PAGE_PROGRAM, 402 STATE_READ, 403 STATE_COLLECTING_DATA, 404 STATE_COLLECTING_VAR_LEN_DATA, 405 STATE_READING_DATA, 406 } CMDState; 407 408 typedef enum { 409 MAN_SPANSION, 410 MAN_MACRONIX, 411 MAN_NUMONYX, 412 MAN_WINBOND, 413 MAN_SST, 414 MAN_GENERIC, 415 } Manufacturer; 416 417 typedef enum { 418 MODE_STD = 0, 419 MODE_DIO = 1, 420 MODE_QIO = 2 421 } SPIMode; 422 423 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 424 425 struct Flash { 426 SSIPeripheral parent_obj; 427 428 BlockBackend *blk; 429 430 uint8_t *storage; 431 uint32_t size; 432 int page_size; 433 434 uint8_t state; 435 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 436 uint32_t len; 437 uint32_t pos; 438 bool data_read_loop; 439 uint8_t needed_bytes; 440 uint8_t cmd_in_progress; 441 uint32_t cur_addr; 442 uint32_t nonvolatile_cfg; 443 /* Configuration register for Macronix */ 444 uint32_t volatile_cfg; 445 uint32_t enh_volatile_cfg; 446 /* Spansion cfg registers. */ 447 uint8_t spansion_cr1nv; 448 uint8_t spansion_cr2nv; 449 uint8_t spansion_cr3nv; 450 uint8_t spansion_cr4nv; 451 uint8_t spansion_cr1v; 452 uint8_t spansion_cr2v; 453 uint8_t spansion_cr3v; 454 uint8_t spansion_cr4v; 455 bool write_enable; 456 bool four_bytes_address_mode; 457 bool reset_enable; 458 bool quad_enable; 459 uint8_t ear; 460 461 int64_t dirty_page; 462 463 const FlashPartInfo *pi; 464 465 }; 466 467 struct M25P80Class { 468 SSIPeripheralClass parent_class; 469 FlashPartInfo *pi; 470 }; 471 472 #define TYPE_M25P80 "m25p80-generic" 473 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) 474 475 static inline Manufacturer get_man(Flash *s) 476 { 477 switch (s->pi->id[0]) { 478 case 0x20: 479 return MAN_NUMONYX; 480 case 0xEF: 481 return MAN_WINBOND; 482 case 0x01: 483 return MAN_SPANSION; 484 case 0xC2: 485 return MAN_MACRONIX; 486 case 0xBF: 487 return MAN_SST; 488 default: 489 return MAN_GENERIC; 490 } 491 } 492 493 static void blk_sync_complete(void *opaque, int ret) 494 { 495 QEMUIOVector *iov = opaque; 496 497 qemu_iovec_destroy(iov); 498 g_free(iov); 499 500 /* do nothing. Masters do not directly interact with the backing store, 501 * only the working copy so no mutexing required. 502 */ 503 } 504 505 static void flash_sync_page(Flash *s, int page) 506 { 507 QEMUIOVector *iov; 508 509 if (!s->blk || blk_is_read_only(s->blk)) { 510 return; 511 } 512 513 iov = g_new(QEMUIOVector, 1); 514 qemu_iovec_init(iov, 1); 515 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 516 s->pi->page_size); 517 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 518 blk_sync_complete, iov); 519 } 520 521 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 522 { 523 QEMUIOVector *iov; 524 525 if (!s->blk || blk_is_read_only(s->blk)) { 526 return; 527 } 528 529 assert(!(len % BDRV_SECTOR_SIZE)); 530 iov = g_new(QEMUIOVector, 1); 531 qemu_iovec_init(iov, 1); 532 qemu_iovec_add(iov, s->storage + off, len); 533 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 534 } 535 536 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 537 { 538 uint32_t len; 539 uint8_t capa_to_assert = 0; 540 541 switch (cmd) { 542 case ERASE_4K: 543 case ERASE4_4K: 544 len = 4 * KiB; 545 capa_to_assert = ER_4K; 546 break; 547 case ERASE_32K: 548 case ERASE4_32K: 549 len = 32 * KiB; 550 capa_to_assert = ER_32K; 551 break; 552 case ERASE_SECTOR: 553 case ERASE4_SECTOR: 554 len = s->pi->sector_size; 555 break; 556 case BULK_ERASE: 557 len = s->size; 558 break; 559 case DIE_ERASE: 560 if (s->pi->die_cnt) { 561 len = s->size / s->pi->die_cnt; 562 offset = offset & (~(len - 1)); 563 } else { 564 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" 565 " by device\n"); 566 return; 567 } 568 break; 569 default: 570 abort(); 571 } 572 573 trace_m25p80_flash_erase(s, offset, len); 574 575 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 576 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 577 " device\n", len); 578 } 579 580 if (!s->write_enable) { 581 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 582 return; 583 } 584 memset(s->storage + offset, 0xff, len); 585 flash_sync_area(s, offset, len); 586 } 587 588 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 589 { 590 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 591 flash_sync_page(s, s->dirty_page); 592 s->dirty_page = newpage; 593 } 594 } 595 596 static inline 597 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 598 { 599 uint32_t page = addr / s->pi->page_size; 600 uint8_t prev = s->storage[s->cur_addr]; 601 602 if (!s->write_enable) { 603 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 604 } 605 606 if ((prev ^ data) & data) { 607 trace_m25p80_programming_zero_to_one(s, addr, prev, data); 608 } 609 610 if (s->pi->flags & EEPROM) { 611 s->storage[s->cur_addr] = data; 612 } else { 613 s->storage[s->cur_addr] &= data; 614 } 615 616 flash_sync_dirty(s, page); 617 s->dirty_page = page; 618 } 619 620 static inline int get_addr_length(Flash *s) 621 { 622 /* check if eeprom is in use */ 623 if (s->pi->flags == EEPROM) { 624 return 2; 625 } 626 627 switch (s->cmd_in_progress) { 628 case PP4: 629 case PP4_4: 630 case QPP_4: 631 case READ4: 632 case QIOR4: 633 case ERASE4_4K: 634 case ERASE4_32K: 635 case ERASE4_SECTOR: 636 case FAST_READ4: 637 case DOR4: 638 case QOR4: 639 case DIOR4: 640 return 4; 641 default: 642 return s->four_bytes_address_mode ? 4 : 3; 643 } 644 } 645 646 static void complete_collecting_data(Flash *s) 647 { 648 int i, n; 649 650 n = get_addr_length(s); 651 s->cur_addr = (n == 3 ? s->ear : 0); 652 for (i = 0; i < n; ++i) { 653 s->cur_addr <<= 8; 654 s->cur_addr |= s->data[i]; 655 } 656 657 s->cur_addr &= s->size - 1; 658 659 s->state = STATE_IDLE; 660 661 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, 662 s->cur_addr); 663 664 switch (s->cmd_in_progress) { 665 case DPP: 666 case QPP: 667 case QPP_4: 668 case PP: 669 case PP4: 670 case PP4_4: 671 s->state = STATE_PAGE_PROGRAM; 672 break; 673 case READ: 674 case READ4: 675 case FAST_READ: 676 case FAST_READ4: 677 case DOR: 678 case DOR4: 679 case QOR: 680 case QOR4: 681 case DIOR: 682 case DIOR4: 683 case QIOR: 684 case QIOR4: 685 s->state = STATE_READ; 686 break; 687 case ERASE_4K: 688 case ERASE4_4K: 689 case ERASE_32K: 690 case ERASE4_32K: 691 case ERASE_SECTOR: 692 case ERASE4_SECTOR: 693 case DIE_ERASE: 694 flash_erase(s, s->cur_addr, s->cmd_in_progress); 695 break; 696 case WRSR: 697 switch (get_man(s)) { 698 case MAN_SPANSION: 699 s->quad_enable = !!(s->data[1] & 0x02); 700 break; 701 case MAN_MACRONIX: 702 s->quad_enable = extract32(s->data[0], 6, 1); 703 if (s->len > 1) { 704 s->volatile_cfg = s->data[1]; 705 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 706 } 707 break; 708 default: 709 break; 710 } 711 if (s->write_enable) { 712 s->write_enable = false; 713 } 714 break; 715 case BRWR: 716 case EXTEND_ADDR_WRITE: 717 s->ear = s->data[0]; 718 break; 719 case WNVCR: 720 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 721 break; 722 case WVCR: 723 s->volatile_cfg = s->data[0]; 724 break; 725 case WEVCR: 726 s->enh_volatile_cfg = s->data[0]; 727 break; 728 case RDID_90: 729 case RDID_AB: 730 if (get_man(s) == MAN_SST) { 731 if (s->cur_addr <= 1) { 732 if (s->cur_addr) { 733 s->data[0] = s->pi->id[2]; 734 s->data[1] = s->pi->id[0]; 735 } else { 736 s->data[0] = s->pi->id[0]; 737 s->data[1] = s->pi->id[2]; 738 } 739 s->pos = 0; 740 s->len = 2; 741 s->data_read_loop = true; 742 s->state = STATE_READING_DATA; 743 } else { 744 qemu_log_mask(LOG_GUEST_ERROR, 745 "M25P80: Invalid read id address\n"); 746 } 747 } else { 748 qemu_log_mask(LOG_GUEST_ERROR, 749 "M25P80: Read id (command 0x90/0xAB) is not supported" 750 " by device\n"); 751 } 752 break; 753 default: 754 break; 755 } 756 } 757 758 static void reset_memory(Flash *s) 759 { 760 s->cmd_in_progress = NOP; 761 s->cur_addr = 0; 762 s->ear = 0; 763 s->four_bytes_address_mode = false; 764 s->len = 0; 765 s->needed_bytes = 0; 766 s->pos = 0; 767 s->state = STATE_IDLE; 768 s->write_enable = false; 769 s->reset_enable = false; 770 s->quad_enable = false; 771 772 switch (get_man(s)) { 773 case MAN_NUMONYX: 774 s->volatile_cfg = 0; 775 s->volatile_cfg |= VCFG_DUMMY; 776 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 777 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 778 == NVCFG_XIP_MODE_DISABLED) { 779 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; 780 } 781 s->volatile_cfg |= deposit32(s->volatile_cfg, 782 VCFG_DUMMY_CLK_POS, 783 CFG_DUMMY_CLK_LEN, 784 extract32(s->nonvolatile_cfg, 785 NVCFG_DUMMY_CLK_POS, 786 CFG_DUMMY_CLK_LEN) 787 ); 788 789 s->enh_volatile_cfg = 0; 790 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; 791 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 792 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 793 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 794 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; 795 } 796 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 797 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; 798 } 799 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 800 s->four_bytes_address_mode = true; 801 } 802 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 803 s->ear = s->size / MAX_3BYTES_SIZE - 1; 804 } 805 break; 806 case MAN_MACRONIX: 807 s->volatile_cfg = 0x7; 808 break; 809 case MAN_SPANSION: 810 s->spansion_cr1v = s->spansion_cr1nv; 811 s->spansion_cr2v = s->spansion_cr2nv; 812 s->spansion_cr3v = s->spansion_cr3nv; 813 s->spansion_cr4v = s->spansion_cr4nv; 814 s->quad_enable = extract32(s->spansion_cr1v, 815 SPANSION_QUAD_CFG_POS, 816 SPANSION_QUAD_CFG_LEN 817 ); 818 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 819 SPANSION_ADDR_LEN_POS, 820 SPANSION_ADDR_LEN_LEN 821 ); 822 break; 823 default: 824 break; 825 } 826 827 trace_m25p80_reset_done(s); 828 } 829 830 static uint8_t numonyx_mode(Flash *s) 831 { 832 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { 833 return MODE_QIO; 834 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { 835 return MODE_DIO; 836 } else { 837 return MODE_STD; 838 } 839 } 840 841 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s) 842 { 843 uint8_t num_dummies; 844 uint8_t mode; 845 assert(get_man(s) == MAN_NUMONYX); 846 847 mode = numonyx_mode(s); 848 num_dummies = extract32(s->volatile_cfg, 4, 4); 849 850 if (num_dummies == 0x0 || num_dummies == 0xf) { 851 switch (s->cmd_in_progress) { 852 case QIOR: 853 case QIOR4: 854 num_dummies = 10; 855 break; 856 default: 857 num_dummies = (mode == MODE_QIO) ? 10 : 8; 858 break; 859 } 860 } 861 862 return num_dummies; 863 } 864 865 static void decode_fast_read_cmd(Flash *s) 866 { 867 s->needed_bytes = get_addr_length(s); 868 switch (get_man(s)) { 869 /* Dummy cycles - modeled with bytes writes instead of bits */ 870 case MAN_WINBOND: 871 s->needed_bytes += 8; 872 break; 873 case MAN_NUMONYX: 874 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 875 break; 876 case MAN_MACRONIX: 877 if (extract32(s->volatile_cfg, 6, 2) == 1) { 878 s->needed_bytes += 6; 879 } else { 880 s->needed_bytes += 8; 881 } 882 break; 883 case MAN_SPANSION: 884 s->needed_bytes += extract32(s->spansion_cr2v, 885 SPANSION_DUMMY_CLK_POS, 886 SPANSION_DUMMY_CLK_LEN 887 ); 888 break; 889 default: 890 break; 891 } 892 s->pos = 0; 893 s->len = 0; 894 s->state = STATE_COLLECTING_DATA; 895 } 896 897 static void decode_dio_read_cmd(Flash *s) 898 { 899 s->needed_bytes = get_addr_length(s); 900 /* Dummy cycles modeled with bytes writes instead of bits */ 901 switch (get_man(s)) { 902 case MAN_WINBOND: 903 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 904 break; 905 case MAN_SPANSION: 906 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 907 s->needed_bytes += extract32(s->spansion_cr2v, 908 SPANSION_DUMMY_CLK_POS, 909 SPANSION_DUMMY_CLK_LEN 910 ); 911 break; 912 case MAN_NUMONYX: 913 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 914 break; 915 case MAN_MACRONIX: 916 switch (extract32(s->volatile_cfg, 6, 2)) { 917 case 1: 918 s->needed_bytes += 6; 919 break; 920 case 2: 921 s->needed_bytes += 8; 922 break; 923 default: 924 s->needed_bytes += 4; 925 break; 926 } 927 break; 928 default: 929 break; 930 } 931 s->pos = 0; 932 s->len = 0; 933 s->state = STATE_COLLECTING_DATA; 934 } 935 936 static void decode_qio_read_cmd(Flash *s) 937 { 938 s->needed_bytes = get_addr_length(s); 939 /* Dummy cycles modeled with bytes writes instead of bits */ 940 switch (get_man(s)) { 941 case MAN_WINBOND: 942 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 943 s->needed_bytes += 4; 944 break; 945 case MAN_SPANSION: 946 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 947 s->needed_bytes += extract32(s->spansion_cr2v, 948 SPANSION_DUMMY_CLK_POS, 949 SPANSION_DUMMY_CLK_LEN 950 ); 951 break; 952 case MAN_NUMONYX: 953 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 954 break; 955 case MAN_MACRONIX: 956 switch (extract32(s->volatile_cfg, 6, 2)) { 957 case 1: 958 s->needed_bytes += 4; 959 break; 960 case 2: 961 s->needed_bytes += 8; 962 break; 963 default: 964 s->needed_bytes += 6; 965 break; 966 } 967 break; 968 default: 969 break; 970 } 971 s->pos = 0; 972 s->len = 0; 973 s->state = STATE_COLLECTING_DATA; 974 } 975 976 static void decode_new_cmd(Flash *s, uint32_t value) 977 { 978 int i; 979 980 s->cmd_in_progress = value; 981 trace_m25p80_command_decoded(s, value); 982 983 if (value != RESET_MEMORY) { 984 s->reset_enable = false; 985 } 986 987 switch (value) { 988 989 case ERASE_4K: 990 case ERASE4_4K: 991 case ERASE_32K: 992 case ERASE4_32K: 993 case ERASE_SECTOR: 994 case ERASE4_SECTOR: 995 case PP: 996 case PP4: 997 case DIE_ERASE: 998 case RDID_90: 999 case RDID_AB: 1000 s->needed_bytes = get_addr_length(s); 1001 s->pos = 0; 1002 s->len = 0; 1003 s->state = STATE_COLLECTING_DATA; 1004 break; 1005 case READ: 1006 case READ4: 1007 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1008 s->needed_bytes = get_addr_length(s); 1009 s->pos = 0; 1010 s->len = 0; 1011 s->state = STATE_COLLECTING_DATA; 1012 } else { 1013 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1014 "DIO or QIO mode\n", s->cmd_in_progress); 1015 } 1016 break; 1017 case DPP: 1018 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1019 s->needed_bytes = get_addr_length(s); 1020 s->pos = 0; 1021 s->len = 0; 1022 s->state = STATE_COLLECTING_DATA; 1023 } else { 1024 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1025 "QIO mode\n", s->cmd_in_progress); 1026 } 1027 break; 1028 case QPP: 1029 case QPP_4: 1030 case PP4_4: 1031 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1032 s->needed_bytes = get_addr_length(s); 1033 s->pos = 0; 1034 s->len = 0; 1035 s->state = STATE_COLLECTING_DATA; 1036 } else { 1037 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1038 "DIO mode\n", s->cmd_in_progress); 1039 } 1040 break; 1041 1042 case FAST_READ: 1043 case FAST_READ4: 1044 decode_fast_read_cmd(s); 1045 break; 1046 case DOR: 1047 case DOR4: 1048 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1049 decode_fast_read_cmd(s); 1050 } else { 1051 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1052 "QIO mode\n", s->cmd_in_progress); 1053 } 1054 break; 1055 case QOR: 1056 case QOR4: 1057 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1058 decode_fast_read_cmd(s); 1059 } else { 1060 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1061 "DIO mode\n", s->cmd_in_progress); 1062 } 1063 break; 1064 1065 case DIOR: 1066 case DIOR4: 1067 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1068 decode_dio_read_cmd(s); 1069 } else { 1070 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1071 "QIO mode\n", s->cmd_in_progress); 1072 } 1073 break; 1074 1075 case QIOR: 1076 case QIOR4: 1077 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1078 decode_qio_read_cmd(s); 1079 } else { 1080 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1081 "DIO mode\n", s->cmd_in_progress); 1082 } 1083 break; 1084 1085 case WRSR: 1086 if (s->write_enable) { 1087 switch (get_man(s)) { 1088 case MAN_SPANSION: 1089 s->needed_bytes = 2; 1090 s->state = STATE_COLLECTING_DATA; 1091 break; 1092 case MAN_MACRONIX: 1093 s->needed_bytes = 2; 1094 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1095 break; 1096 default: 1097 s->needed_bytes = 1; 1098 s->state = STATE_COLLECTING_DATA; 1099 } 1100 s->pos = 0; 1101 } 1102 break; 1103 1104 case WRDI: 1105 s->write_enable = false; 1106 break; 1107 case WREN: 1108 s->write_enable = true; 1109 break; 1110 1111 case RDSR: 1112 s->data[0] = (!!s->write_enable) << 1; 1113 if (get_man(s) == MAN_MACRONIX) { 1114 s->data[0] |= (!!s->quad_enable) << 6; 1115 } 1116 s->pos = 0; 1117 s->len = 1; 1118 s->data_read_loop = true; 1119 s->state = STATE_READING_DATA; 1120 break; 1121 1122 case READ_FSR: 1123 s->data[0] = FSR_FLASH_READY; 1124 if (s->four_bytes_address_mode) { 1125 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 1126 } 1127 s->pos = 0; 1128 s->len = 1; 1129 s->data_read_loop = true; 1130 s->state = STATE_READING_DATA; 1131 break; 1132 1133 case JEDEC_READ: 1134 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1135 trace_m25p80_populated_jedec(s); 1136 for (i = 0; i < s->pi->id_len; i++) { 1137 s->data[i] = s->pi->id[i]; 1138 } 1139 for (; i < SPI_NOR_MAX_ID_LEN; i++) { 1140 s->data[i] = 0; 1141 } 1142 1143 s->len = SPI_NOR_MAX_ID_LEN; 1144 s->pos = 0; 1145 s->state = STATE_READING_DATA; 1146 } else { 1147 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read " 1148 "in DIO or QIO mode\n"); 1149 } 1150 break; 1151 1152 case RDCR: 1153 s->data[0] = s->volatile_cfg & 0xFF; 1154 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 1155 s->pos = 0; 1156 s->len = 1; 1157 s->state = STATE_READING_DATA; 1158 break; 1159 1160 case BULK_ERASE_60: 1161 case BULK_ERASE: 1162 if (s->write_enable) { 1163 trace_m25p80_chip_erase(s); 1164 flash_erase(s, 0, BULK_ERASE); 1165 } else { 1166 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 1167 "protect!\n"); 1168 } 1169 break; 1170 case NOP: 1171 break; 1172 case EN_4BYTE_ADDR: 1173 s->four_bytes_address_mode = true; 1174 break; 1175 case EX_4BYTE_ADDR: 1176 s->four_bytes_address_mode = false; 1177 break; 1178 case BRRD: 1179 case EXTEND_ADDR_READ: 1180 s->data[0] = s->ear; 1181 s->pos = 0; 1182 s->len = 1; 1183 s->state = STATE_READING_DATA; 1184 break; 1185 case BRWR: 1186 case EXTEND_ADDR_WRITE: 1187 if (s->write_enable) { 1188 s->needed_bytes = 1; 1189 s->pos = 0; 1190 s->len = 0; 1191 s->state = STATE_COLLECTING_DATA; 1192 } 1193 break; 1194 case RNVCR: 1195 s->data[0] = s->nonvolatile_cfg & 0xFF; 1196 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1197 s->pos = 0; 1198 s->len = 2; 1199 s->state = STATE_READING_DATA; 1200 break; 1201 case WNVCR: 1202 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1203 s->needed_bytes = 2; 1204 s->pos = 0; 1205 s->len = 0; 1206 s->state = STATE_COLLECTING_DATA; 1207 } 1208 break; 1209 case RVCR: 1210 s->data[0] = s->volatile_cfg & 0xFF; 1211 s->pos = 0; 1212 s->len = 1; 1213 s->state = STATE_READING_DATA; 1214 break; 1215 case WVCR: 1216 if (s->write_enable) { 1217 s->needed_bytes = 1; 1218 s->pos = 0; 1219 s->len = 0; 1220 s->state = STATE_COLLECTING_DATA; 1221 } 1222 break; 1223 case REVCR: 1224 s->data[0] = s->enh_volatile_cfg & 0xFF; 1225 s->pos = 0; 1226 s->len = 1; 1227 s->state = STATE_READING_DATA; 1228 break; 1229 case WEVCR: 1230 if (s->write_enable) { 1231 s->needed_bytes = 1; 1232 s->pos = 0; 1233 s->len = 0; 1234 s->state = STATE_COLLECTING_DATA; 1235 } 1236 break; 1237 case RESET_ENABLE: 1238 s->reset_enable = true; 1239 break; 1240 case RESET_MEMORY: 1241 if (s->reset_enable) { 1242 reset_memory(s); 1243 } 1244 break; 1245 case RDCR_EQIO: 1246 switch (get_man(s)) { 1247 case MAN_SPANSION: 1248 s->data[0] = (!!s->quad_enable) << 1; 1249 s->pos = 0; 1250 s->len = 1; 1251 s->state = STATE_READING_DATA; 1252 break; 1253 case MAN_MACRONIX: 1254 s->quad_enable = true; 1255 break; 1256 default: 1257 break; 1258 } 1259 break; 1260 case RSTQIO: 1261 s->quad_enable = false; 1262 break; 1263 default: 1264 s->pos = 0; 1265 s->len = 1; 1266 s->state = STATE_READING_DATA; 1267 s->data_read_loop = true; 1268 s->data[0] = 0; 1269 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1270 break; 1271 } 1272 } 1273 1274 static int m25p80_cs(SSIPeripheral *ss, bool select) 1275 { 1276 Flash *s = M25P80(ss); 1277 1278 if (select) { 1279 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1280 complete_collecting_data(s); 1281 } 1282 s->len = 0; 1283 s->pos = 0; 1284 s->state = STATE_IDLE; 1285 flash_sync_dirty(s, -1); 1286 s->data_read_loop = false; 1287 } 1288 1289 trace_m25p80_select(s, select ? "de" : ""); 1290 1291 return 0; 1292 } 1293 1294 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) 1295 { 1296 Flash *s = M25P80(ss); 1297 uint32_t r = 0; 1298 1299 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, 1300 s->cur_addr, (uint8_t)tx); 1301 1302 switch (s->state) { 1303 1304 case STATE_PAGE_PROGRAM: 1305 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); 1306 flash_write8(s, s->cur_addr, (uint8_t)tx); 1307 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1308 break; 1309 1310 case STATE_READ: 1311 r = s->storage[s->cur_addr]; 1312 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); 1313 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1314 break; 1315 1316 case STATE_COLLECTING_DATA: 1317 case STATE_COLLECTING_VAR_LEN_DATA: 1318 1319 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1320 qemu_log_mask(LOG_GUEST_ERROR, 1321 "M25P80: Write overrun internal data buffer. " 1322 "SPI controller (QEMU emulator or guest driver) " 1323 "is misbehaving\n"); 1324 s->len = s->pos = 0; 1325 s->state = STATE_IDLE; 1326 break; 1327 } 1328 1329 s->data[s->len] = (uint8_t)tx; 1330 s->len++; 1331 1332 if (s->len == s->needed_bytes) { 1333 complete_collecting_data(s); 1334 } 1335 break; 1336 1337 case STATE_READING_DATA: 1338 1339 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1340 qemu_log_mask(LOG_GUEST_ERROR, 1341 "M25P80: Read overrun internal data buffer. " 1342 "SPI controller (QEMU emulator or guest driver) " 1343 "is misbehaving\n"); 1344 s->len = s->pos = 0; 1345 s->state = STATE_IDLE; 1346 break; 1347 } 1348 1349 r = s->data[s->pos]; 1350 trace_m25p80_read_data(s, s->pos, (uint8_t)r); 1351 s->pos++; 1352 if (s->pos == s->len) { 1353 s->pos = 0; 1354 if (!s->data_read_loop) { 1355 s->state = STATE_IDLE; 1356 } 1357 } 1358 break; 1359 1360 default: 1361 case STATE_IDLE: 1362 decode_new_cmd(s, (uint8_t)tx); 1363 break; 1364 } 1365 1366 return r; 1367 } 1368 1369 static void m25p80_realize(SSIPeripheral *ss, Error **errp) 1370 { 1371 Flash *s = M25P80(ss); 1372 M25P80Class *mc = M25P80_GET_CLASS(s); 1373 int ret; 1374 1375 s->pi = mc->pi; 1376 1377 s->size = s->pi->sector_size * s->pi->n_sectors; 1378 s->dirty_page = -1; 1379 1380 if (s->blk) { 1381 uint64_t perm = BLK_PERM_CONSISTENT_READ | 1382 (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE); 1383 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); 1384 if (ret < 0) { 1385 return; 1386 } 1387 1388 trace_m25p80_binding(s); 1389 s->storage = blk_blockalign(s->blk, s->size); 1390 1391 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) { 1392 error_setg(errp, "failed to read the initial flash content"); 1393 return; 1394 } 1395 } else { 1396 trace_m25p80_binding_no_bdrv(s); 1397 s->storage = blk_blockalign(NULL, s->size); 1398 memset(s->storage, 0xFF, s->size); 1399 } 1400 } 1401 1402 static void m25p80_reset(DeviceState *d) 1403 { 1404 Flash *s = M25P80(d); 1405 1406 reset_memory(s); 1407 } 1408 1409 static int m25p80_pre_save(void *opaque) 1410 { 1411 flash_sync_dirty((Flash *)opaque, -1); 1412 1413 return 0; 1414 } 1415 1416 static Property m25p80_properties[] = { 1417 /* This is default value for Micron flash */ 1418 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1419 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1420 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1421 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1422 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1423 DEFINE_PROP_DRIVE("drive", Flash, blk), 1424 DEFINE_PROP_END_OF_LIST(), 1425 }; 1426 1427 static int m25p80_pre_load(void *opaque) 1428 { 1429 Flash *s = (Flash *)opaque; 1430 1431 s->data_read_loop = false; 1432 return 0; 1433 } 1434 1435 static bool m25p80_data_read_loop_needed(void *opaque) 1436 { 1437 Flash *s = (Flash *)opaque; 1438 1439 return s->data_read_loop; 1440 } 1441 1442 static const VMStateDescription vmstate_m25p80_data_read_loop = { 1443 .name = "m25p80/data_read_loop", 1444 .version_id = 1, 1445 .minimum_version_id = 1, 1446 .needed = m25p80_data_read_loop_needed, 1447 .fields = (VMStateField[]) { 1448 VMSTATE_BOOL(data_read_loop, Flash), 1449 VMSTATE_END_OF_LIST() 1450 } 1451 }; 1452 1453 static const VMStateDescription vmstate_m25p80 = { 1454 .name = "m25p80", 1455 .version_id = 0, 1456 .minimum_version_id = 0, 1457 .pre_save = m25p80_pre_save, 1458 .pre_load = m25p80_pre_load, 1459 .fields = (VMStateField[]) { 1460 VMSTATE_UINT8(state, Flash), 1461 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1462 VMSTATE_UINT32(len, Flash), 1463 VMSTATE_UINT32(pos, Flash), 1464 VMSTATE_UINT8(needed_bytes, Flash), 1465 VMSTATE_UINT8(cmd_in_progress, Flash), 1466 VMSTATE_UINT32(cur_addr, Flash), 1467 VMSTATE_BOOL(write_enable, Flash), 1468 VMSTATE_BOOL(reset_enable, Flash), 1469 VMSTATE_UINT8(ear, Flash), 1470 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1471 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1472 VMSTATE_UINT32(volatile_cfg, Flash), 1473 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1474 VMSTATE_BOOL(quad_enable, Flash), 1475 VMSTATE_UINT8(spansion_cr1nv, Flash), 1476 VMSTATE_UINT8(spansion_cr2nv, Flash), 1477 VMSTATE_UINT8(spansion_cr3nv, Flash), 1478 VMSTATE_UINT8(spansion_cr4nv, Flash), 1479 VMSTATE_END_OF_LIST() 1480 }, 1481 .subsections = (const VMStateDescription * []) { 1482 &vmstate_m25p80_data_read_loop, 1483 NULL 1484 } 1485 }; 1486 1487 static void m25p80_class_init(ObjectClass *klass, void *data) 1488 { 1489 DeviceClass *dc = DEVICE_CLASS(klass); 1490 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); 1491 M25P80Class *mc = M25P80_CLASS(klass); 1492 1493 k->realize = m25p80_realize; 1494 k->transfer = m25p80_transfer8; 1495 k->set_cs = m25p80_cs; 1496 k->cs_polarity = SSI_CS_LOW; 1497 dc->vmsd = &vmstate_m25p80; 1498 device_class_set_props(dc, m25p80_properties); 1499 dc->reset = m25p80_reset; 1500 mc->pi = data; 1501 } 1502 1503 static const TypeInfo m25p80_info = { 1504 .name = TYPE_M25P80, 1505 .parent = TYPE_SSI_PERIPHERAL, 1506 .instance_size = sizeof(Flash), 1507 .class_size = sizeof(M25P80Class), 1508 .abstract = true, 1509 }; 1510 1511 static void m25p80_register_types(void) 1512 { 1513 int i; 1514 1515 type_register_static(&m25p80_info); 1516 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1517 TypeInfo ti = { 1518 .name = known_devices[i].part_name, 1519 .parent = TYPE_M25P80, 1520 .class_init = m25p80_class_init, 1521 .class_data = (void *)&known_devices[i], 1522 }; 1523 type_register(&ti); 1524 } 1525 } 1526 1527 type_init(m25p80_register_types) 1528