1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/blockdev.h" 28 #include "hw/ssi/ssi.h" 29 #include "qemu/bitops.h" 30 #include "qemu/log.h" 31 #include "qapi/error.h" 32 33 #ifndef M25P80_ERR_DEBUG 34 #define M25P80_ERR_DEBUG 0 35 #endif 36 37 #define DB_PRINT_L(level, ...) do { \ 38 if (M25P80_ERR_DEBUG > (level)) { \ 39 fprintf(stderr, ": %s: ", __func__); \ 40 fprintf(stderr, ## __VA_ARGS__); \ 41 } \ 42 } while (0); 43 44 /* Fields for FlashPartInfo->flags */ 45 46 /* erase capabilities */ 47 #define ER_4K 1 48 #define ER_32K 2 49 /* set to allow the page program command to write 0s back to 1. Useful for 50 * modelling EEPROM with SPI flash command set 51 */ 52 #define EEPROM 0x100 53 54 /* 16 MiB max in 3 byte address mode */ 55 #define MAX_3BYTES_SIZE 0x1000000 56 57 #define SPI_NOR_MAX_ID_LEN 6 58 59 typedef struct FlashPartInfo { 60 const char *part_name; 61 /* 62 * This array stores the ID bytes. 63 * The first three bytes are the JEDIC ID. 64 * JEDEC ID zero means "no ID" (mostly older chips). 65 */ 66 uint8_t id[SPI_NOR_MAX_ID_LEN]; 67 uint8_t id_len; 68 /* there is confusion between manufacturers as to what a sector is. In this 69 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 70 * command (opcode 0xd8). 71 */ 72 uint32_t sector_size; 73 uint32_t n_sectors; 74 uint32_t page_size; 75 uint16_t flags; 76 } FlashPartInfo; 77 78 /* adapted from linux */ 79 /* Used when the "_ext_id" is two bytes at most */ 80 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 81 .part_name = _part_name,\ 82 .id = {\ 83 ((_jedec_id) >> 16) & 0xff,\ 84 ((_jedec_id) >> 8) & 0xff,\ 85 (_jedec_id) & 0xff,\ 86 ((_ext_id) >> 8) & 0xff,\ 87 (_ext_id) & 0xff,\ 88 },\ 89 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 90 .sector_size = (_sector_size),\ 91 .n_sectors = (_n_sectors),\ 92 .page_size = 256,\ 93 .flags = (_flags), 94 95 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 96 .part_name = _part_name,\ 97 .id = {\ 98 ((_jedec_id) >> 16) & 0xff,\ 99 ((_jedec_id) >> 8) & 0xff,\ 100 (_jedec_id) & 0xff,\ 101 ((_ext_id) >> 16) & 0xff,\ 102 ((_ext_id) >> 8) & 0xff,\ 103 (_ext_id) & 0xff,\ 104 },\ 105 .id_len = 6,\ 106 .sector_size = (_sector_size),\ 107 .n_sectors = (_n_sectors),\ 108 .page_size = 256,\ 109 .flags = (_flags),\ 110 111 #define JEDEC_NUMONYX 0x20 112 #define JEDEC_WINBOND 0xEF 113 #define JEDEC_SPANSION 0x01 114 115 /* Numonyx (Micron) Configuration register macros */ 116 #define VCFG_DUMMY 0x1 117 #define VCFG_WRAP_SEQUENTIAL 0x2 118 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 119 #define NVCFG_XIP_MODE_MASK (7 << 9) 120 #define VCFG_XIP_MODE_ENABLED (1 << 3) 121 #define CFG_DUMMY_CLK_LEN 4 122 #define NVCFG_DUMMY_CLK_POS 12 123 #define VCFG_DUMMY_CLK_POS 4 124 #define EVCFG_OUT_DRIVER_STRENGHT_DEF 7 125 #define EVCFG_VPP_ACCELERATOR (1 << 3) 126 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 127 #define NVCFG_DUAL_IO_MASK (1 << 2) 128 #define EVCFG_DUAL_IO_ENABLED (1 << 6) 129 #define NVCFG_QUAD_IO_MASK (1 << 3) 130 #define EVCFG_QUAD_IO_ENABLED (1 << 7) 131 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 132 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 133 134 /* Numonyx (Micron) Flag Status Register macros */ 135 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 136 #define FSR_FLASH_READY (1 << 7) 137 138 /* Spansion configuration registers macros. */ 139 #define SPANSION_QUAD_CFG_POS 0 140 #define SPANSION_QUAD_CFG_LEN 1 141 #define SPANSION_DUMMY_CLK_POS 0 142 #define SPANSION_DUMMY_CLK_LEN 4 143 #define SPANSION_ADDR_LEN_POS 7 144 #define SPANSION_ADDR_LEN_LEN 1 145 146 /* 147 * Spansion read mode command length in bytes, 148 * the mode is currently not supported. 149 */ 150 151 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 152 153 static const FlashPartInfo known_devices[] = { 154 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 155 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 156 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 157 158 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 159 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 160 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 161 162 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 163 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 164 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 165 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 166 167 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 168 169 /* Atmel EEPROMS - it is assumed, that don't care bit in command 170 * is set to 0. Block protection is not supported. 171 */ 172 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 173 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 174 175 /* EON -- en25xxx */ 176 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 177 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 178 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 179 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 180 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 181 182 /* GigaDevice */ 183 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 184 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 185 186 /* Intel/Numonyx -- xxxs33b */ 187 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 188 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 189 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 190 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 191 192 /* Macronix */ 193 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 194 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 195 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 196 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 197 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 198 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 199 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 200 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 201 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) }, 202 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 203 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 204 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 205 206 /* Micron */ 207 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 208 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 209 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 210 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 211 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 212 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 213 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 214 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 215 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 216 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 217 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 218 { INFO("mt25ql01g", 0x20ba21, 0, 64 << 10, 2048, ER_4K) }, 219 { INFO("mt25qu01g", 0x20bb21, 0, 64 << 10, 2048, ER_4K) }, 220 221 /* Spansion -- single (large) sector size only, at least 222 * for the chips listed here (without boot sectors). 223 */ 224 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 225 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 226 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 227 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 228 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 229 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 230 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 231 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 232 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 233 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 234 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 235 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 236 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 237 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 238 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 239 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 240 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 241 242 /* Spansion -- boot sectors support */ 243 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 244 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 245 246 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 247 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 248 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 249 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 250 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 251 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 252 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 253 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 254 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 255 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 256 257 /* ST Microelectronics -- newer production may have feature updates */ 258 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 259 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 260 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 261 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 262 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 263 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 264 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 265 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 266 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 267 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 268 269 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 270 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 271 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 272 273 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 274 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 275 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 276 277 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 278 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 279 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 280 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 281 282 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 283 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 284 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 285 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 286 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 287 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 288 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 289 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 290 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 291 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 292 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 293 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 294 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 295 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, 296 }; 297 298 typedef enum { 299 NOP = 0, 300 WRSR = 0x1, 301 WRDI = 0x4, 302 RDSR = 0x5, 303 WREN = 0x6, 304 JEDEC_READ = 0x9f, 305 BULK_ERASE = 0xc7, 306 READ_FSR = 0x70, 307 RDCR = 0x15, 308 309 READ = 0x03, 310 READ4 = 0x13, 311 FAST_READ = 0x0b, 312 FAST_READ4 = 0x0c, 313 DOR = 0x3b, 314 DOR4 = 0x3c, 315 QOR = 0x6b, 316 QOR4 = 0x6c, 317 DIOR = 0xbb, 318 DIOR4 = 0xbc, 319 QIOR = 0xeb, 320 QIOR4 = 0xec, 321 322 PP = 0x02, 323 PP4 = 0x12, 324 PP4_4 = 0x3e, 325 DPP = 0xa2, 326 QPP = 0x32, 327 328 ERASE_4K = 0x20, 329 ERASE4_4K = 0x21, 330 ERASE_32K = 0x52, 331 ERASE4_32K = 0x5c, 332 ERASE_SECTOR = 0xd8, 333 ERASE4_SECTOR = 0xdc, 334 335 EN_4BYTE_ADDR = 0xB7, 336 EX_4BYTE_ADDR = 0xE9, 337 338 EXTEND_ADDR_READ = 0xC8, 339 EXTEND_ADDR_WRITE = 0xC5, 340 341 RESET_ENABLE = 0x66, 342 RESET_MEMORY = 0x99, 343 344 /* 345 * Micron: 0x35 - enable QPI 346 * Spansion: 0x35 - read control register 347 */ 348 RDCR_EQIO = 0x35, 349 RSTQIO = 0xf5, 350 351 RNVCR = 0xB5, 352 WNVCR = 0xB1, 353 354 RVCR = 0x85, 355 WVCR = 0x81, 356 357 REVCR = 0x65, 358 WEVCR = 0x61, 359 } FlashCMD; 360 361 typedef enum { 362 STATE_IDLE, 363 STATE_PAGE_PROGRAM, 364 STATE_READ, 365 STATE_COLLECTING_DATA, 366 STATE_COLLECTING_VAR_LEN_DATA, 367 STATE_READING_DATA, 368 } CMDState; 369 370 typedef enum { 371 MAN_SPANSION, 372 MAN_MACRONIX, 373 MAN_NUMONYX, 374 MAN_WINBOND, 375 MAN_GENERIC, 376 } Manufacturer; 377 378 typedef struct Flash { 379 SSISlave parent_obj; 380 381 BlockBackend *blk; 382 383 uint8_t *storage; 384 uint32_t size; 385 int page_size; 386 387 uint8_t state; 388 uint8_t data[16]; 389 uint32_t len; 390 uint32_t pos; 391 uint8_t needed_bytes; 392 uint8_t cmd_in_progress; 393 uint32_t cur_addr; 394 uint32_t nonvolatile_cfg; 395 /* Configuration register for Macronix */ 396 uint32_t volatile_cfg; 397 uint32_t enh_volatile_cfg; 398 /* Spansion cfg registers. */ 399 uint8_t spansion_cr1nv; 400 uint8_t spansion_cr2nv; 401 uint8_t spansion_cr3nv; 402 uint8_t spansion_cr4nv; 403 uint8_t spansion_cr1v; 404 uint8_t spansion_cr2v; 405 uint8_t spansion_cr3v; 406 uint8_t spansion_cr4v; 407 bool write_enable; 408 bool four_bytes_address_mode; 409 bool reset_enable; 410 bool quad_enable; 411 uint8_t ear; 412 413 int64_t dirty_page; 414 415 const FlashPartInfo *pi; 416 417 } Flash; 418 419 typedef struct M25P80Class { 420 SSISlaveClass parent_class; 421 FlashPartInfo *pi; 422 } M25P80Class; 423 424 #define TYPE_M25P80 "m25p80-generic" 425 #define M25P80(obj) \ 426 OBJECT_CHECK(Flash, (obj), TYPE_M25P80) 427 #define M25P80_CLASS(klass) \ 428 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80) 429 #define M25P80_GET_CLASS(obj) \ 430 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80) 431 432 static inline Manufacturer get_man(Flash *s) 433 { 434 switch (s->pi->id[0]) { 435 case 0x20: 436 return MAN_NUMONYX; 437 case 0xEF: 438 return MAN_WINBOND; 439 case 0x01: 440 return MAN_SPANSION; 441 case 0xC2: 442 return MAN_MACRONIX; 443 default: 444 return MAN_GENERIC; 445 } 446 } 447 448 static void blk_sync_complete(void *opaque, int ret) 449 { 450 QEMUIOVector *iov = opaque; 451 452 qemu_iovec_destroy(iov); 453 g_free(iov); 454 455 /* do nothing. Masters do not directly interact with the backing store, 456 * only the working copy so no mutexing required. 457 */ 458 } 459 460 static void flash_sync_page(Flash *s, int page) 461 { 462 QEMUIOVector *iov = g_new(QEMUIOVector, 1); 463 464 if (!s->blk || blk_is_read_only(s->blk)) { 465 return; 466 } 467 468 qemu_iovec_init(iov, 1); 469 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 470 s->pi->page_size); 471 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 472 blk_sync_complete, iov); 473 } 474 475 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 476 { 477 QEMUIOVector *iov = g_new(QEMUIOVector, 1); 478 479 if (!s->blk || blk_is_read_only(s->blk)) { 480 return; 481 } 482 483 assert(!(len % BDRV_SECTOR_SIZE)); 484 qemu_iovec_init(iov, 1); 485 qemu_iovec_add(iov, s->storage + off, len); 486 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 487 } 488 489 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 490 { 491 uint32_t len; 492 uint8_t capa_to_assert = 0; 493 494 switch (cmd) { 495 case ERASE_4K: 496 case ERASE4_4K: 497 len = 4 << 10; 498 capa_to_assert = ER_4K; 499 break; 500 case ERASE_32K: 501 case ERASE4_32K: 502 len = 32 << 10; 503 capa_to_assert = ER_32K; 504 break; 505 case ERASE_SECTOR: 506 case ERASE4_SECTOR: 507 len = s->pi->sector_size; 508 break; 509 case BULK_ERASE: 510 len = s->size; 511 break; 512 default: 513 abort(); 514 } 515 516 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len); 517 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 518 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 519 " device\n", len); 520 } 521 522 if (!s->write_enable) { 523 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 524 return; 525 } 526 memset(s->storage + offset, 0xff, len); 527 flash_sync_area(s, offset, len); 528 } 529 530 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 531 { 532 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 533 flash_sync_page(s, s->dirty_page); 534 s->dirty_page = newpage; 535 } 536 } 537 538 static inline 539 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 540 { 541 uint32_t page = addr / s->pi->page_size; 542 uint8_t prev = s->storage[s->cur_addr]; 543 544 if (!s->write_enable) { 545 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 546 } 547 548 if ((prev ^ data) & data) { 549 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8 550 " -> %" PRIx8 "\n", addr, prev, data); 551 } 552 553 if (s->pi->flags & EEPROM) { 554 s->storage[s->cur_addr] = data; 555 } else { 556 s->storage[s->cur_addr] &= data; 557 } 558 559 flash_sync_dirty(s, page); 560 s->dirty_page = page; 561 } 562 563 static inline int get_addr_length(Flash *s) 564 { 565 /* check if eeprom is in use */ 566 if (s->pi->flags == EEPROM) { 567 return 2; 568 } 569 570 switch (s->cmd_in_progress) { 571 case PP4: 572 case PP4_4: 573 case READ4: 574 case QIOR4: 575 case ERASE4_4K: 576 case ERASE4_32K: 577 case ERASE4_SECTOR: 578 case FAST_READ4: 579 case DOR4: 580 case QOR4: 581 case DIOR4: 582 return 4; 583 default: 584 return s->four_bytes_address_mode ? 4 : 3; 585 } 586 } 587 588 static void complete_collecting_data(Flash *s) 589 { 590 int i, n; 591 592 n = get_addr_length(s); 593 s->cur_addr = (n == 3 ? s->ear : 0); 594 for (i = 0; i < n; ++i) { 595 s->cur_addr <<= 8; 596 s->cur_addr |= s->data[i]; 597 } 598 599 s->cur_addr &= s->size - 1; 600 601 s->state = STATE_IDLE; 602 603 switch (s->cmd_in_progress) { 604 case DPP: 605 case QPP: 606 case PP: 607 case PP4: 608 case PP4_4: 609 s->state = STATE_PAGE_PROGRAM; 610 break; 611 case READ: 612 case READ4: 613 case FAST_READ: 614 case FAST_READ4: 615 case DOR: 616 case DOR4: 617 case QOR: 618 case QOR4: 619 case DIOR: 620 case DIOR4: 621 case QIOR: 622 case QIOR4: 623 s->state = STATE_READ; 624 break; 625 case ERASE_4K: 626 case ERASE4_4K: 627 case ERASE_32K: 628 case ERASE4_32K: 629 case ERASE_SECTOR: 630 case ERASE4_SECTOR: 631 flash_erase(s, s->cur_addr, s->cmd_in_progress); 632 break; 633 case WRSR: 634 switch (get_man(s)) { 635 case MAN_SPANSION: 636 s->quad_enable = !!(s->data[1] & 0x02); 637 break; 638 case MAN_MACRONIX: 639 s->quad_enable = extract32(s->data[0], 6, 1); 640 if (s->len > 1) { 641 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 642 } 643 break; 644 default: 645 break; 646 } 647 if (s->write_enable) { 648 s->write_enable = false; 649 } 650 break; 651 case EXTEND_ADDR_WRITE: 652 s->ear = s->data[0]; 653 break; 654 case WNVCR: 655 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 656 break; 657 case WVCR: 658 s->volatile_cfg = s->data[0]; 659 break; 660 case WEVCR: 661 s->enh_volatile_cfg = s->data[0]; 662 break; 663 default: 664 break; 665 } 666 } 667 668 static void reset_memory(Flash *s) 669 { 670 s->cmd_in_progress = NOP; 671 s->cur_addr = 0; 672 s->ear = 0; 673 s->four_bytes_address_mode = false; 674 s->len = 0; 675 s->needed_bytes = 0; 676 s->pos = 0; 677 s->state = STATE_IDLE; 678 s->write_enable = false; 679 s->reset_enable = false; 680 s->quad_enable = false; 681 682 switch (get_man(s)) { 683 case MAN_NUMONYX: 684 s->volatile_cfg = 0; 685 s->volatile_cfg |= VCFG_DUMMY; 686 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 687 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 688 != NVCFG_XIP_MODE_DISABLED) { 689 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED; 690 } 691 s->volatile_cfg |= deposit32(s->volatile_cfg, 692 VCFG_DUMMY_CLK_POS, 693 CFG_DUMMY_CLK_LEN, 694 extract32(s->nonvolatile_cfg, 695 NVCFG_DUMMY_CLK_POS, 696 CFG_DUMMY_CLK_LEN) 697 ); 698 699 s->enh_volatile_cfg = 0; 700 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF; 701 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 702 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 703 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 704 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; 705 } 706 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 707 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; 708 } 709 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 710 s->four_bytes_address_mode = true; 711 } 712 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 713 s->ear = s->size / MAX_3BYTES_SIZE - 1; 714 } 715 break; 716 case MAN_MACRONIX: 717 s->volatile_cfg = 0x7; 718 break; 719 case MAN_SPANSION: 720 s->spansion_cr1v = s->spansion_cr1nv; 721 s->spansion_cr2v = s->spansion_cr2nv; 722 s->spansion_cr3v = s->spansion_cr3nv; 723 s->spansion_cr4v = s->spansion_cr4nv; 724 s->quad_enable = extract32(s->spansion_cr1v, 725 SPANSION_QUAD_CFG_POS, 726 SPANSION_QUAD_CFG_LEN 727 ); 728 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 729 SPANSION_ADDR_LEN_POS, 730 SPANSION_ADDR_LEN_LEN 731 ); 732 break; 733 default: 734 break; 735 } 736 737 DB_PRINT_L(0, "Reset done.\n"); 738 } 739 740 static void decode_fast_read_cmd(Flash *s) 741 { 742 s->needed_bytes = get_addr_length(s); 743 switch (get_man(s)) { 744 /* Dummy cycles - modeled with bytes writes instead of bits */ 745 case MAN_WINBOND: 746 s->needed_bytes += 8; 747 break; 748 case MAN_NUMONYX: 749 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 750 break; 751 case MAN_MACRONIX: 752 if (extract32(s->volatile_cfg, 6, 2) == 1) { 753 s->needed_bytes += 6; 754 } else { 755 s->needed_bytes += 8; 756 } 757 break; 758 case MAN_SPANSION: 759 s->needed_bytes += extract32(s->spansion_cr2v, 760 SPANSION_DUMMY_CLK_POS, 761 SPANSION_DUMMY_CLK_LEN 762 ); 763 break; 764 default: 765 break; 766 } 767 s->pos = 0; 768 s->len = 0; 769 s->state = STATE_COLLECTING_DATA; 770 } 771 772 static void decode_dio_read_cmd(Flash *s) 773 { 774 s->needed_bytes = get_addr_length(s); 775 /* Dummy cycles modeled with bytes writes instead of bits */ 776 switch (get_man(s)) { 777 case MAN_WINBOND: 778 s->needed_bytes += 8; 779 break; 780 case MAN_SPANSION: 781 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 782 s->needed_bytes += extract32(s->spansion_cr2v, 783 SPANSION_DUMMY_CLK_POS, 784 SPANSION_DUMMY_CLK_LEN 785 ); 786 break; 787 case MAN_NUMONYX: 788 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 789 break; 790 case MAN_MACRONIX: 791 switch (extract32(s->volatile_cfg, 6, 2)) { 792 case 1: 793 s->needed_bytes += 6; 794 break; 795 case 2: 796 s->needed_bytes += 8; 797 break; 798 default: 799 s->needed_bytes += 4; 800 break; 801 } 802 break; 803 default: 804 break; 805 } 806 s->pos = 0; 807 s->len = 0; 808 s->state = STATE_COLLECTING_DATA; 809 } 810 811 static void decode_qio_read_cmd(Flash *s) 812 { 813 s->needed_bytes = get_addr_length(s); 814 /* Dummy cycles modeled with bytes writes instead of bits */ 815 switch (get_man(s)) { 816 case MAN_WINBOND: 817 s->needed_bytes += 8; 818 break; 819 case MAN_SPANSION: 820 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 821 s->needed_bytes += extract32(s->spansion_cr2v, 822 SPANSION_DUMMY_CLK_POS, 823 SPANSION_DUMMY_CLK_LEN 824 ); 825 break; 826 case MAN_NUMONYX: 827 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 828 break; 829 case MAN_MACRONIX: 830 switch (extract32(s->volatile_cfg, 6, 2)) { 831 case 1: 832 s->needed_bytes += 4; 833 break; 834 case 2: 835 s->needed_bytes += 8; 836 break; 837 default: 838 s->needed_bytes += 6; 839 break; 840 } 841 break; 842 default: 843 break; 844 } 845 s->pos = 0; 846 s->len = 0; 847 s->state = STATE_COLLECTING_DATA; 848 } 849 850 static void decode_new_cmd(Flash *s, uint32_t value) 851 { 852 s->cmd_in_progress = value; 853 int i; 854 DB_PRINT_L(0, "decoded new command:%x\n", value); 855 856 if (value != RESET_MEMORY) { 857 s->reset_enable = false; 858 } 859 860 switch (value) { 861 862 case ERASE_4K: 863 case ERASE4_4K: 864 case ERASE_32K: 865 case ERASE4_32K: 866 case ERASE_SECTOR: 867 case ERASE4_SECTOR: 868 case READ: 869 case READ4: 870 case DPP: 871 case QPP: 872 case PP: 873 case PP4: 874 case PP4_4: 875 s->needed_bytes = get_addr_length(s); 876 s->pos = 0; 877 s->len = 0; 878 s->state = STATE_COLLECTING_DATA; 879 break; 880 881 case FAST_READ: 882 case FAST_READ4: 883 case DOR: 884 case DOR4: 885 case QOR: 886 case QOR4: 887 decode_fast_read_cmd(s); 888 break; 889 890 case DIOR: 891 case DIOR4: 892 decode_dio_read_cmd(s); 893 break; 894 895 case QIOR: 896 case QIOR4: 897 decode_qio_read_cmd(s); 898 break; 899 900 case WRSR: 901 if (s->write_enable) { 902 switch (get_man(s)) { 903 case MAN_SPANSION: 904 s->needed_bytes = 2; 905 s->state = STATE_COLLECTING_DATA; 906 break; 907 case MAN_MACRONIX: 908 s->needed_bytes = 2; 909 s->state = STATE_COLLECTING_VAR_LEN_DATA; 910 break; 911 default: 912 s->needed_bytes = 1; 913 s->state = STATE_COLLECTING_DATA; 914 } 915 s->pos = 0; 916 } 917 break; 918 919 case WRDI: 920 s->write_enable = false; 921 break; 922 case WREN: 923 s->write_enable = true; 924 break; 925 926 case RDSR: 927 s->data[0] = (!!s->write_enable) << 1; 928 if (get_man(s) == MAN_MACRONIX) { 929 s->data[0] |= (!!s->quad_enable) << 6; 930 } 931 s->pos = 0; 932 s->len = 1; 933 s->state = STATE_READING_DATA; 934 break; 935 936 case READ_FSR: 937 s->data[0] = FSR_FLASH_READY; 938 if (s->four_bytes_address_mode) { 939 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 940 } 941 s->pos = 0; 942 s->len = 1; 943 s->state = STATE_READING_DATA; 944 break; 945 946 case JEDEC_READ: 947 DB_PRINT_L(0, "populated jedec code\n"); 948 for (i = 0; i < s->pi->id_len; i++) { 949 s->data[i] = s->pi->id[i]; 950 } 951 952 s->len = s->pi->id_len; 953 s->pos = 0; 954 s->state = STATE_READING_DATA; 955 break; 956 957 case RDCR: 958 s->data[0] = s->volatile_cfg & 0xFF; 959 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 960 s->pos = 0; 961 s->len = 1; 962 s->state = STATE_READING_DATA; 963 break; 964 965 case BULK_ERASE: 966 if (s->write_enable) { 967 DB_PRINT_L(0, "chip erase\n"); 968 flash_erase(s, 0, BULK_ERASE); 969 } else { 970 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 971 "protect!\n"); 972 } 973 break; 974 case NOP: 975 break; 976 case EN_4BYTE_ADDR: 977 s->four_bytes_address_mode = true; 978 break; 979 case EX_4BYTE_ADDR: 980 s->four_bytes_address_mode = false; 981 break; 982 case EXTEND_ADDR_READ: 983 s->data[0] = s->ear; 984 s->pos = 0; 985 s->len = 1; 986 s->state = STATE_READING_DATA; 987 break; 988 case EXTEND_ADDR_WRITE: 989 if (s->write_enable) { 990 s->needed_bytes = 1; 991 s->pos = 0; 992 s->len = 0; 993 s->state = STATE_COLLECTING_DATA; 994 } 995 break; 996 case RNVCR: 997 s->data[0] = s->nonvolatile_cfg & 0xFF; 998 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 999 s->pos = 0; 1000 s->len = 2; 1001 s->state = STATE_READING_DATA; 1002 break; 1003 case WNVCR: 1004 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1005 s->needed_bytes = 2; 1006 s->pos = 0; 1007 s->len = 0; 1008 s->state = STATE_COLLECTING_DATA; 1009 } 1010 break; 1011 case RVCR: 1012 s->data[0] = s->volatile_cfg & 0xFF; 1013 s->pos = 0; 1014 s->len = 1; 1015 s->state = STATE_READING_DATA; 1016 break; 1017 case WVCR: 1018 if (s->write_enable) { 1019 s->needed_bytes = 1; 1020 s->pos = 0; 1021 s->len = 0; 1022 s->state = STATE_COLLECTING_DATA; 1023 } 1024 break; 1025 case REVCR: 1026 s->data[0] = s->enh_volatile_cfg & 0xFF; 1027 s->pos = 0; 1028 s->len = 1; 1029 s->state = STATE_READING_DATA; 1030 break; 1031 case WEVCR: 1032 if (s->write_enable) { 1033 s->needed_bytes = 1; 1034 s->pos = 0; 1035 s->len = 0; 1036 s->state = STATE_COLLECTING_DATA; 1037 } 1038 break; 1039 case RESET_ENABLE: 1040 s->reset_enable = true; 1041 break; 1042 case RESET_MEMORY: 1043 if (s->reset_enable) { 1044 reset_memory(s); 1045 } 1046 break; 1047 case RDCR_EQIO: 1048 switch (get_man(s)) { 1049 case MAN_SPANSION: 1050 s->data[0] = (!!s->quad_enable) << 1; 1051 s->pos = 0; 1052 s->len = 1; 1053 s->state = STATE_READING_DATA; 1054 break; 1055 case MAN_MACRONIX: 1056 s->quad_enable = true; 1057 break; 1058 default: 1059 break; 1060 } 1061 break; 1062 case RSTQIO: 1063 s->quad_enable = false; 1064 break; 1065 default: 1066 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1067 break; 1068 } 1069 } 1070 1071 static int m25p80_cs(SSISlave *ss, bool select) 1072 { 1073 Flash *s = M25P80(ss); 1074 1075 if (select) { 1076 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1077 complete_collecting_data(s); 1078 } 1079 s->len = 0; 1080 s->pos = 0; 1081 s->state = STATE_IDLE; 1082 flash_sync_dirty(s, -1); 1083 } 1084 1085 DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); 1086 1087 return 0; 1088 } 1089 1090 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) 1091 { 1092 Flash *s = M25P80(ss); 1093 uint32_t r = 0; 1094 1095 switch (s->state) { 1096 1097 case STATE_PAGE_PROGRAM: 1098 DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n", 1099 s->cur_addr, (uint8_t)tx); 1100 flash_write8(s, s->cur_addr, (uint8_t)tx); 1101 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1102 break; 1103 1104 case STATE_READ: 1105 r = s->storage[s->cur_addr]; 1106 DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr, 1107 (uint8_t)r); 1108 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1109 break; 1110 1111 case STATE_COLLECTING_DATA: 1112 case STATE_COLLECTING_VAR_LEN_DATA: 1113 s->data[s->len] = (uint8_t)tx; 1114 s->len++; 1115 1116 if (s->len == s->needed_bytes) { 1117 complete_collecting_data(s); 1118 } 1119 break; 1120 1121 case STATE_READING_DATA: 1122 r = s->data[s->pos]; 1123 s->pos++; 1124 if (s->pos == s->len) { 1125 s->pos = 0; 1126 s->state = STATE_IDLE; 1127 } 1128 break; 1129 1130 default: 1131 case STATE_IDLE: 1132 decode_new_cmd(s, (uint8_t)tx); 1133 break; 1134 } 1135 1136 return r; 1137 } 1138 1139 static void m25p80_realize(SSISlave *ss, Error **errp) 1140 { 1141 Flash *s = M25P80(ss); 1142 M25P80Class *mc = M25P80_GET_CLASS(s); 1143 1144 s->pi = mc->pi; 1145 1146 s->size = s->pi->sector_size * s->pi->n_sectors; 1147 s->dirty_page = -1; 1148 1149 if (s->blk) { 1150 DB_PRINT_L(0, "Binding to IF_MTD drive\n"); 1151 s->storage = blk_blockalign(s->blk, s->size); 1152 1153 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) { 1154 error_setg(errp, "failed to read the initial flash content"); 1155 return; 1156 } 1157 } else { 1158 DB_PRINT_L(0, "No BDRV - binding to RAM\n"); 1159 s->storage = blk_blockalign(NULL, s->size); 1160 memset(s->storage, 0xFF, s->size); 1161 } 1162 } 1163 1164 static void m25p80_reset(DeviceState *d) 1165 { 1166 Flash *s = M25P80(d); 1167 1168 reset_memory(s); 1169 } 1170 1171 static void m25p80_pre_save(void *opaque) 1172 { 1173 flash_sync_dirty((Flash *)opaque, -1); 1174 } 1175 1176 static Property m25p80_properties[] = { 1177 /* This is default value for Micron flash */ 1178 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1179 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1180 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1181 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1182 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1183 DEFINE_PROP_DRIVE("drive", Flash, blk), 1184 DEFINE_PROP_END_OF_LIST(), 1185 }; 1186 1187 static const VMStateDescription vmstate_m25p80 = { 1188 .name = "xilinx_spi", 1189 .version_id = 3, 1190 .minimum_version_id = 1, 1191 .pre_save = m25p80_pre_save, 1192 .fields = (VMStateField[]) { 1193 VMSTATE_UINT8(state, Flash), 1194 VMSTATE_UINT8_ARRAY(data, Flash, 16), 1195 VMSTATE_UINT32(len, Flash), 1196 VMSTATE_UINT32(pos, Flash), 1197 VMSTATE_UINT8(needed_bytes, Flash), 1198 VMSTATE_UINT8(cmd_in_progress, Flash), 1199 VMSTATE_UNUSED(4), 1200 VMSTATE_UINT32(cur_addr, Flash), 1201 VMSTATE_BOOL(write_enable, Flash), 1202 VMSTATE_BOOL_V(reset_enable, Flash, 2), 1203 VMSTATE_UINT8_V(ear, Flash, 2), 1204 VMSTATE_BOOL_V(four_bytes_address_mode, Flash, 2), 1205 VMSTATE_UINT32_V(nonvolatile_cfg, Flash, 2), 1206 VMSTATE_UINT32_V(volatile_cfg, Flash, 2), 1207 VMSTATE_UINT32_V(enh_volatile_cfg, Flash, 2), 1208 VMSTATE_BOOL_V(quad_enable, Flash, 3), 1209 VMSTATE_UINT8_V(spansion_cr1nv, Flash, 3), 1210 VMSTATE_UINT8_V(spansion_cr2nv, Flash, 3), 1211 VMSTATE_UINT8_V(spansion_cr3nv, Flash, 3), 1212 VMSTATE_UINT8_V(spansion_cr4nv, Flash, 3), 1213 VMSTATE_END_OF_LIST() 1214 } 1215 }; 1216 1217 static void m25p80_class_init(ObjectClass *klass, void *data) 1218 { 1219 DeviceClass *dc = DEVICE_CLASS(klass); 1220 SSISlaveClass *k = SSI_SLAVE_CLASS(klass); 1221 M25P80Class *mc = M25P80_CLASS(klass); 1222 1223 k->realize = m25p80_realize; 1224 k->transfer = m25p80_transfer8; 1225 k->set_cs = m25p80_cs; 1226 k->cs_polarity = SSI_CS_LOW; 1227 dc->vmsd = &vmstate_m25p80; 1228 dc->props = m25p80_properties; 1229 dc->reset = m25p80_reset; 1230 mc->pi = data; 1231 } 1232 1233 static const TypeInfo m25p80_info = { 1234 .name = TYPE_M25P80, 1235 .parent = TYPE_SSI_SLAVE, 1236 .instance_size = sizeof(Flash), 1237 .class_size = sizeof(M25P80Class), 1238 .abstract = true, 1239 }; 1240 1241 static void m25p80_register_types(void) 1242 { 1243 int i; 1244 1245 type_register_static(&m25p80_info); 1246 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1247 TypeInfo ti = { 1248 .name = known_devices[i].part_name, 1249 .parent = TYPE_M25P80, 1250 .class_init = m25p80_class_init, 1251 .class_data = (void *)&known_devices[i], 1252 }; 1253 type_register(&ti); 1254 } 1255 } 1256 1257 type_init(m25p80_register_types) 1258