1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/ssi/ssi.h" 29 #include "migration/vmstate.h" 30 #include "qemu/bitops.h" 31 #include "qemu/log.h" 32 #include "qemu/module.h" 33 #include "qemu/error-report.h" 34 #include "qapi/error.h" 35 #include "trace.h" 36 37 /* Fields for FlashPartInfo->flags */ 38 39 /* erase capabilities */ 40 #define ER_4K 1 41 #define ER_32K 2 42 /* set to allow the page program command to write 0s back to 1. Useful for 43 * modelling EEPROM with SPI flash command set 44 */ 45 #define EEPROM 0x100 46 47 /* 16 MiB max in 3 byte address mode */ 48 #define MAX_3BYTES_SIZE 0x1000000 49 50 #define SPI_NOR_MAX_ID_LEN 6 51 52 typedef struct FlashPartInfo { 53 const char *part_name; 54 /* 55 * This array stores the ID bytes. 56 * The first three bytes are the JEDIC ID. 57 * JEDEC ID zero means "no ID" (mostly older chips). 58 */ 59 uint8_t id[SPI_NOR_MAX_ID_LEN]; 60 uint8_t id_len; 61 /* there is confusion between manufacturers as to what a sector is. In this 62 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 63 * command (opcode 0xd8). 64 */ 65 uint32_t sector_size; 66 uint32_t n_sectors; 67 uint32_t page_size; 68 uint16_t flags; 69 /* 70 * Big sized spi nor are often stacked devices, thus sometime 71 * replace chip erase with die erase. 72 * This field inform how many die is in the chip. 73 */ 74 uint8_t die_cnt; 75 } FlashPartInfo; 76 77 /* adapted from linux */ 78 /* Used when the "_ext_id" is two bytes at most */ 79 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 80 .part_name = _part_name,\ 81 .id = {\ 82 ((_jedec_id) >> 16) & 0xff,\ 83 ((_jedec_id) >> 8) & 0xff,\ 84 (_jedec_id) & 0xff,\ 85 ((_ext_id) >> 8) & 0xff,\ 86 (_ext_id) & 0xff,\ 87 },\ 88 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 89 .sector_size = (_sector_size),\ 90 .n_sectors = (_n_sectors),\ 91 .page_size = 256,\ 92 .flags = (_flags),\ 93 .die_cnt = 0 94 95 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 96 .part_name = _part_name,\ 97 .id = {\ 98 ((_jedec_id) >> 16) & 0xff,\ 99 ((_jedec_id) >> 8) & 0xff,\ 100 (_jedec_id) & 0xff,\ 101 ((_ext_id) >> 16) & 0xff,\ 102 ((_ext_id) >> 8) & 0xff,\ 103 (_ext_id) & 0xff,\ 104 },\ 105 .id_len = 6,\ 106 .sector_size = (_sector_size),\ 107 .n_sectors = (_n_sectors),\ 108 .page_size = 256,\ 109 .flags = (_flags),\ 110 .die_cnt = 0 111 112 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ 113 _flags, _die_cnt)\ 114 .part_name = _part_name,\ 115 .id = {\ 116 ((_jedec_id) >> 16) & 0xff,\ 117 ((_jedec_id) >> 8) & 0xff,\ 118 (_jedec_id) & 0xff,\ 119 ((_ext_id) >> 8) & 0xff,\ 120 (_ext_id) & 0xff,\ 121 },\ 122 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 123 .sector_size = (_sector_size),\ 124 .n_sectors = (_n_sectors),\ 125 .page_size = 256,\ 126 .flags = (_flags),\ 127 .die_cnt = _die_cnt 128 129 #define JEDEC_NUMONYX 0x20 130 #define JEDEC_WINBOND 0xEF 131 #define JEDEC_SPANSION 0x01 132 133 /* Numonyx (Micron) Configuration register macros */ 134 #define VCFG_DUMMY 0x1 135 #define VCFG_WRAP_SEQUENTIAL 0x2 136 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 137 #define NVCFG_XIP_MODE_MASK (7 << 9) 138 #define VCFG_XIP_MODE_ENABLED (1 << 3) 139 #define CFG_DUMMY_CLK_LEN 4 140 #define NVCFG_DUMMY_CLK_POS 12 141 #define VCFG_DUMMY_CLK_POS 4 142 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 143 #define EVCFG_VPP_ACCELERATOR (1 << 3) 144 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 145 #define NVCFG_DUAL_IO_MASK (1 << 2) 146 #define EVCFG_DUAL_IO_ENABLED (1 << 6) 147 #define NVCFG_QUAD_IO_MASK (1 << 3) 148 #define EVCFG_QUAD_IO_ENABLED (1 << 7) 149 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 150 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 151 152 /* Numonyx (Micron) Flag Status Register macros */ 153 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 154 #define FSR_FLASH_READY (1 << 7) 155 156 /* Spansion configuration registers macros. */ 157 #define SPANSION_QUAD_CFG_POS 0 158 #define SPANSION_QUAD_CFG_LEN 1 159 #define SPANSION_DUMMY_CLK_POS 0 160 #define SPANSION_DUMMY_CLK_LEN 4 161 #define SPANSION_ADDR_LEN_POS 7 162 #define SPANSION_ADDR_LEN_LEN 1 163 164 /* 165 * Spansion read mode command length in bytes, 166 * the mode is currently not supported. 167 */ 168 169 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 170 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 171 172 static const FlashPartInfo known_devices[] = { 173 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 174 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 175 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 176 177 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 178 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 179 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 180 181 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 182 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 183 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 184 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 185 186 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 187 188 /* Atmel EEPROMS - it is assumed, that don't care bit in command 189 * is set to 0. Block protection is not supported. 190 */ 191 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 192 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 193 194 /* EON -- en25xxx */ 195 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 196 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 197 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 198 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 199 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 200 201 /* GigaDevice */ 202 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 203 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 204 205 /* Intel/Numonyx -- xxxs33b */ 206 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 207 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 208 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 209 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 210 211 /* Macronix */ 212 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 213 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 214 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 215 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 216 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 217 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 218 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 219 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 220 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) }, 221 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 222 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 223 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 224 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 225 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 226 227 /* Micron */ 228 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 229 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 230 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 231 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 232 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 233 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 234 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 235 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 236 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, 237 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 238 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 239 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 240 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 241 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, 242 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, 243 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 244 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 245 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 246 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 247 248 /* Spansion -- single (large) sector size only, at least 249 * for the chips listed here (without boot sectors). 250 */ 251 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 252 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 253 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 254 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 255 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 256 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 257 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 258 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 259 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 260 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 261 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 262 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 263 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 264 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 265 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 266 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 267 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 268 269 /* Spansion -- boot sectors support */ 270 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 271 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 272 273 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 274 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 275 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 276 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 277 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 278 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 279 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 280 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 281 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 282 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 283 284 /* ST Microelectronics -- newer production may have feature updates */ 285 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 286 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 287 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 288 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 289 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 290 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 291 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 292 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 293 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 294 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 295 296 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 297 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 298 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 299 300 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 301 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 302 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 303 304 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 305 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 306 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 307 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 308 309 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 310 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 311 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 312 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 313 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 314 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 315 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 316 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 317 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 318 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 319 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 320 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 321 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 322 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, 323 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) }, 324 }; 325 326 typedef enum { 327 NOP = 0, 328 WRSR = 0x1, 329 WRDI = 0x4, 330 RDSR = 0x5, 331 WREN = 0x6, 332 BRRD = 0x16, 333 BRWR = 0x17, 334 JEDEC_READ = 0x9f, 335 BULK_ERASE_60 = 0x60, 336 BULK_ERASE = 0xc7, 337 READ_FSR = 0x70, 338 RDCR = 0x15, 339 340 READ = 0x03, 341 READ4 = 0x13, 342 FAST_READ = 0x0b, 343 FAST_READ4 = 0x0c, 344 DOR = 0x3b, 345 DOR4 = 0x3c, 346 QOR = 0x6b, 347 QOR4 = 0x6c, 348 DIOR = 0xbb, 349 DIOR4 = 0xbc, 350 QIOR = 0xeb, 351 QIOR4 = 0xec, 352 353 PP = 0x02, 354 PP4 = 0x12, 355 PP4_4 = 0x3e, 356 DPP = 0xa2, 357 QPP = 0x32, 358 QPP_4 = 0x34, 359 RDID_90 = 0x90, 360 RDID_AB = 0xab, 361 362 ERASE_4K = 0x20, 363 ERASE4_4K = 0x21, 364 ERASE_32K = 0x52, 365 ERASE4_32K = 0x5c, 366 ERASE_SECTOR = 0xd8, 367 ERASE4_SECTOR = 0xdc, 368 369 EN_4BYTE_ADDR = 0xB7, 370 EX_4BYTE_ADDR = 0xE9, 371 372 EXTEND_ADDR_READ = 0xC8, 373 EXTEND_ADDR_WRITE = 0xC5, 374 375 RESET_ENABLE = 0x66, 376 RESET_MEMORY = 0x99, 377 378 /* 379 * Micron: 0x35 - enable QPI 380 * Spansion: 0x35 - read control register 381 */ 382 RDCR_EQIO = 0x35, 383 RSTQIO = 0xf5, 384 385 RNVCR = 0xB5, 386 WNVCR = 0xB1, 387 388 RVCR = 0x85, 389 WVCR = 0x81, 390 391 REVCR = 0x65, 392 WEVCR = 0x61, 393 394 DIE_ERASE = 0xC4, 395 } FlashCMD; 396 397 typedef enum { 398 STATE_IDLE, 399 STATE_PAGE_PROGRAM, 400 STATE_READ, 401 STATE_COLLECTING_DATA, 402 STATE_COLLECTING_VAR_LEN_DATA, 403 STATE_READING_DATA, 404 } CMDState; 405 406 typedef enum { 407 MAN_SPANSION, 408 MAN_MACRONIX, 409 MAN_NUMONYX, 410 MAN_WINBOND, 411 MAN_SST, 412 MAN_GENERIC, 413 } Manufacturer; 414 415 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 416 417 typedef struct Flash { 418 SSISlave parent_obj; 419 420 BlockBackend *blk; 421 422 uint8_t *storage; 423 uint32_t size; 424 int page_size; 425 426 uint8_t state; 427 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 428 uint32_t len; 429 uint32_t pos; 430 bool data_read_loop; 431 uint8_t needed_bytes; 432 uint8_t cmd_in_progress; 433 uint32_t cur_addr; 434 uint32_t nonvolatile_cfg; 435 /* Configuration register for Macronix */ 436 uint32_t volatile_cfg; 437 uint32_t enh_volatile_cfg; 438 /* Spansion cfg registers. */ 439 uint8_t spansion_cr1nv; 440 uint8_t spansion_cr2nv; 441 uint8_t spansion_cr3nv; 442 uint8_t spansion_cr4nv; 443 uint8_t spansion_cr1v; 444 uint8_t spansion_cr2v; 445 uint8_t spansion_cr3v; 446 uint8_t spansion_cr4v; 447 bool write_enable; 448 bool four_bytes_address_mode; 449 bool reset_enable; 450 bool quad_enable; 451 uint8_t ear; 452 453 int64_t dirty_page; 454 455 const FlashPartInfo *pi; 456 457 } Flash; 458 459 typedef struct M25P80Class { 460 SSISlaveClass parent_class; 461 FlashPartInfo *pi; 462 } M25P80Class; 463 464 #define TYPE_M25P80 "m25p80-generic" 465 #define M25P80(obj) \ 466 OBJECT_CHECK(Flash, (obj), TYPE_M25P80) 467 #define M25P80_CLASS(klass) \ 468 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80) 469 #define M25P80_GET_CLASS(obj) \ 470 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80) 471 472 static inline Manufacturer get_man(Flash *s) 473 { 474 switch (s->pi->id[0]) { 475 case 0x20: 476 return MAN_NUMONYX; 477 case 0xEF: 478 return MAN_WINBOND; 479 case 0x01: 480 return MAN_SPANSION; 481 case 0xC2: 482 return MAN_MACRONIX; 483 case 0xBF: 484 return MAN_SST; 485 default: 486 return MAN_GENERIC; 487 } 488 } 489 490 static void blk_sync_complete(void *opaque, int ret) 491 { 492 QEMUIOVector *iov = opaque; 493 494 qemu_iovec_destroy(iov); 495 g_free(iov); 496 497 /* do nothing. Masters do not directly interact with the backing store, 498 * only the working copy so no mutexing required. 499 */ 500 } 501 502 static void flash_sync_page(Flash *s, int page) 503 { 504 QEMUIOVector *iov; 505 506 if (!s->blk || blk_is_read_only(s->blk)) { 507 return; 508 } 509 510 iov = g_new(QEMUIOVector, 1); 511 qemu_iovec_init(iov, 1); 512 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 513 s->pi->page_size); 514 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 515 blk_sync_complete, iov); 516 } 517 518 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 519 { 520 QEMUIOVector *iov; 521 522 if (!s->blk || blk_is_read_only(s->blk)) { 523 return; 524 } 525 526 assert(!(len % BDRV_SECTOR_SIZE)); 527 iov = g_new(QEMUIOVector, 1); 528 qemu_iovec_init(iov, 1); 529 qemu_iovec_add(iov, s->storage + off, len); 530 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 531 } 532 533 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 534 { 535 uint32_t len; 536 uint8_t capa_to_assert = 0; 537 538 switch (cmd) { 539 case ERASE_4K: 540 case ERASE4_4K: 541 len = 4 * KiB; 542 capa_to_assert = ER_4K; 543 break; 544 case ERASE_32K: 545 case ERASE4_32K: 546 len = 32 * KiB; 547 capa_to_assert = ER_32K; 548 break; 549 case ERASE_SECTOR: 550 case ERASE4_SECTOR: 551 len = s->pi->sector_size; 552 break; 553 case BULK_ERASE: 554 len = s->size; 555 break; 556 case DIE_ERASE: 557 if (s->pi->die_cnt) { 558 len = s->size / s->pi->die_cnt; 559 offset = offset & (~(len - 1)); 560 } else { 561 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" 562 " by device\n"); 563 return; 564 } 565 break; 566 default: 567 abort(); 568 } 569 570 trace_m25p80_flash_erase(s, offset, len); 571 572 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 573 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 574 " device\n", len); 575 } 576 577 if (!s->write_enable) { 578 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 579 return; 580 } 581 memset(s->storage + offset, 0xff, len); 582 flash_sync_area(s, offset, len); 583 } 584 585 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 586 { 587 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 588 flash_sync_page(s, s->dirty_page); 589 s->dirty_page = newpage; 590 } 591 } 592 593 static inline 594 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 595 { 596 uint32_t page = addr / s->pi->page_size; 597 uint8_t prev = s->storage[s->cur_addr]; 598 599 if (!s->write_enable) { 600 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 601 } 602 603 if ((prev ^ data) & data) { 604 trace_m25p80_programming_zero_to_one(s, addr, prev, data); 605 } 606 607 if (s->pi->flags & EEPROM) { 608 s->storage[s->cur_addr] = data; 609 } else { 610 s->storage[s->cur_addr] &= data; 611 } 612 613 flash_sync_dirty(s, page); 614 s->dirty_page = page; 615 } 616 617 static inline int get_addr_length(Flash *s) 618 { 619 /* check if eeprom is in use */ 620 if (s->pi->flags == EEPROM) { 621 return 2; 622 } 623 624 switch (s->cmd_in_progress) { 625 case PP4: 626 case PP4_4: 627 case QPP_4: 628 case READ4: 629 case QIOR4: 630 case ERASE4_4K: 631 case ERASE4_32K: 632 case ERASE4_SECTOR: 633 case FAST_READ4: 634 case DOR4: 635 case QOR4: 636 case DIOR4: 637 return 4; 638 default: 639 return s->four_bytes_address_mode ? 4 : 3; 640 } 641 } 642 643 static void complete_collecting_data(Flash *s) 644 { 645 int i, n; 646 647 n = get_addr_length(s); 648 s->cur_addr = (n == 3 ? s->ear : 0); 649 for (i = 0; i < n; ++i) { 650 s->cur_addr <<= 8; 651 s->cur_addr |= s->data[i]; 652 } 653 654 s->cur_addr &= s->size - 1; 655 656 s->state = STATE_IDLE; 657 658 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, 659 s->cur_addr); 660 661 switch (s->cmd_in_progress) { 662 case DPP: 663 case QPP: 664 case QPP_4: 665 case PP: 666 case PP4: 667 case PP4_4: 668 s->state = STATE_PAGE_PROGRAM; 669 break; 670 case READ: 671 case READ4: 672 case FAST_READ: 673 case FAST_READ4: 674 case DOR: 675 case DOR4: 676 case QOR: 677 case QOR4: 678 case DIOR: 679 case DIOR4: 680 case QIOR: 681 case QIOR4: 682 s->state = STATE_READ; 683 break; 684 case ERASE_4K: 685 case ERASE4_4K: 686 case ERASE_32K: 687 case ERASE4_32K: 688 case ERASE_SECTOR: 689 case ERASE4_SECTOR: 690 case DIE_ERASE: 691 flash_erase(s, s->cur_addr, s->cmd_in_progress); 692 break; 693 case WRSR: 694 switch (get_man(s)) { 695 case MAN_SPANSION: 696 s->quad_enable = !!(s->data[1] & 0x02); 697 break; 698 case MAN_MACRONIX: 699 s->quad_enable = extract32(s->data[0], 6, 1); 700 if (s->len > 1) { 701 s->volatile_cfg = s->data[1]; 702 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 703 } 704 break; 705 default: 706 break; 707 } 708 if (s->write_enable) { 709 s->write_enable = false; 710 } 711 break; 712 case BRWR: 713 case EXTEND_ADDR_WRITE: 714 s->ear = s->data[0]; 715 break; 716 case WNVCR: 717 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 718 break; 719 case WVCR: 720 s->volatile_cfg = s->data[0]; 721 break; 722 case WEVCR: 723 s->enh_volatile_cfg = s->data[0]; 724 break; 725 case RDID_90: 726 case RDID_AB: 727 if (get_man(s) == MAN_SST) { 728 if (s->cur_addr <= 1) { 729 if (s->cur_addr) { 730 s->data[0] = s->pi->id[2]; 731 s->data[1] = s->pi->id[0]; 732 } else { 733 s->data[0] = s->pi->id[0]; 734 s->data[1] = s->pi->id[2]; 735 } 736 s->pos = 0; 737 s->len = 2; 738 s->data_read_loop = true; 739 s->state = STATE_READING_DATA; 740 } else { 741 qemu_log_mask(LOG_GUEST_ERROR, 742 "M25P80: Invalid read id address\n"); 743 } 744 } else { 745 qemu_log_mask(LOG_GUEST_ERROR, 746 "M25P80: Read id (command 0x90/0xAB) is not supported" 747 " by device\n"); 748 } 749 break; 750 default: 751 break; 752 } 753 } 754 755 static void reset_memory(Flash *s) 756 { 757 s->cmd_in_progress = NOP; 758 s->cur_addr = 0; 759 s->ear = 0; 760 s->four_bytes_address_mode = false; 761 s->len = 0; 762 s->needed_bytes = 0; 763 s->pos = 0; 764 s->state = STATE_IDLE; 765 s->write_enable = false; 766 s->reset_enable = false; 767 s->quad_enable = false; 768 769 switch (get_man(s)) { 770 case MAN_NUMONYX: 771 s->volatile_cfg = 0; 772 s->volatile_cfg |= VCFG_DUMMY; 773 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 774 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 775 != NVCFG_XIP_MODE_DISABLED) { 776 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED; 777 } 778 s->volatile_cfg |= deposit32(s->volatile_cfg, 779 VCFG_DUMMY_CLK_POS, 780 CFG_DUMMY_CLK_LEN, 781 extract32(s->nonvolatile_cfg, 782 NVCFG_DUMMY_CLK_POS, 783 CFG_DUMMY_CLK_LEN) 784 ); 785 786 s->enh_volatile_cfg = 0; 787 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; 788 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 789 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 790 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 791 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; 792 } 793 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 794 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; 795 } 796 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 797 s->four_bytes_address_mode = true; 798 } 799 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 800 s->ear = s->size / MAX_3BYTES_SIZE - 1; 801 } 802 break; 803 case MAN_MACRONIX: 804 s->volatile_cfg = 0x7; 805 break; 806 case MAN_SPANSION: 807 s->spansion_cr1v = s->spansion_cr1nv; 808 s->spansion_cr2v = s->spansion_cr2nv; 809 s->spansion_cr3v = s->spansion_cr3nv; 810 s->spansion_cr4v = s->spansion_cr4nv; 811 s->quad_enable = extract32(s->spansion_cr1v, 812 SPANSION_QUAD_CFG_POS, 813 SPANSION_QUAD_CFG_LEN 814 ); 815 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 816 SPANSION_ADDR_LEN_POS, 817 SPANSION_ADDR_LEN_LEN 818 ); 819 break; 820 default: 821 break; 822 } 823 824 trace_m25p80_reset_done(s); 825 } 826 827 static void decode_fast_read_cmd(Flash *s) 828 { 829 s->needed_bytes = get_addr_length(s); 830 switch (get_man(s)) { 831 /* Dummy cycles - modeled with bytes writes instead of bits */ 832 case MAN_WINBOND: 833 s->needed_bytes += 8; 834 break; 835 case MAN_NUMONYX: 836 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 837 break; 838 case MAN_MACRONIX: 839 if (extract32(s->volatile_cfg, 6, 2) == 1) { 840 s->needed_bytes += 6; 841 } else { 842 s->needed_bytes += 8; 843 } 844 break; 845 case MAN_SPANSION: 846 s->needed_bytes += extract32(s->spansion_cr2v, 847 SPANSION_DUMMY_CLK_POS, 848 SPANSION_DUMMY_CLK_LEN 849 ); 850 break; 851 default: 852 break; 853 } 854 s->pos = 0; 855 s->len = 0; 856 s->state = STATE_COLLECTING_DATA; 857 } 858 859 static void decode_dio_read_cmd(Flash *s) 860 { 861 s->needed_bytes = get_addr_length(s); 862 /* Dummy cycles modeled with bytes writes instead of bits */ 863 switch (get_man(s)) { 864 case MAN_WINBOND: 865 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 866 break; 867 case MAN_SPANSION: 868 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 869 s->needed_bytes += extract32(s->spansion_cr2v, 870 SPANSION_DUMMY_CLK_POS, 871 SPANSION_DUMMY_CLK_LEN 872 ); 873 break; 874 case MAN_NUMONYX: 875 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 876 break; 877 case MAN_MACRONIX: 878 switch (extract32(s->volatile_cfg, 6, 2)) { 879 case 1: 880 s->needed_bytes += 6; 881 break; 882 case 2: 883 s->needed_bytes += 8; 884 break; 885 default: 886 s->needed_bytes += 4; 887 break; 888 } 889 break; 890 default: 891 break; 892 } 893 s->pos = 0; 894 s->len = 0; 895 s->state = STATE_COLLECTING_DATA; 896 } 897 898 static void decode_qio_read_cmd(Flash *s) 899 { 900 s->needed_bytes = get_addr_length(s); 901 /* Dummy cycles modeled with bytes writes instead of bits */ 902 switch (get_man(s)) { 903 case MAN_WINBOND: 904 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 905 s->needed_bytes += 4; 906 break; 907 case MAN_SPANSION: 908 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 909 s->needed_bytes += extract32(s->spansion_cr2v, 910 SPANSION_DUMMY_CLK_POS, 911 SPANSION_DUMMY_CLK_LEN 912 ); 913 break; 914 case MAN_NUMONYX: 915 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 916 break; 917 case MAN_MACRONIX: 918 switch (extract32(s->volatile_cfg, 6, 2)) { 919 case 1: 920 s->needed_bytes += 4; 921 break; 922 case 2: 923 s->needed_bytes += 8; 924 break; 925 default: 926 s->needed_bytes += 6; 927 break; 928 } 929 break; 930 default: 931 break; 932 } 933 s->pos = 0; 934 s->len = 0; 935 s->state = STATE_COLLECTING_DATA; 936 } 937 938 static void decode_new_cmd(Flash *s, uint32_t value) 939 { 940 int i; 941 942 s->cmd_in_progress = value; 943 trace_m25p80_command_decoded(s, value); 944 945 if (value != RESET_MEMORY) { 946 s->reset_enable = false; 947 } 948 949 switch (value) { 950 951 case ERASE_4K: 952 case ERASE4_4K: 953 case ERASE_32K: 954 case ERASE4_32K: 955 case ERASE_SECTOR: 956 case ERASE4_SECTOR: 957 case READ: 958 case READ4: 959 case DPP: 960 case QPP: 961 case QPP_4: 962 case PP: 963 case PP4: 964 case PP4_4: 965 case DIE_ERASE: 966 case RDID_90: 967 case RDID_AB: 968 s->needed_bytes = get_addr_length(s); 969 s->pos = 0; 970 s->len = 0; 971 s->state = STATE_COLLECTING_DATA; 972 break; 973 974 case FAST_READ: 975 case FAST_READ4: 976 case DOR: 977 case DOR4: 978 case QOR: 979 case QOR4: 980 decode_fast_read_cmd(s); 981 break; 982 983 case DIOR: 984 case DIOR4: 985 decode_dio_read_cmd(s); 986 break; 987 988 case QIOR: 989 case QIOR4: 990 decode_qio_read_cmd(s); 991 break; 992 993 case WRSR: 994 if (s->write_enable) { 995 switch (get_man(s)) { 996 case MAN_SPANSION: 997 s->needed_bytes = 2; 998 s->state = STATE_COLLECTING_DATA; 999 break; 1000 case MAN_MACRONIX: 1001 s->needed_bytes = 2; 1002 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1003 break; 1004 default: 1005 s->needed_bytes = 1; 1006 s->state = STATE_COLLECTING_DATA; 1007 } 1008 s->pos = 0; 1009 } 1010 break; 1011 1012 case WRDI: 1013 s->write_enable = false; 1014 break; 1015 case WREN: 1016 s->write_enable = true; 1017 break; 1018 1019 case RDSR: 1020 s->data[0] = (!!s->write_enable) << 1; 1021 if (get_man(s) == MAN_MACRONIX) { 1022 s->data[0] |= (!!s->quad_enable) << 6; 1023 } 1024 s->pos = 0; 1025 s->len = 1; 1026 s->data_read_loop = true; 1027 s->state = STATE_READING_DATA; 1028 break; 1029 1030 case READ_FSR: 1031 s->data[0] = FSR_FLASH_READY; 1032 if (s->four_bytes_address_mode) { 1033 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 1034 } 1035 s->pos = 0; 1036 s->len = 1; 1037 s->data_read_loop = true; 1038 s->state = STATE_READING_DATA; 1039 break; 1040 1041 case JEDEC_READ: 1042 trace_m25p80_populated_jedec(s); 1043 for (i = 0; i < s->pi->id_len; i++) { 1044 s->data[i] = s->pi->id[i]; 1045 } 1046 for (; i < SPI_NOR_MAX_ID_LEN; i++) { 1047 s->data[i] = 0; 1048 } 1049 1050 s->len = SPI_NOR_MAX_ID_LEN; 1051 s->pos = 0; 1052 s->state = STATE_READING_DATA; 1053 break; 1054 1055 case RDCR: 1056 s->data[0] = s->volatile_cfg & 0xFF; 1057 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 1058 s->pos = 0; 1059 s->len = 1; 1060 s->state = STATE_READING_DATA; 1061 break; 1062 1063 case BULK_ERASE_60: 1064 case BULK_ERASE: 1065 if (s->write_enable) { 1066 trace_m25p80_chip_erase(s); 1067 flash_erase(s, 0, BULK_ERASE); 1068 } else { 1069 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 1070 "protect!\n"); 1071 } 1072 break; 1073 case NOP: 1074 break; 1075 case EN_4BYTE_ADDR: 1076 s->four_bytes_address_mode = true; 1077 break; 1078 case EX_4BYTE_ADDR: 1079 s->four_bytes_address_mode = false; 1080 break; 1081 case BRRD: 1082 case EXTEND_ADDR_READ: 1083 s->data[0] = s->ear; 1084 s->pos = 0; 1085 s->len = 1; 1086 s->state = STATE_READING_DATA; 1087 break; 1088 case BRWR: 1089 case EXTEND_ADDR_WRITE: 1090 if (s->write_enable) { 1091 s->needed_bytes = 1; 1092 s->pos = 0; 1093 s->len = 0; 1094 s->state = STATE_COLLECTING_DATA; 1095 } 1096 break; 1097 case RNVCR: 1098 s->data[0] = s->nonvolatile_cfg & 0xFF; 1099 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1100 s->pos = 0; 1101 s->len = 2; 1102 s->state = STATE_READING_DATA; 1103 break; 1104 case WNVCR: 1105 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1106 s->needed_bytes = 2; 1107 s->pos = 0; 1108 s->len = 0; 1109 s->state = STATE_COLLECTING_DATA; 1110 } 1111 break; 1112 case RVCR: 1113 s->data[0] = s->volatile_cfg & 0xFF; 1114 s->pos = 0; 1115 s->len = 1; 1116 s->state = STATE_READING_DATA; 1117 break; 1118 case WVCR: 1119 if (s->write_enable) { 1120 s->needed_bytes = 1; 1121 s->pos = 0; 1122 s->len = 0; 1123 s->state = STATE_COLLECTING_DATA; 1124 } 1125 break; 1126 case REVCR: 1127 s->data[0] = s->enh_volatile_cfg & 0xFF; 1128 s->pos = 0; 1129 s->len = 1; 1130 s->state = STATE_READING_DATA; 1131 break; 1132 case WEVCR: 1133 if (s->write_enable) { 1134 s->needed_bytes = 1; 1135 s->pos = 0; 1136 s->len = 0; 1137 s->state = STATE_COLLECTING_DATA; 1138 } 1139 break; 1140 case RESET_ENABLE: 1141 s->reset_enable = true; 1142 break; 1143 case RESET_MEMORY: 1144 if (s->reset_enable) { 1145 reset_memory(s); 1146 } 1147 break; 1148 case RDCR_EQIO: 1149 switch (get_man(s)) { 1150 case MAN_SPANSION: 1151 s->data[0] = (!!s->quad_enable) << 1; 1152 s->pos = 0; 1153 s->len = 1; 1154 s->state = STATE_READING_DATA; 1155 break; 1156 case MAN_MACRONIX: 1157 s->quad_enable = true; 1158 break; 1159 default: 1160 break; 1161 } 1162 break; 1163 case RSTQIO: 1164 s->quad_enable = false; 1165 break; 1166 default: 1167 s->pos = 0; 1168 s->len = 1; 1169 s->state = STATE_READING_DATA; 1170 s->data_read_loop = true; 1171 s->data[0] = 0; 1172 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1173 break; 1174 } 1175 } 1176 1177 static int m25p80_cs(SSISlave *ss, bool select) 1178 { 1179 Flash *s = M25P80(ss); 1180 1181 if (select) { 1182 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1183 complete_collecting_data(s); 1184 } 1185 s->len = 0; 1186 s->pos = 0; 1187 s->state = STATE_IDLE; 1188 flash_sync_dirty(s, -1); 1189 s->data_read_loop = false; 1190 } 1191 1192 trace_m25p80_select(s, select ? "de" : ""); 1193 1194 return 0; 1195 } 1196 1197 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) 1198 { 1199 Flash *s = M25P80(ss); 1200 uint32_t r = 0; 1201 1202 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, 1203 s->cur_addr, (uint8_t)tx); 1204 1205 switch (s->state) { 1206 1207 case STATE_PAGE_PROGRAM: 1208 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); 1209 flash_write8(s, s->cur_addr, (uint8_t)tx); 1210 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1211 break; 1212 1213 case STATE_READ: 1214 r = s->storage[s->cur_addr]; 1215 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); 1216 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1217 break; 1218 1219 case STATE_COLLECTING_DATA: 1220 case STATE_COLLECTING_VAR_LEN_DATA: 1221 1222 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1223 qemu_log_mask(LOG_GUEST_ERROR, 1224 "M25P80: Write overrun internal data buffer. " 1225 "SPI controller (QEMU emulator or guest driver) " 1226 "is misbehaving\n"); 1227 s->len = s->pos = 0; 1228 s->state = STATE_IDLE; 1229 break; 1230 } 1231 1232 s->data[s->len] = (uint8_t)tx; 1233 s->len++; 1234 1235 if (s->len == s->needed_bytes) { 1236 complete_collecting_data(s); 1237 } 1238 break; 1239 1240 case STATE_READING_DATA: 1241 1242 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1243 qemu_log_mask(LOG_GUEST_ERROR, 1244 "M25P80: Read overrun internal data buffer. " 1245 "SPI controller (QEMU emulator or guest driver) " 1246 "is misbehaving\n"); 1247 s->len = s->pos = 0; 1248 s->state = STATE_IDLE; 1249 break; 1250 } 1251 1252 r = s->data[s->pos]; 1253 trace_m25p80_read_data(s, s->pos, (uint8_t)r); 1254 s->pos++; 1255 if (s->pos == s->len) { 1256 s->pos = 0; 1257 if (!s->data_read_loop) { 1258 s->state = STATE_IDLE; 1259 } 1260 } 1261 break; 1262 1263 default: 1264 case STATE_IDLE: 1265 decode_new_cmd(s, (uint8_t)tx); 1266 break; 1267 } 1268 1269 return r; 1270 } 1271 1272 static void m25p80_realize(SSISlave *ss, Error **errp) 1273 { 1274 Flash *s = M25P80(ss); 1275 M25P80Class *mc = M25P80_GET_CLASS(s); 1276 int ret; 1277 1278 s->pi = mc->pi; 1279 1280 s->size = s->pi->sector_size * s->pi->n_sectors; 1281 s->dirty_page = -1; 1282 1283 if (s->blk) { 1284 uint64_t perm = BLK_PERM_CONSISTENT_READ | 1285 (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE); 1286 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); 1287 if (ret < 0) { 1288 return; 1289 } 1290 1291 trace_m25p80_binding(s); 1292 s->storage = blk_blockalign(s->blk, s->size); 1293 1294 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) { 1295 error_setg(errp, "failed to read the initial flash content"); 1296 return; 1297 } 1298 } else { 1299 trace_m25p80_binding_no_bdrv(s); 1300 s->storage = blk_blockalign(NULL, s->size); 1301 memset(s->storage, 0xFF, s->size); 1302 } 1303 } 1304 1305 static void m25p80_reset(DeviceState *d) 1306 { 1307 Flash *s = M25P80(d); 1308 1309 reset_memory(s); 1310 } 1311 1312 static int m25p80_pre_save(void *opaque) 1313 { 1314 flash_sync_dirty((Flash *)opaque, -1); 1315 1316 return 0; 1317 } 1318 1319 static Property m25p80_properties[] = { 1320 /* This is default value for Micron flash */ 1321 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1322 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1323 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1324 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1325 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1326 DEFINE_PROP_DRIVE("drive", Flash, blk), 1327 DEFINE_PROP_END_OF_LIST(), 1328 }; 1329 1330 static int m25p80_pre_load(void *opaque) 1331 { 1332 Flash *s = (Flash *)opaque; 1333 1334 s->data_read_loop = false; 1335 return 0; 1336 } 1337 1338 static bool m25p80_data_read_loop_needed(void *opaque) 1339 { 1340 Flash *s = (Flash *)opaque; 1341 1342 return s->data_read_loop; 1343 } 1344 1345 static const VMStateDescription vmstate_m25p80_data_read_loop = { 1346 .name = "m25p80/data_read_loop", 1347 .version_id = 1, 1348 .minimum_version_id = 1, 1349 .needed = m25p80_data_read_loop_needed, 1350 .fields = (VMStateField[]) { 1351 VMSTATE_BOOL(data_read_loop, Flash), 1352 VMSTATE_END_OF_LIST() 1353 } 1354 }; 1355 1356 static const VMStateDescription vmstate_m25p80 = { 1357 .name = "m25p80", 1358 .version_id = 0, 1359 .minimum_version_id = 0, 1360 .pre_save = m25p80_pre_save, 1361 .pre_load = m25p80_pre_load, 1362 .fields = (VMStateField[]) { 1363 VMSTATE_UINT8(state, Flash), 1364 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1365 VMSTATE_UINT32(len, Flash), 1366 VMSTATE_UINT32(pos, Flash), 1367 VMSTATE_UINT8(needed_bytes, Flash), 1368 VMSTATE_UINT8(cmd_in_progress, Flash), 1369 VMSTATE_UINT32(cur_addr, Flash), 1370 VMSTATE_BOOL(write_enable, Flash), 1371 VMSTATE_BOOL(reset_enable, Flash), 1372 VMSTATE_UINT8(ear, Flash), 1373 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1374 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1375 VMSTATE_UINT32(volatile_cfg, Flash), 1376 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1377 VMSTATE_BOOL(quad_enable, Flash), 1378 VMSTATE_UINT8(spansion_cr1nv, Flash), 1379 VMSTATE_UINT8(spansion_cr2nv, Flash), 1380 VMSTATE_UINT8(spansion_cr3nv, Flash), 1381 VMSTATE_UINT8(spansion_cr4nv, Flash), 1382 VMSTATE_END_OF_LIST() 1383 }, 1384 .subsections = (const VMStateDescription * []) { 1385 &vmstate_m25p80_data_read_loop, 1386 NULL 1387 } 1388 }; 1389 1390 static void m25p80_class_init(ObjectClass *klass, void *data) 1391 { 1392 DeviceClass *dc = DEVICE_CLASS(klass); 1393 SSISlaveClass *k = SSI_SLAVE_CLASS(klass); 1394 M25P80Class *mc = M25P80_CLASS(klass); 1395 1396 k->realize = m25p80_realize; 1397 k->transfer = m25p80_transfer8; 1398 k->set_cs = m25p80_cs; 1399 k->cs_polarity = SSI_CS_LOW; 1400 dc->vmsd = &vmstate_m25p80; 1401 device_class_set_props(dc, m25p80_properties); 1402 dc->reset = m25p80_reset; 1403 mc->pi = data; 1404 } 1405 1406 static const TypeInfo m25p80_info = { 1407 .name = TYPE_M25P80, 1408 .parent = TYPE_SSI_SLAVE, 1409 .instance_size = sizeof(Flash), 1410 .class_size = sizeof(M25P80Class), 1411 .abstract = true, 1412 }; 1413 1414 static void m25p80_register_types(void) 1415 { 1416 int i; 1417 1418 type_register_static(&m25p80_info); 1419 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1420 TypeInfo ti = { 1421 .name = known_devices[i].part_name, 1422 .parent = TYPE_M25P80, 1423 .class_init = m25p80_class_init, 1424 .class_data = (void *)&known_devices[i], 1425 }; 1426 type_register(&ti); 1427 } 1428 } 1429 1430 type_init(m25p80_register_types) 1431