1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/qdev-properties-system.h" 29 #include "hw/ssi/ssi.h" 30 #include "migration/vmstate.h" 31 #include "qemu/bitops.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 #include "qemu/error-report.h" 35 #include "qapi/error.h" 36 #include "trace.h" 37 #include "qom/object.h" 38 39 /* Fields for FlashPartInfo->flags */ 40 41 /* erase capabilities */ 42 #define ER_4K 1 43 #define ER_32K 2 44 /* set to allow the page program command to write 0s back to 1. Useful for 45 * modelling EEPROM with SPI flash command set 46 */ 47 #define EEPROM 0x100 48 49 /* 16 MiB max in 3 byte address mode */ 50 #define MAX_3BYTES_SIZE 0x1000000 51 52 #define SPI_NOR_MAX_ID_LEN 6 53 54 typedef struct FlashPartInfo { 55 const char *part_name; 56 /* 57 * This array stores the ID bytes. 58 * The first three bytes are the JEDIC ID. 59 * JEDEC ID zero means "no ID" (mostly older chips). 60 */ 61 uint8_t id[SPI_NOR_MAX_ID_LEN]; 62 uint8_t id_len; 63 /* there is confusion between manufacturers as to what a sector is. In this 64 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 65 * command (opcode 0xd8). 66 */ 67 uint32_t sector_size; 68 uint32_t n_sectors; 69 uint32_t page_size; 70 uint16_t flags; 71 /* 72 * Big sized spi nor are often stacked devices, thus sometime 73 * replace chip erase with die erase. 74 * This field inform how many die is in the chip. 75 */ 76 uint8_t die_cnt; 77 } FlashPartInfo; 78 79 /* adapted from linux */ 80 /* Used when the "_ext_id" is two bytes at most */ 81 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 82 .part_name = _part_name,\ 83 .id = {\ 84 ((_jedec_id) >> 16) & 0xff,\ 85 ((_jedec_id) >> 8) & 0xff,\ 86 (_jedec_id) & 0xff,\ 87 ((_ext_id) >> 8) & 0xff,\ 88 (_ext_id) & 0xff,\ 89 },\ 90 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 91 .sector_size = (_sector_size),\ 92 .n_sectors = (_n_sectors),\ 93 .page_size = 256,\ 94 .flags = (_flags),\ 95 .die_cnt = 0 96 97 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 98 .part_name = _part_name,\ 99 .id = {\ 100 ((_jedec_id) >> 16) & 0xff,\ 101 ((_jedec_id) >> 8) & 0xff,\ 102 (_jedec_id) & 0xff,\ 103 ((_ext_id) >> 16) & 0xff,\ 104 ((_ext_id) >> 8) & 0xff,\ 105 (_ext_id) & 0xff,\ 106 },\ 107 .id_len = 6,\ 108 .sector_size = (_sector_size),\ 109 .n_sectors = (_n_sectors),\ 110 .page_size = 256,\ 111 .flags = (_flags),\ 112 .die_cnt = 0 113 114 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ 115 _flags, _die_cnt)\ 116 .part_name = _part_name,\ 117 .id = {\ 118 ((_jedec_id) >> 16) & 0xff,\ 119 ((_jedec_id) >> 8) & 0xff,\ 120 (_jedec_id) & 0xff,\ 121 ((_ext_id) >> 8) & 0xff,\ 122 (_ext_id) & 0xff,\ 123 },\ 124 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 125 .sector_size = (_sector_size),\ 126 .n_sectors = (_n_sectors),\ 127 .page_size = 256,\ 128 .flags = (_flags),\ 129 .die_cnt = _die_cnt 130 131 #define JEDEC_NUMONYX 0x20 132 #define JEDEC_WINBOND 0xEF 133 #define JEDEC_SPANSION 0x01 134 135 /* Numonyx (Micron) Configuration register macros */ 136 #define VCFG_DUMMY 0x1 137 #define VCFG_WRAP_SEQUENTIAL 0x2 138 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 139 #define NVCFG_XIP_MODE_MASK (7 << 9) 140 #define VCFG_XIP_MODE_DISABLED (1 << 3) 141 #define CFG_DUMMY_CLK_LEN 4 142 #define NVCFG_DUMMY_CLK_POS 12 143 #define VCFG_DUMMY_CLK_POS 4 144 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 145 #define EVCFG_VPP_ACCELERATOR (1 << 3) 146 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 147 #define NVCFG_DUAL_IO_MASK (1 << 2) 148 #define EVCFG_DUAL_IO_DISABLED (1 << 6) 149 #define NVCFG_QUAD_IO_MASK (1 << 3) 150 #define EVCFG_QUAD_IO_DISABLED (1 << 7) 151 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 152 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 153 154 /* Numonyx (Micron) Flag Status Register macros */ 155 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 156 #define FSR_FLASH_READY (1 << 7) 157 158 /* Spansion configuration registers macros. */ 159 #define SPANSION_QUAD_CFG_POS 0 160 #define SPANSION_QUAD_CFG_LEN 1 161 #define SPANSION_DUMMY_CLK_POS 0 162 #define SPANSION_DUMMY_CLK_LEN 4 163 #define SPANSION_ADDR_LEN_POS 7 164 #define SPANSION_ADDR_LEN_LEN 1 165 166 /* 167 * Spansion read mode command length in bytes, 168 * the mode is currently not supported. 169 */ 170 171 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 172 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 173 174 static const FlashPartInfo known_devices[] = { 175 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 176 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 177 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 178 179 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 180 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 181 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 182 183 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 184 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 185 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 186 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 187 188 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 189 190 /* Atmel EEPROMS - it is assumed, that don't care bit in command 191 * is set to 0. Block protection is not supported. 192 */ 193 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 194 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 195 196 /* EON -- en25xxx */ 197 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 198 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 199 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 200 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 201 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 202 203 /* GigaDevice */ 204 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 205 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 206 207 /* Intel/Numonyx -- xxxs33b */ 208 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 209 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 210 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 211 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 212 213 /* ISSI */ 214 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, 215 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, 216 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, 217 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, 218 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, 219 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, 220 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) }, 221 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) }, 222 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) }, 223 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) }, 224 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) }, 225 226 /* Macronix */ 227 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 228 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 229 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 230 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 231 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 232 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 233 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 234 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 235 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) }, 236 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 237 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 238 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 239 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 240 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 241 242 /* Micron */ 243 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 244 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 245 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 246 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 247 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 248 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 249 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 250 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 251 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, 252 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 253 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 254 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 255 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 256 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, 257 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, 258 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024, 259 ER_4K | ER_32K, 2) }, 260 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 261 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 262 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 263 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 264 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 265 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 266 267 /* Spansion -- single (large) sector size only, at least 268 * for the chips listed here (without boot sectors). 269 */ 270 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 271 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 272 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 273 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 274 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 275 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 276 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 277 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 278 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 279 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 280 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 281 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 282 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 283 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 284 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 285 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 286 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 287 288 /* Spansion -- boot sectors support */ 289 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 290 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 291 292 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 293 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 294 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 295 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 296 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 297 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 298 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 299 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 300 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 301 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 302 303 /* ST Microelectronics -- newer production may have feature updates */ 304 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 305 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 306 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 307 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 308 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 309 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 310 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 311 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 312 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 313 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 314 315 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 316 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 317 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 318 319 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 320 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 321 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 322 323 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 324 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 325 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 326 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 327 328 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 329 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 330 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 331 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 332 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 333 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 334 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 335 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 336 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 337 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 338 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 339 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 340 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 341 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, 342 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) }, 343 { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K) }, 344 }; 345 346 typedef enum { 347 NOP = 0, 348 WRSR = 0x1, 349 WRDI = 0x4, 350 RDSR = 0x5, 351 WREN = 0x6, 352 BRRD = 0x16, 353 BRWR = 0x17, 354 JEDEC_READ = 0x9f, 355 BULK_ERASE_60 = 0x60, 356 BULK_ERASE = 0xc7, 357 READ_FSR = 0x70, 358 RDCR = 0x15, 359 360 READ = 0x03, 361 READ4 = 0x13, 362 FAST_READ = 0x0b, 363 FAST_READ4 = 0x0c, 364 DOR = 0x3b, 365 DOR4 = 0x3c, 366 QOR = 0x6b, 367 QOR4 = 0x6c, 368 DIOR = 0xbb, 369 DIOR4 = 0xbc, 370 QIOR = 0xeb, 371 QIOR4 = 0xec, 372 373 PP = 0x02, 374 PP4 = 0x12, 375 PP4_4 = 0x3e, 376 DPP = 0xa2, 377 QPP = 0x32, 378 QPP_4 = 0x34, 379 RDID_90 = 0x90, 380 RDID_AB = 0xab, 381 AAI_WP = 0xad, 382 383 ERASE_4K = 0x20, 384 ERASE4_4K = 0x21, 385 ERASE_32K = 0x52, 386 ERASE4_32K = 0x5c, 387 ERASE_SECTOR = 0xd8, 388 ERASE4_SECTOR = 0xdc, 389 390 EN_4BYTE_ADDR = 0xB7, 391 EX_4BYTE_ADDR = 0xE9, 392 393 EXTEND_ADDR_READ = 0xC8, 394 EXTEND_ADDR_WRITE = 0xC5, 395 396 RESET_ENABLE = 0x66, 397 RESET_MEMORY = 0x99, 398 399 /* 400 * Micron: 0x35 - enable QPI 401 * Spansion: 0x35 - read control register 402 */ 403 RDCR_EQIO = 0x35, 404 RSTQIO = 0xf5, 405 406 RNVCR = 0xB5, 407 WNVCR = 0xB1, 408 409 RVCR = 0x85, 410 WVCR = 0x81, 411 412 REVCR = 0x65, 413 WEVCR = 0x61, 414 415 DIE_ERASE = 0xC4, 416 } FlashCMD; 417 418 typedef enum { 419 STATE_IDLE, 420 STATE_PAGE_PROGRAM, 421 STATE_READ, 422 STATE_COLLECTING_DATA, 423 STATE_COLLECTING_VAR_LEN_DATA, 424 STATE_READING_DATA, 425 } CMDState; 426 427 typedef enum { 428 MAN_SPANSION, 429 MAN_MACRONIX, 430 MAN_NUMONYX, 431 MAN_WINBOND, 432 MAN_SST, 433 MAN_ISSI, 434 MAN_GENERIC, 435 } Manufacturer; 436 437 typedef enum { 438 MODE_STD = 0, 439 MODE_DIO = 1, 440 MODE_QIO = 2 441 } SPIMode; 442 443 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 444 445 struct Flash { 446 SSIPeripheral parent_obj; 447 448 BlockBackend *blk; 449 450 uint8_t *storage; 451 uint32_t size; 452 int page_size; 453 454 uint8_t state; 455 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 456 uint32_t len; 457 uint32_t pos; 458 bool data_read_loop; 459 uint8_t needed_bytes; 460 uint8_t cmd_in_progress; 461 uint32_t cur_addr; 462 uint32_t nonvolatile_cfg; 463 /* Configuration register for Macronix */ 464 uint32_t volatile_cfg; 465 uint32_t enh_volatile_cfg; 466 /* Spansion cfg registers. */ 467 uint8_t spansion_cr1nv; 468 uint8_t spansion_cr2nv; 469 uint8_t spansion_cr3nv; 470 uint8_t spansion_cr4nv; 471 uint8_t spansion_cr1v; 472 uint8_t spansion_cr2v; 473 uint8_t spansion_cr3v; 474 uint8_t spansion_cr4v; 475 bool write_enable; 476 bool four_bytes_address_mode; 477 bool reset_enable; 478 bool quad_enable; 479 bool aai_enable; 480 uint8_t ear; 481 482 int64_t dirty_page; 483 484 const FlashPartInfo *pi; 485 486 }; 487 488 struct M25P80Class { 489 SSIPeripheralClass parent_class; 490 FlashPartInfo *pi; 491 }; 492 493 #define TYPE_M25P80 "m25p80-generic" 494 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) 495 496 static inline Manufacturer get_man(Flash *s) 497 { 498 switch (s->pi->id[0]) { 499 case 0x20: 500 return MAN_NUMONYX; 501 case 0xEF: 502 return MAN_WINBOND; 503 case 0x01: 504 return MAN_SPANSION; 505 case 0xC2: 506 return MAN_MACRONIX; 507 case 0xBF: 508 return MAN_SST; 509 case 0x9D: 510 return MAN_ISSI; 511 default: 512 return MAN_GENERIC; 513 } 514 } 515 516 static void blk_sync_complete(void *opaque, int ret) 517 { 518 QEMUIOVector *iov = opaque; 519 520 qemu_iovec_destroy(iov); 521 g_free(iov); 522 523 /* do nothing. Masters do not directly interact with the backing store, 524 * only the working copy so no mutexing required. 525 */ 526 } 527 528 static void flash_sync_page(Flash *s, int page) 529 { 530 QEMUIOVector *iov; 531 532 if (!s->blk || !blk_is_writable(s->blk)) { 533 return; 534 } 535 536 iov = g_new(QEMUIOVector, 1); 537 qemu_iovec_init(iov, 1); 538 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 539 s->pi->page_size); 540 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 541 blk_sync_complete, iov); 542 } 543 544 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 545 { 546 QEMUIOVector *iov; 547 548 if (!s->blk || !blk_is_writable(s->blk)) { 549 return; 550 } 551 552 assert(!(len % BDRV_SECTOR_SIZE)); 553 iov = g_new(QEMUIOVector, 1); 554 qemu_iovec_init(iov, 1); 555 qemu_iovec_add(iov, s->storage + off, len); 556 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 557 } 558 559 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 560 { 561 uint32_t len; 562 uint8_t capa_to_assert = 0; 563 564 switch (cmd) { 565 case ERASE_4K: 566 case ERASE4_4K: 567 len = 4 * KiB; 568 capa_to_assert = ER_4K; 569 break; 570 case ERASE_32K: 571 case ERASE4_32K: 572 len = 32 * KiB; 573 capa_to_assert = ER_32K; 574 break; 575 case ERASE_SECTOR: 576 case ERASE4_SECTOR: 577 len = s->pi->sector_size; 578 break; 579 case BULK_ERASE: 580 len = s->size; 581 break; 582 case DIE_ERASE: 583 if (s->pi->die_cnt) { 584 len = s->size / s->pi->die_cnt; 585 offset = offset & (~(len - 1)); 586 } else { 587 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" 588 " by device\n"); 589 return; 590 } 591 break; 592 default: 593 abort(); 594 } 595 596 trace_m25p80_flash_erase(s, offset, len); 597 598 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 599 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 600 " device\n", len); 601 } 602 603 if (!s->write_enable) { 604 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 605 return; 606 } 607 memset(s->storage + offset, 0xff, len); 608 flash_sync_area(s, offset, len); 609 } 610 611 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 612 { 613 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 614 flash_sync_page(s, s->dirty_page); 615 s->dirty_page = newpage; 616 } 617 } 618 619 static inline 620 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 621 { 622 uint32_t page = addr / s->pi->page_size; 623 uint8_t prev = s->storage[s->cur_addr]; 624 625 if (!s->write_enable) { 626 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 627 return; 628 } 629 630 if ((prev ^ data) & data) { 631 trace_m25p80_programming_zero_to_one(s, addr, prev, data); 632 } 633 634 if (s->pi->flags & EEPROM) { 635 s->storage[s->cur_addr] = data; 636 } else { 637 s->storage[s->cur_addr] &= data; 638 } 639 640 flash_sync_dirty(s, page); 641 s->dirty_page = page; 642 } 643 644 static inline int get_addr_length(Flash *s) 645 { 646 /* check if eeprom is in use */ 647 if (s->pi->flags == EEPROM) { 648 return 2; 649 } 650 651 switch (s->cmd_in_progress) { 652 case PP4: 653 case PP4_4: 654 case QPP_4: 655 case READ4: 656 case QIOR4: 657 case ERASE4_4K: 658 case ERASE4_32K: 659 case ERASE4_SECTOR: 660 case FAST_READ4: 661 case DOR4: 662 case QOR4: 663 case DIOR4: 664 return 4; 665 default: 666 return s->four_bytes_address_mode ? 4 : 3; 667 } 668 } 669 670 static void complete_collecting_data(Flash *s) 671 { 672 int i, n; 673 674 n = get_addr_length(s); 675 s->cur_addr = (n == 3 ? s->ear : 0); 676 for (i = 0; i < n; ++i) { 677 s->cur_addr <<= 8; 678 s->cur_addr |= s->data[i]; 679 } 680 681 s->cur_addr &= s->size - 1; 682 683 s->state = STATE_IDLE; 684 685 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, 686 s->cur_addr); 687 688 switch (s->cmd_in_progress) { 689 case DPP: 690 case QPP: 691 case QPP_4: 692 case PP: 693 case PP4: 694 case PP4_4: 695 s->state = STATE_PAGE_PROGRAM; 696 break; 697 case AAI_WP: 698 /* AAI programming starts from the even address */ 699 s->cur_addr &= ~BIT(0); 700 s->state = STATE_PAGE_PROGRAM; 701 break; 702 case READ: 703 case READ4: 704 case FAST_READ: 705 case FAST_READ4: 706 case DOR: 707 case DOR4: 708 case QOR: 709 case QOR4: 710 case DIOR: 711 case DIOR4: 712 case QIOR: 713 case QIOR4: 714 s->state = STATE_READ; 715 break; 716 case ERASE_4K: 717 case ERASE4_4K: 718 case ERASE_32K: 719 case ERASE4_32K: 720 case ERASE_SECTOR: 721 case ERASE4_SECTOR: 722 case DIE_ERASE: 723 flash_erase(s, s->cur_addr, s->cmd_in_progress); 724 break; 725 case WRSR: 726 switch (get_man(s)) { 727 case MAN_SPANSION: 728 s->quad_enable = !!(s->data[1] & 0x02); 729 break; 730 case MAN_ISSI: 731 s->quad_enable = extract32(s->data[0], 6, 1); 732 break; 733 case MAN_MACRONIX: 734 s->quad_enable = extract32(s->data[0], 6, 1); 735 if (s->len > 1) { 736 s->volatile_cfg = s->data[1]; 737 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 738 } 739 break; 740 default: 741 break; 742 } 743 if (s->write_enable) { 744 s->write_enable = false; 745 } 746 break; 747 case BRWR: 748 case EXTEND_ADDR_WRITE: 749 s->ear = s->data[0]; 750 break; 751 case WNVCR: 752 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 753 break; 754 case WVCR: 755 s->volatile_cfg = s->data[0]; 756 break; 757 case WEVCR: 758 s->enh_volatile_cfg = s->data[0]; 759 break; 760 case RDID_90: 761 case RDID_AB: 762 if (get_man(s) == MAN_SST) { 763 if (s->cur_addr <= 1) { 764 if (s->cur_addr) { 765 s->data[0] = s->pi->id[2]; 766 s->data[1] = s->pi->id[0]; 767 } else { 768 s->data[0] = s->pi->id[0]; 769 s->data[1] = s->pi->id[2]; 770 } 771 s->pos = 0; 772 s->len = 2; 773 s->data_read_loop = true; 774 s->state = STATE_READING_DATA; 775 } else { 776 qemu_log_mask(LOG_GUEST_ERROR, 777 "M25P80: Invalid read id address\n"); 778 } 779 } else { 780 qemu_log_mask(LOG_GUEST_ERROR, 781 "M25P80: Read id (command 0x90/0xAB) is not supported" 782 " by device\n"); 783 } 784 break; 785 default: 786 break; 787 } 788 } 789 790 static void reset_memory(Flash *s) 791 { 792 s->cmd_in_progress = NOP; 793 s->cur_addr = 0; 794 s->ear = 0; 795 s->four_bytes_address_mode = false; 796 s->len = 0; 797 s->needed_bytes = 0; 798 s->pos = 0; 799 s->state = STATE_IDLE; 800 s->write_enable = false; 801 s->reset_enable = false; 802 s->quad_enable = false; 803 s->aai_enable = false; 804 805 switch (get_man(s)) { 806 case MAN_NUMONYX: 807 s->volatile_cfg = 0; 808 s->volatile_cfg |= VCFG_DUMMY; 809 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 810 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 811 == NVCFG_XIP_MODE_DISABLED) { 812 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; 813 } 814 s->volatile_cfg |= deposit32(s->volatile_cfg, 815 VCFG_DUMMY_CLK_POS, 816 CFG_DUMMY_CLK_LEN, 817 extract32(s->nonvolatile_cfg, 818 NVCFG_DUMMY_CLK_POS, 819 CFG_DUMMY_CLK_LEN) 820 ); 821 822 s->enh_volatile_cfg = 0; 823 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; 824 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 825 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 826 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 827 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; 828 } 829 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 830 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; 831 } 832 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 833 s->four_bytes_address_mode = true; 834 } 835 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 836 s->ear = s->size / MAX_3BYTES_SIZE - 1; 837 } 838 break; 839 case MAN_MACRONIX: 840 s->volatile_cfg = 0x7; 841 break; 842 case MAN_SPANSION: 843 s->spansion_cr1v = s->spansion_cr1nv; 844 s->spansion_cr2v = s->spansion_cr2nv; 845 s->spansion_cr3v = s->spansion_cr3nv; 846 s->spansion_cr4v = s->spansion_cr4nv; 847 s->quad_enable = extract32(s->spansion_cr1v, 848 SPANSION_QUAD_CFG_POS, 849 SPANSION_QUAD_CFG_LEN 850 ); 851 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 852 SPANSION_ADDR_LEN_POS, 853 SPANSION_ADDR_LEN_LEN 854 ); 855 break; 856 default: 857 break; 858 } 859 860 trace_m25p80_reset_done(s); 861 } 862 863 static uint8_t numonyx_mode(Flash *s) 864 { 865 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { 866 return MODE_QIO; 867 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { 868 return MODE_DIO; 869 } else { 870 return MODE_STD; 871 } 872 } 873 874 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s) 875 { 876 uint8_t num_dummies; 877 uint8_t mode; 878 assert(get_man(s) == MAN_NUMONYX); 879 880 mode = numonyx_mode(s); 881 num_dummies = extract32(s->volatile_cfg, 4, 4); 882 883 if (num_dummies == 0x0 || num_dummies == 0xf) { 884 switch (s->cmd_in_progress) { 885 case QIOR: 886 case QIOR4: 887 num_dummies = 10; 888 break; 889 default: 890 num_dummies = (mode == MODE_QIO) ? 10 : 8; 891 break; 892 } 893 } 894 895 return num_dummies; 896 } 897 898 static void decode_fast_read_cmd(Flash *s) 899 { 900 s->needed_bytes = get_addr_length(s); 901 switch (get_man(s)) { 902 /* Dummy cycles - modeled with bytes writes instead of bits */ 903 case MAN_SST: 904 s->needed_bytes += 1; 905 break; 906 case MAN_WINBOND: 907 s->needed_bytes += 8; 908 break; 909 case MAN_NUMONYX: 910 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 911 break; 912 case MAN_MACRONIX: 913 if (extract32(s->volatile_cfg, 6, 2) == 1) { 914 s->needed_bytes += 6; 915 } else { 916 s->needed_bytes += 8; 917 } 918 break; 919 case MAN_SPANSION: 920 s->needed_bytes += extract32(s->spansion_cr2v, 921 SPANSION_DUMMY_CLK_POS, 922 SPANSION_DUMMY_CLK_LEN 923 ); 924 break; 925 case MAN_ISSI: 926 /* 927 * The Fast Read instruction code is followed by address bytes and 928 * dummy cycles, transmitted via the SI line. 929 * 930 * The number of dummy cycles is configurable but this is currently 931 * unmodeled, hence the default value 8 is used. 932 * 933 * QPI (Quad Peripheral Interface) mode has different default value 934 * of dummy cycles, but this is unsupported at the time being. 935 */ 936 s->needed_bytes += 1; 937 break; 938 default: 939 break; 940 } 941 s->pos = 0; 942 s->len = 0; 943 s->state = STATE_COLLECTING_DATA; 944 } 945 946 static void decode_dio_read_cmd(Flash *s) 947 { 948 s->needed_bytes = get_addr_length(s); 949 /* Dummy cycles modeled with bytes writes instead of bits */ 950 switch (get_man(s)) { 951 case MAN_WINBOND: 952 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 953 break; 954 case MAN_SPANSION: 955 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 956 s->needed_bytes += extract32(s->spansion_cr2v, 957 SPANSION_DUMMY_CLK_POS, 958 SPANSION_DUMMY_CLK_LEN 959 ); 960 break; 961 case MAN_NUMONYX: 962 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 963 break; 964 case MAN_MACRONIX: 965 switch (extract32(s->volatile_cfg, 6, 2)) { 966 case 1: 967 s->needed_bytes += 6; 968 break; 969 case 2: 970 s->needed_bytes += 8; 971 break; 972 default: 973 s->needed_bytes += 4; 974 break; 975 } 976 break; 977 case MAN_ISSI: 978 /* 979 * The Fast Read Dual I/O instruction code is followed by address bytes 980 * and dummy cycles, transmitted via the IO1 and IO0 line. 981 * 982 * The number of dummy cycles is configurable but this is currently 983 * unmodeled, hence the default value 4 is used. 984 */ 985 s->needed_bytes += 1; 986 break; 987 default: 988 break; 989 } 990 s->pos = 0; 991 s->len = 0; 992 s->state = STATE_COLLECTING_DATA; 993 } 994 995 static void decode_qio_read_cmd(Flash *s) 996 { 997 s->needed_bytes = get_addr_length(s); 998 /* Dummy cycles modeled with bytes writes instead of bits */ 999 switch (get_man(s)) { 1000 case MAN_WINBOND: 1001 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1002 s->needed_bytes += 4; 1003 break; 1004 case MAN_SPANSION: 1005 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1006 s->needed_bytes += extract32(s->spansion_cr2v, 1007 SPANSION_DUMMY_CLK_POS, 1008 SPANSION_DUMMY_CLK_LEN 1009 ); 1010 break; 1011 case MAN_NUMONYX: 1012 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1013 break; 1014 case MAN_MACRONIX: 1015 switch (extract32(s->volatile_cfg, 6, 2)) { 1016 case 1: 1017 s->needed_bytes += 4; 1018 break; 1019 case 2: 1020 s->needed_bytes += 8; 1021 break; 1022 default: 1023 s->needed_bytes += 6; 1024 break; 1025 } 1026 break; 1027 case MAN_ISSI: 1028 /* 1029 * The Fast Read Quad I/O instruction code is followed by address bytes 1030 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line. 1031 * 1032 * The number of dummy cycles is configurable but this is currently 1033 * unmodeled, hence the default value 6 is used. 1034 * 1035 * QPI (Quad Peripheral Interface) mode has different default value 1036 * of dummy cycles, but this is unsupported at the time being. 1037 */ 1038 s->needed_bytes += 3; 1039 break; 1040 default: 1041 break; 1042 } 1043 s->pos = 0; 1044 s->len = 0; 1045 s->state = STATE_COLLECTING_DATA; 1046 } 1047 1048 static bool is_valid_aai_cmd(uint32_t cmd) 1049 { 1050 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR; 1051 } 1052 1053 static void decode_new_cmd(Flash *s, uint32_t value) 1054 { 1055 int i; 1056 1057 s->cmd_in_progress = value; 1058 trace_m25p80_command_decoded(s, value); 1059 1060 if (value != RESET_MEMORY) { 1061 s->reset_enable = false; 1062 } 1063 1064 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) { 1065 qemu_log_mask(LOG_GUEST_ERROR, 1066 "M25P80: Invalid cmd within AAI programming sequence"); 1067 } 1068 1069 switch (value) { 1070 1071 case ERASE_4K: 1072 case ERASE4_4K: 1073 case ERASE_32K: 1074 case ERASE4_32K: 1075 case ERASE_SECTOR: 1076 case ERASE4_SECTOR: 1077 case PP: 1078 case PP4: 1079 case DIE_ERASE: 1080 case RDID_90: 1081 case RDID_AB: 1082 s->needed_bytes = get_addr_length(s); 1083 s->pos = 0; 1084 s->len = 0; 1085 s->state = STATE_COLLECTING_DATA; 1086 break; 1087 case READ: 1088 case READ4: 1089 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1090 s->needed_bytes = get_addr_length(s); 1091 s->pos = 0; 1092 s->len = 0; 1093 s->state = STATE_COLLECTING_DATA; 1094 } else { 1095 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1096 "DIO or QIO mode\n", s->cmd_in_progress); 1097 } 1098 break; 1099 case DPP: 1100 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1101 s->needed_bytes = get_addr_length(s); 1102 s->pos = 0; 1103 s->len = 0; 1104 s->state = STATE_COLLECTING_DATA; 1105 } else { 1106 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1107 "QIO mode\n", s->cmd_in_progress); 1108 } 1109 break; 1110 case QPP: 1111 case QPP_4: 1112 case PP4_4: 1113 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1114 s->needed_bytes = get_addr_length(s); 1115 s->pos = 0; 1116 s->len = 0; 1117 s->state = STATE_COLLECTING_DATA; 1118 } else { 1119 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1120 "DIO mode\n", s->cmd_in_progress); 1121 } 1122 break; 1123 1124 case FAST_READ: 1125 case FAST_READ4: 1126 decode_fast_read_cmd(s); 1127 break; 1128 case DOR: 1129 case DOR4: 1130 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1131 decode_fast_read_cmd(s); 1132 } else { 1133 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1134 "QIO mode\n", s->cmd_in_progress); 1135 } 1136 break; 1137 case QOR: 1138 case QOR4: 1139 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1140 decode_fast_read_cmd(s); 1141 } else { 1142 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1143 "DIO mode\n", s->cmd_in_progress); 1144 } 1145 break; 1146 1147 case DIOR: 1148 case DIOR4: 1149 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1150 decode_dio_read_cmd(s); 1151 } else { 1152 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1153 "QIO mode\n", s->cmd_in_progress); 1154 } 1155 break; 1156 1157 case QIOR: 1158 case QIOR4: 1159 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1160 decode_qio_read_cmd(s); 1161 } else { 1162 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1163 "DIO mode\n", s->cmd_in_progress); 1164 } 1165 break; 1166 1167 case WRSR: 1168 if (s->write_enable) { 1169 switch (get_man(s)) { 1170 case MAN_SPANSION: 1171 s->needed_bytes = 2; 1172 s->state = STATE_COLLECTING_DATA; 1173 break; 1174 case MAN_MACRONIX: 1175 s->needed_bytes = 2; 1176 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1177 break; 1178 default: 1179 s->needed_bytes = 1; 1180 s->state = STATE_COLLECTING_DATA; 1181 } 1182 s->pos = 0; 1183 } 1184 break; 1185 1186 case WRDI: 1187 s->write_enable = false; 1188 if (get_man(s) == MAN_SST) { 1189 s->aai_enable = false; 1190 } 1191 break; 1192 case WREN: 1193 s->write_enable = true; 1194 break; 1195 1196 case RDSR: 1197 s->data[0] = (!!s->write_enable) << 1; 1198 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) { 1199 s->data[0] |= (!!s->quad_enable) << 6; 1200 } 1201 if (get_man(s) == MAN_SST) { 1202 s->data[0] |= (!!s->aai_enable) << 6; 1203 } 1204 1205 s->pos = 0; 1206 s->len = 1; 1207 s->data_read_loop = true; 1208 s->state = STATE_READING_DATA; 1209 break; 1210 1211 case READ_FSR: 1212 s->data[0] = FSR_FLASH_READY; 1213 if (s->four_bytes_address_mode) { 1214 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 1215 } 1216 s->pos = 0; 1217 s->len = 1; 1218 s->data_read_loop = true; 1219 s->state = STATE_READING_DATA; 1220 break; 1221 1222 case JEDEC_READ: 1223 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1224 trace_m25p80_populated_jedec(s); 1225 for (i = 0; i < s->pi->id_len; i++) { 1226 s->data[i] = s->pi->id[i]; 1227 } 1228 for (; i < SPI_NOR_MAX_ID_LEN; i++) { 1229 s->data[i] = 0; 1230 } 1231 1232 s->len = SPI_NOR_MAX_ID_LEN; 1233 s->pos = 0; 1234 s->state = STATE_READING_DATA; 1235 } else { 1236 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read " 1237 "in DIO or QIO mode\n"); 1238 } 1239 break; 1240 1241 case RDCR: 1242 s->data[0] = s->volatile_cfg & 0xFF; 1243 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 1244 s->pos = 0; 1245 s->len = 1; 1246 s->state = STATE_READING_DATA; 1247 break; 1248 1249 case BULK_ERASE_60: 1250 case BULK_ERASE: 1251 if (s->write_enable) { 1252 trace_m25p80_chip_erase(s); 1253 flash_erase(s, 0, BULK_ERASE); 1254 } else { 1255 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 1256 "protect!\n"); 1257 } 1258 break; 1259 case NOP: 1260 break; 1261 case EN_4BYTE_ADDR: 1262 s->four_bytes_address_mode = true; 1263 break; 1264 case EX_4BYTE_ADDR: 1265 s->four_bytes_address_mode = false; 1266 break; 1267 case BRRD: 1268 case EXTEND_ADDR_READ: 1269 s->data[0] = s->ear; 1270 s->pos = 0; 1271 s->len = 1; 1272 s->state = STATE_READING_DATA; 1273 break; 1274 case BRWR: 1275 case EXTEND_ADDR_WRITE: 1276 if (s->write_enable) { 1277 s->needed_bytes = 1; 1278 s->pos = 0; 1279 s->len = 0; 1280 s->state = STATE_COLLECTING_DATA; 1281 } 1282 break; 1283 case RNVCR: 1284 s->data[0] = s->nonvolatile_cfg & 0xFF; 1285 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1286 s->pos = 0; 1287 s->len = 2; 1288 s->state = STATE_READING_DATA; 1289 break; 1290 case WNVCR: 1291 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1292 s->needed_bytes = 2; 1293 s->pos = 0; 1294 s->len = 0; 1295 s->state = STATE_COLLECTING_DATA; 1296 } 1297 break; 1298 case RVCR: 1299 s->data[0] = s->volatile_cfg & 0xFF; 1300 s->pos = 0; 1301 s->len = 1; 1302 s->state = STATE_READING_DATA; 1303 break; 1304 case WVCR: 1305 if (s->write_enable) { 1306 s->needed_bytes = 1; 1307 s->pos = 0; 1308 s->len = 0; 1309 s->state = STATE_COLLECTING_DATA; 1310 } 1311 break; 1312 case REVCR: 1313 s->data[0] = s->enh_volatile_cfg & 0xFF; 1314 s->pos = 0; 1315 s->len = 1; 1316 s->state = STATE_READING_DATA; 1317 break; 1318 case WEVCR: 1319 if (s->write_enable) { 1320 s->needed_bytes = 1; 1321 s->pos = 0; 1322 s->len = 0; 1323 s->state = STATE_COLLECTING_DATA; 1324 } 1325 break; 1326 case RESET_ENABLE: 1327 s->reset_enable = true; 1328 break; 1329 case RESET_MEMORY: 1330 if (s->reset_enable) { 1331 reset_memory(s); 1332 } 1333 break; 1334 case RDCR_EQIO: 1335 switch (get_man(s)) { 1336 case MAN_SPANSION: 1337 s->data[0] = (!!s->quad_enable) << 1; 1338 s->pos = 0; 1339 s->len = 1; 1340 s->state = STATE_READING_DATA; 1341 break; 1342 case MAN_MACRONIX: 1343 s->quad_enable = true; 1344 break; 1345 default: 1346 break; 1347 } 1348 break; 1349 case RSTQIO: 1350 s->quad_enable = false; 1351 break; 1352 case AAI_WP: 1353 if (get_man(s) == MAN_SST) { 1354 if (s->write_enable) { 1355 if (s->aai_enable) { 1356 s->state = STATE_PAGE_PROGRAM; 1357 } else { 1358 s->aai_enable = true; 1359 s->needed_bytes = get_addr_length(s); 1360 s->state = STATE_COLLECTING_DATA; 1361 } 1362 } else { 1363 qemu_log_mask(LOG_GUEST_ERROR, 1364 "M25P80: AAI_WP with write protect\n"); 1365 } 1366 } else { 1367 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1368 } 1369 break; 1370 default: 1371 s->pos = 0; 1372 s->len = 1; 1373 s->state = STATE_READING_DATA; 1374 s->data_read_loop = true; 1375 s->data[0] = 0; 1376 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1377 break; 1378 } 1379 } 1380 1381 static int m25p80_cs(SSIPeripheral *ss, bool select) 1382 { 1383 Flash *s = M25P80(ss); 1384 1385 if (select) { 1386 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1387 complete_collecting_data(s); 1388 } 1389 s->len = 0; 1390 s->pos = 0; 1391 s->state = STATE_IDLE; 1392 flash_sync_dirty(s, -1); 1393 s->data_read_loop = false; 1394 } 1395 1396 trace_m25p80_select(s, select ? "de" : ""); 1397 1398 return 0; 1399 } 1400 1401 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) 1402 { 1403 Flash *s = M25P80(ss); 1404 uint32_t r = 0; 1405 1406 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, 1407 s->cur_addr, (uint8_t)tx); 1408 1409 switch (s->state) { 1410 1411 case STATE_PAGE_PROGRAM: 1412 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); 1413 flash_write8(s, s->cur_addr, (uint8_t)tx); 1414 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1415 1416 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) { 1417 /* 1418 * There is no wrap mode during AAI programming once the highest 1419 * unprotected memory address is reached. The Write-Enable-Latch 1420 * bit is automatically reset, and AAI programming mode aborts. 1421 */ 1422 s->write_enable = false; 1423 s->aai_enable = false; 1424 } 1425 1426 break; 1427 1428 case STATE_READ: 1429 r = s->storage[s->cur_addr]; 1430 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); 1431 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1432 break; 1433 1434 case STATE_COLLECTING_DATA: 1435 case STATE_COLLECTING_VAR_LEN_DATA: 1436 1437 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1438 qemu_log_mask(LOG_GUEST_ERROR, 1439 "M25P80: Write overrun internal data buffer. " 1440 "SPI controller (QEMU emulator or guest driver) " 1441 "is misbehaving\n"); 1442 s->len = s->pos = 0; 1443 s->state = STATE_IDLE; 1444 break; 1445 } 1446 1447 s->data[s->len] = (uint8_t)tx; 1448 s->len++; 1449 1450 if (s->len == s->needed_bytes) { 1451 complete_collecting_data(s); 1452 } 1453 break; 1454 1455 case STATE_READING_DATA: 1456 1457 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1458 qemu_log_mask(LOG_GUEST_ERROR, 1459 "M25P80: Read overrun internal data buffer. " 1460 "SPI controller (QEMU emulator or guest driver) " 1461 "is misbehaving\n"); 1462 s->len = s->pos = 0; 1463 s->state = STATE_IDLE; 1464 break; 1465 } 1466 1467 r = s->data[s->pos]; 1468 trace_m25p80_read_data(s, s->pos, (uint8_t)r); 1469 s->pos++; 1470 if (s->pos == s->len) { 1471 s->pos = 0; 1472 if (!s->data_read_loop) { 1473 s->state = STATE_IDLE; 1474 } 1475 } 1476 break; 1477 1478 default: 1479 case STATE_IDLE: 1480 decode_new_cmd(s, (uint8_t)tx); 1481 break; 1482 } 1483 1484 return r; 1485 } 1486 1487 static void m25p80_realize(SSIPeripheral *ss, Error **errp) 1488 { 1489 Flash *s = M25P80(ss); 1490 M25P80Class *mc = M25P80_GET_CLASS(s); 1491 int ret; 1492 1493 s->pi = mc->pi; 1494 1495 s->size = s->pi->sector_size * s->pi->n_sectors; 1496 s->dirty_page = -1; 1497 1498 if (s->blk) { 1499 uint64_t perm = BLK_PERM_CONSISTENT_READ | 1500 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0); 1501 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); 1502 if (ret < 0) { 1503 return; 1504 } 1505 1506 trace_m25p80_binding(s); 1507 s->storage = blk_blockalign(s->blk, s->size); 1508 1509 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) { 1510 error_setg(errp, "failed to read the initial flash content"); 1511 return; 1512 } 1513 } else { 1514 trace_m25p80_binding_no_bdrv(s); 1515 s->storage = blk_blockalign(NULL, s->size); 1516 memset(s->storage, 0xFF, s->size); 1517 } 1518 } 1519 1520 static void m25p80_reset(DeviceState *d) 1521 { 1522 Flash *s = M25P80(d); 1523 1524 reset_memory(s); 1525 } 1526 1527 static int m25p80_pre_save(void *opaque) 1528 { 1529 flash_sync_dirty((Flash *)opaque, -1); 1530 1531 return 0; 1532 } 1533 1534 static Property m25p80_properties[] = { 1535 /* This is default value for Micron flash */ 1536 DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false), 1537 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1538 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1539 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1540 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1541 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1542 DEFINE_PROP_DRIVE("drive", Flash, blk), 1543 DEFINE_PROP_END_OF_LIST(), 1544 }; 1545 1546 static int m25p80_pre_load(void *opaque) 1547 { 1548 Flash *s = (Flash *)opaque; 1549 1550 s->data_read_loop = false; 1551 return 0; 1552 } 1553 1554 static bool m25p80_data_read_loop_needed(void *opaque) 1555 { 1556 Flash *s = (Flash *)opaque; 1557 1558 return s->data_read_loop; 1559 } 1560 1561 static const VMStateDescription vmstate_m25p80_data_read_loop = { 1562 .name = "m25p80/data_read_loop", 1563 .version_id = 1, 1564 .minimum_version_id = 1, 1565 .needed = m25p80_data_read_loop_needed, 1566 .fields = (VMStateField[]) { 1567 VMSTATE_BOOL(data_read_loop, Flash), 1568 VMSTATE_END_OF_LIST() 1569 } 1570 }; 1571 1572 static bool m25p80_aai_enable_needed(void *opaque) 1573 { 1574 Flash *s = (Flash *)opaque; 1575 1576 return s->aai_enable; 1577 } 1578 1579 static const VMStateDescription vmstate_m25p80_aai_enable = { 1580 .name = "m25p80/aai_enable", 1581 .version_id = 1, 1582 .minimum_version_id = 1, 1583 .needed = m25p80_aai_enable_needed, 1584 .fields = (VMStateField[]) { 1585 VMSTATE_BOOL(aai_enable, Flash), 1586 VMSTATE_END_OF_LIST() 1587 } 1588 }; 1589 1590 static const VMStateDescription vmstate_m25p80 = { 1591 .name = "m25p80", 1592 .version_id = 0, 1593 .minimum_version_id = 0, 1594 .pre_save = m25p80_pre_save, 1595 .pre_load = m25p80_pre_load, 1596 .fields = (VMStateField[]) { 1597 VMSTATE_UINT8(state, Flash), 1598 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1599 VMSTATE_UINT32(len, Flash), 1600 VMSTATE_UINT32(pos, Flash), 1601 VMSTATE_UINT8(needed_bytes, Flash), 1602 VMSTATE_UINT8(cmd_in_progress, Flash), 1603 VMSTATE_UINT32(cur_addr, Flash), 1604 VMSTATE_BOOL(write_enable, Flash), 1605 VMSTATE_BOOL(reset_enable, Flash), 1606 VMSTATE_UINT8(ear, Flash), 1607 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1608 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1609 VMSTATE_UINT32(volatile_cfg, Flash), 1610 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1611 VMSTATE_BOOL(quad_enable, Flash), 1612 VMSTATE_UINT8(spansion_cr1nv, Flash), 1613 VMSTATE_UINT8(spansion_cr2nv, Flash), 1614 VMSTATE_UINT8(spansion_cr3nv, Flash), 1615 VMSTATE_UINT8(spansion_cr4nv, Flash), 1616 VMSTATE_END_OF_LIST() 1617 }, 1618 .subsections = (const VMStateDescription * []) { 1619 &vmstate_m25p80_data_read_loop, 1620 &vmstate_m25p80_aai_enable, 1621 NULL 1622 } 1623 }; 1624 1625 static void m25p80_class_init(ObjectClass *klass, void *data) 1626 { 1627 DeviceClass *dc = DEVICE_CLASS(klass); 1628 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); 1629 M25P80Class *mc = M25P80_CLASS(klass); 1630 1631 k->realize = m25p80_realize; 1632 k->transfer = m25p80_transfer8; 1633 k->set_cs = m25p80_cs; 1634 k->cs_polarity = SSI_CS_LOW; 1635 dc->vmsd = &vmstate_m25p80; 1636 device_class_set_props(dc, m25p80_properties); 1637 dc->reset = m25p80_reset; 1638 mc->pi = data; 1639 } 1640 1641 static const TypeInfo m25p80_info = { 1642 .name = TYPE_M25P80, 1643 .parent = TYPE_SSI_PERIPHERAL, 1644 .instance_size = sizeof(Flash), 1645 .class_size = sizeof(M25P80Class), 1646 .abstract = true, 1647 }; 1648 1649 static void m25p80_register_types(void) 1650 { 1651 int i; 1652 1653 type_register_static(&m25p80_info); 1654 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1655 TypeInfo ti = { 1656 .name = known_devices[i].part_name, 1657 .parent = TYPE_M25P80, 1658 .class_init = m25p80_class_init, 1659 .class_data = (void *)&known_devices[i], 1660 }; 1661 type_register(&ti); 1662 } 1663 } 1664 1665 type_init(m25p80_register_types) 1666