xref: /openbmc/qemu/hw/block/m25p80.c (revision 8fa3b702)
1 /*
2  * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3  * set. Known devices table current as of Jun/2012 and taken from linux.
4  * See drivers/mtd/devices/m25p80.c.
5  *
6  * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7  * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8  * Copyright (C) 2012 PetaLogix
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 or
13  * (at your option) a later version of the License.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License along
21  * with this program; if not, see <http://www.gnu.org/licenses/>.
22  */
23 
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/ssi/ssi.h"
29 #include "migration/vmstate.h"
30 #include "qemu/bitops.h"
31 #include "qemu/log.h"
32 #include "qemu/module.h"
33 #include "qemu/error-report.h"
34 #include "qapi/error.h"
35 #include "trace.h"
36 #include "qom/object.h"
37 
38 /* Fields for FlashPartInfo->flags */
39 
40 /* erase capabilities */
41 #define ER_4K 1
42 #define ER_32K 2
43 /* set to allow the page program command to write 0s back to 1. Useful for
44  * modelling EEPROM with SPI flash command set
45  */
46 #define EEPROM 0x100
47 
48 /* 16 MiB max in 3 byte address mode */
49 #define MAX_3BYTES_SIZE 0x1000000
50 
51 #define SPI_NOR_MAX_ID_LEN 6
52 
53 typedef struct FlashPartInfo {
54     const char *part_name;
55     /*
56      * This array stores the ID bytes.
57      * The first three bytes are the JEDIC ID.
58      * JEDEC ID zero means "no ID" (mostly older chips).
59      */
60     uint8_t id[SPI_NOR_MAX_ID_LEN];
61     uint8_t id_len;
62     /* there is confusion between manufacturers as to what a sector is. In this
63      * device model, a "sector" is the size that is erased by the ERASE_SECTOR
64      * command (opcode 0xd8).
65      */
66     uint32_t sector_size;
67     uint32_t n_sectors;
68     uint32_t page_size;
69     uint16_t flags;
70     /*
71      * Big sized spi nor are often stacked devices, thus sometime
72      * replace chip erase with die erase.
73      * This field inform how many die is in the chip.
74      */
75     uint8_t die_cnt;
76 } FlashPartInfo;
77 
78 /* adapted from linux */
79 /* Used when the "_ext_id" is two bytes at most */
80 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
81     .part_name = _part_name,\
82     .id = {\
83         ((_jedec_id) >> 16) & 0xff,\
84         ((_jedec_id) >> 8) & 0xff,\
85         (_jedec_id) & 0xff,\
86         ((_ext_id) >> 8) & 0xff,\
87         (_ext_id) & 0xff,\
88           },\
89     .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
90     .sector_size = (_sector_size),\
91     .n_sectors = (_n_sectors),\
92     .page_size = 256,\
93     .flags = (_flags),\
94     .die_cnt = 0
95 
96 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
97     .part_name = _part_name,\
98     .id = {\
99         ((_jedec_id) >> 16) & 0xff,\
100         ((_jedec_id) >> 8) & 0xff,\
101         (_jedec_id) & 0xff,\
102         ((_ext_id) >> 16) & 0xff,\
103         ((_ext_id) >> 8) & 0xff,\
104         (_ext_id) & 0xff,\
105           },\
106     .id_len = 6,\
107     .sector_size = (_sector_size),\
108     .n_sectors = (_n_sectors),\
109     .page_size = 256,\
110     .flags = (_flags),\
111     .die_cnt = 0
112 
113 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
114                     _flags, _die_cnt)\
115     .part_name = _part_name,\
116     .id = {\
117         ((_jedec_id) >> 16) & 0xff,\
118         ((_jedec_id) >> 8) & 0xff,\
119         (_jedec_id) & 0xff,\
120         ((_ext_id) >> 8) & 0xff,\
121         (_ext_id) & 0xff,\
122           },\
123     .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
124     .sector_size = (_sector_size),\
125     .n_sectors = (_n_sectors),\
126     .page_size = 256,\
127     .flags = (_flags),\
128     .die_cnt = _die_cnt
129 
130 #define JEDEC_NUMONYX 0x20
131 #define JEDEC_WINBOND 0xEF
132 #define JEDEC_SPANSION 0x01
133 
134 /* Numonyx (Micron) Configuration register macros */
135 #define VCFG_DUMMY 0x1
136 #define VCFG_WRAP_SEQUENTIAL 0x2
137 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
138 #define NVCFG_XIP_MODE_MASK (7 << 9)
139 #define VCFG_XIP_MODE_ENABLED (1 << 3)
140 #define CFG_DUMMY_CLK_LEN 4
141 #define NVCFG_DUMMY_CLK_POS 12
142 #define VCFG_DUMMY_CLK_POS 4
143 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7
144 #define EVCFG_VPP_ACCELERATOR (1 << 3)
145 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
146 #define NVCFG_DUAL_IO_MASK (1 << 2)
147 #define EVCFG_DUAL_IO_ENABLED (1 << 6)
148 #define NVCFG_QUAD_IO_MASK (1 << 3)
149 #define EVCFG_QUAD_IO_ENABLED (1 << 7)
150 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
151 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
152 
153 /* Numonyx (Micron) Flag Status Register macros */
154 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
155 #define FSR_FLASH_READY (1 << 7)
156 
157 /* Spansion configuration registers macros. */
158 #define SPANSION_QUAD_CFG_POS 0
159 #define SPANSION_QUAD_CFG_LEN 1
160 #define SPANSION_DUMMY_CLK_POS 0
161 #define SPANSION_DUMMY_CLK_LEN 4
162 #define SPANSION_ADDR_LEN_POS 7
163 #define SPANSION_ADDR_LEN_LEN 1
164 
165 /*
166  * Spansion read mode command length in bytes,
167  * the mode is currently not supported.
168 */
169 
170 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
171 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
172 
173 static const FlashPartInfo known_devices[] = {
174     /* Atmel -- some are (confusingly) marketed as "DataFlash" */
175     { INFO("at25fs010",   0x1f6601,      0,  32 << 10,   4, ER_4K) },
176     { INFO("at25fs040",   0x1f6604,      0,  64 << 10,   8, ER_4K) },
177 
178     { INFO("at25df041a",  0x1f4401,      0,  64 << 10,   8, ER_4K) },
179     { INFO("at25df321a",  0x1f4701,      0,  64 << 10,  64, ER_4K) },
180     { INFO("at25df641",   0x1f4800,      0,  64 << 10, 128, ER_4K) },
181 
182     { INFO("at26f004",    0x1f0400,      0,  64 << 10,   8, ER_4K) },
183     { INFO("at26df081a",  0x1f4501,      0,  64 << 10,  16, ER_4K) },
184     { INFO("at26df161a",  0x1f4601,      0,  64 << 10,  32, ER_4K) },
185     { INFO("at26df321",   0x1f4700,      0,  64 << 10,  64, ER_4K) },
186 
187     { INFO("at45db081d",  0x1f2500,      0,  64 << 10,  16, ER_4K) },
188 
189     /* Atmel EEPROMS - it is assumed, that don't care bit in command
190      * is set to 0. Block protection is not supported.
191      */
192     { INFO("at25128a-nonjedec", 0x0,     0,         1, 131072, EEPROM) },
193     { INFO("at25256a-nonjedec", 0x0,     0,         1, 262144, EEPROM) },
194 
195     /* EON -- en25xxx */
196     { INFO("en25f32",     0x1c3116,      0,  64 << 10,  64, ER_4K) },
197     { INFO("en25p32",     0x1c2016,      0,  64 << 10,  64, 0) },
198     { INFO("en25q32b",    0x1c3016,      0,  64 << 10,  64, 0) },
199     { INFO("en25p64",     0x1c2017,      0,  64 << 10, 128, 0) },
200     { INFO("en25q64",     0x1c3017,      0,  64 << 10, 128, ER_4K) },
201 
202     /* GigaDevice */
203     { INFO("gd25q32",     0xc84016,      0,  64 << 10,  64, ER_4K) },
204     { INFO("gd25q64",     0xc84017,      0,  64 << 10, 128, ER_4K) },
205 
206     /* Intel/Numonyx -- xxxs33b */
207     { INFO("160s33b",     0x898911,      0,  64 << 10,  32, 0) },
208     { INFO("320s33b",     0x898912,      0,  64 << 10,  64, 0) },
209     { INFO("640s33b",     0x898913,      0,  64 << 10, 128, 0) },
210     { INFO("n25q064",     0x20ba17,      0,  64 << 10, 128, 0) },
211 
212     /* Macronix */
213     { INFO("mx25l2005a",  0xc22012,      0,  64 << 10,   4, ER_4K) },
214     { INFO("mx25l4005a",  0xc22013,      0,  64 << 10,   8, ER_4K) },
215     { INFO("mx25l8005",   0xc22014,      0,  64 << 10,  16, 0) },
216     { INFO("mx25l1606e",  0xc22015,      0,  64 << 10,  32, ER_4K) },
217     { INFO("mx25l3205d",  0xc22016,      0,  64 << 10,  64, 0) },
218     { INFO("mx25l6405d",  0xc22017,      0,  64 << 10, 128, 0) },
219     { INFO("mx25l12805d", 0xc22018,      0,  64 << 10, 256, 0) },
220     { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
221     { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512, 0) },
222     { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
223     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
224     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
225     { INFO("mx66u1g45g",  0xc2253b,      0,  64 << 10, 2048, ER_4K | ER_32K) },
226     { INFO("mx66l1g45g",  0xc2201b,      0,  64 << 10, 2048, ER_4K | ER_32K) },
227 
228     /* Micron */
229     { INFO("n25q032a11",  0x20bb16,      0,  64 << 10,  64, ER_4K) },
230     { INFO("n25q032a13",  0x20ba16,      0,  64 << 10,  64, ER_4K) },
231     { INFO("n25q064a11",  0x20bb17,      0,  64 << 10, 128, ER_4K) },
232     { INFO("n25q064a13",  0x20ba17,      0,  64 << 10, 128, ER_4K) },
233     { INFO("n25q128a11",  0x20bb18,      0,  64 << 10, 256, ER_4K) },
234     { INFO("n25q128a13",  0x20ba18,      0,  64 << 10, 256, ER_4K) },
235     { INFO("n25q256a11",  0x20bb19,      0,  64 << 10, 512, ER_4K) },
236     { INFO("n25q256a13",  0x20ba19,      0,  64 << 10, 512, ER_4K) },
237     { INFO("n25q512a11",  0x20bb20,      0,  64 << 10, 1024, ER_4K) },
238     { INFO("n25q512a13",  0x20ba20,      0,  64 << 10, 1024, ER_4K) },
239     { INFO("n25q128",     0x20ba18,      0,  64 << 10, 256, 0) },
240     { INFO("n25q256a",    0x20ba19,      0,  64 << 10, 512, ER_4K) },
241     { INFO("n25q512a",    0x20ba20,      0,  64 << 10, 1024, ER_4K) },
242     { INFO("n25q512ax3",  0x20ba20,  0x1000,  64 << 10, 1024, ER_4K) },
243     { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
244     { INFO_STACKED("n25q00",    0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
245     { INFO_STACKED("n25q00a",   0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
246     { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
247     { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
248 
249     /* Spansion -- single (large) sector size only, at least
250      * for the chips listed here (without boot sectors).
251      */
252     { INFO("s25sl032p",   0x010215, 0x4d00,  64 << 10,  64, ER_4K) },
253     { INFO("s25sl064p",   0x010216, 0x4d00,  64 << 10, 128, ER_4K) },
254     { INFO("s25fl256s0",  0x010219, 0x4d00, 256 << 10, 128, 0) },
255     { INFO("s25fl256s1",  0x010219, 0x4d01,  64 << 10, 512, 0) },
256     { INFO6("s25fl512s",  0x010220, 0x4d0080, 256 << 10, 256, 0) },
257     { INFO6("s70fl01gs",  0x010221, 0x4d0080, 256 << 10, 512, 0) },
258     { INFO("s25sl12800",  0x012018, 0x0300, 256 << 10,  64, 0) },
259     { INFO("s25sl12801",  0x012018, 0x0301,  64 << 10, 256, 0) },
260     { INFO("s25fl129p0",  0x012018, 0x4d00, 256 << 10,  64, 0) },
261     { INFO("s25fl129p1",  0x012018, 0x4d01,  64 << 10, 256, 0) },
262     { INFO("s25sl004a",   0x010212,      0,  64 << 10,   8, 0) },
263     { INFO("s25sl008a",   0x010213,      0,  64 << 10,  16, 0) },
264     { INFO("s25sl016a",   0x010214,      0,  64 << 10,  32, 0) },
265     { INFO("s25sl032a",   0x010215,      0,  64 << 10,  64, 0) },
266     { INFO("s25sl064a",   0x010216,      0,  64 << 10, 128, 0) },
267     { INFO("s25fl016k",   0xef4015,      0,  64 << 10,  32, ER_4K | ER_32K) },
268     { INFO("s25fl064k",   0xef4017,      0,  64 << 10, 128, ER_4K | ER_32K) },
269 
270     /* Spansion --  boot sectors support  */
271     { INFO6("s25fs512s",    0x010220, 0x4d0081, 256 << 10, 256, 0) },
272     { INFO6("s70fs01gs",    0x010221, 0x4d0081, 256 << 10, 512, 0) },
273 
274     /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
275     { INFO("sst25vf040b", 0xbf258d,      0,  64 << 10,   8, ER_4K) },
276     { INFO("sst25vf080b", 0xbf258e,      0,  64 << 10,  16, ER_4K) },
277     { INFO("sst25vf016b", 0xbf2541,      0,  64 << 10,  32, ER_4K) },
278     { INFO("sst25vf032b", 0xbf254a,      0,  64 << 10,  64, ER_4K) },
279     { INFO("sst25wf512",  0xbf2501,      0,  64 << 10,   1, ER_4K) },
280     { INFO("sst25wf010",  0xbf2502,      0,  64 << 10,   2, ER_4K) },
281     { INFO("sst25wf020",  0xbf2503,      0,  64 << 10,   4, ER_4K) },
282     { INFO("sst25wf040",  0xbf2504,      0,  64 << 10,   8, ER_4K) },
283     { INFO("sst25wf080",  0xbf2505,      0,  64 << 10,  16, ER_4K) },
284 
285     /* ST Microelectronics -- newer production may have feature updates */
286     { INFO("m25p05",      0x202010,      0,  32 << 10,   2, 0) },
287     { INFO("m25p10",      0x202011,      0,  32 << 10,   4, 0) },
288     { INFO("m25p20",      0x202012,      0,  64 << 10,   4, 0) },
289     { INFO("m25p40",      0x202013,      0,  64 << 10,   8, 0) },
290     { INFO("m25p80",      0x202014,      0,  64 << 10,  16, 0) },
291     { INFO("m25p16",      0x202015,      0,  64 << 10,  32, 0) },
292     { INFO("m25p32",      0x202016,      0,  64 << 10,  64, 0) },
293     { INFO("m25p64",      0x202017,      0,  64 << 10, 128, 0) },
294     { INFO("m25p128",     0x202018,      0, 256 << 10,  64, 0) },
295     { INFO("n25q032",     0x20ba16,      0,  64 << 10,  64, 0) },
296 
297     { INFO("m45pe10",     0x204011,      0,  64 << 10,   2, 0) },
298     { INFO("m45pe80",     0x204014,      0,  64 << 10,  16, 0) },
299     { INFO("m45pe16",     0x204015,      0,  64 << 10,  32, 0) },
300 
301     { INFO("m25pe20",     0x208012,      0,  64 << 10,   4, 0) },
302     { INFO("m25pe80",     0x208014,      0,  64 << 10,  16, 0) },
303     { INFO("m25pe16",     0x208015,      0,  64 << 10,  32, ER_4K) },
304 
305     { INFO("m25px32",     0x207116,      0,  64 << 10,  64, ER_4K) },
306     { INFO("m25px32-s0",  0x207316,      0,  64 << 10,  64, ER_4K) },
307     { INFO("m25px32-s1",  0x206316,      0,  64 << 10,  64, ER_4K) },
308     { INFO("m25px64",     0x207117,      0,  64 << 10, 128, 0) },
309 
310     /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
311     { INFO("w25x10",      0xef3011,      0,  64 << 10,   2, ER_4K) },
312     { INFO("w25x20",      0xef3012,      0,  64 << 10,   4, ER_4K) },
313     { INFO("w25x40",      0xef3013,      0,  64 << 10,   8, ER_4K) },
314     { INFO("w25x80",      0xef3014,      0,  64 << 10,  16, ER_4K) },
315     { INFO("w25x16",      0xef3015,      0,  64 << 10,  32, ER_4K) },
316     { INFO("w25x32",      0xef3016,      0,  64 << 10,  64, ER_4K) },
317     { INFO("w25q32",      0xef4016,      0,  64 << 10,  64, ER_4K) },
318     { INFO("w25q32dw",    0xef6016,      0,  64 << 10,  64, ER_4K) },
319     { INFO("w25x64",      0xef3017,      0,  64 << 10, 128, ER_4K) },
320     { INFO("w25q64",      0xef4017,      0,  64 << 10, 128, ER_4K) },
321     { INFO("w25q80",      0xef5014,      0,  64 << 10,  16, ER_4K) },
322     { INFO("w25q80bl",    0xef4014,      0,  64 << 10,  16, ER_4K) },
323     { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K) },
324     { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K) },
325 };
326 
327 typedef enum {
328     NOP = 0,
329     WRSR = 0x1,
330     WRDI = 0x4,
331     RDSR = 0x5,
332     WREN = 0x6,
333     BRRD = 0x16,
334     BRWR = 0x17,
335     JEDEC_READ = 0x9f,
336     BULK_ERASE_60 = 0x60,
337     BULK_ERASE = 0xc7,
338     READ_FSR = 0x70,
339     RDCR = 0x15,
340 
341     READ = 0x03,
342     READ4 = 0x13,
343     FAST_READ = 0x0b,
344     FAST_READ4 = 0x0c,
345     DOR = 0x3b,
346     DOR4 = 0x3c,
347     QOR = 0x6b,
348     QOR4 = 0x6c,
349     DIOR = 0xbb,
350     DIOR4 = 0xbc,
351     QIOR = 0xeb,
352     QIOR4 = 0xec,
353 
354     PP = 0x02,
355     PP4 = 0x12,
356     PP4_4 = 0x3e,
357     DPP = 0xa2,
358     QPP = 0x32,
359     QPP_4 = 0x34,
360     RDID_90 = 0x90,
361     RDID_AB = 0xab,
362 
363     ERASE_4K = 0x20,
364     ERASE4_4K = 0x21,
365     ERASE_32K = 0x52,
366     ERASE4_32K = 0x5c,
367     ERASE_SECTOR = 0xd8,
368     ERASE4_SECTOR = 0xdc,
369 
370     EN_4BYTE_ADDR = 0xB7,
371     EX_4BYTE_ADDR = 0xE9,
372 
373     EXTEND_ADDR_READ = 0xC8,
374     EXTEND_ADDR_WRITE = 0xC5,
375 
376     RESET_ENABLE = 0x66,
377     RESET_MEMORY = 0x99,
378 
379     /*
380      * Micron: 0x35 - enable QPI
381      * Spansion: 0x35 - read control register
382      */
383     RDCR_EQIO = 0x35,
384     RSTQIO = 0xf5,
385 
386     RNVCR = 0xB5,
387     WNVCR = 0xB1,
388 
389     RVCR = 0x85,
390     WVCR = 0x81,
391 
392     REVCR = 0x65,
393     WEVCR = 0x61,
394 
395     DIE_ERASE = 0xC4,
396 } FlashCMD;
397 
398 typedef enum {
399     STATE_IDLE,
400     STATE_PAGE_PROGRAM,
401     STATE_READ,
402     STATE_COLLECTING_DATA,
403     STATE_COLLECTING_VAR_LEN_DATA,
404     STATE_READING_DATA,
405 } CMDState;
406 
407 typedef enum {
408     MAN_SPANSION,
409     MAN_MACRONIX,
410     MAN_NUMONYX,
411     MAN_WINBOND,
412     MAN_SST,
413     MAN_GENERIC,
414 } Manufacturer;
415 
416 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
417 
418 struct Flash {
419     SSISlave parent_obj;
420 
421     BlockBackend *blk;
422 
423     uint8_t *storage;
424     uint32_t size;
425     int page_size;
426 
427     uint8_t state;
428     uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
429     uint32_t len;
430     uint32_t pos;
431     bool data_read_loop;
432     uint8_t needed_bytes;
433     uint8_t cmd_in_progress;
434     uint32_t cur_addr;
435     uint32_t nonvolatile_cfg;
436     /* Configuration register for Macronix */
437     uint32_t volatile_cfg;
438     uint32_t enh_volatile_cfg;
439     /* Spansion cfg registers. */
440     uint8_t spansion_cr1nv;
441     uint8_t spansion_cr2nv;
442     uint8_t spansion_cr3nv;
443     uint8_t spansion_cr4nv;
444     uint8_t spansion_cr1v;
445     uint8_t spansion_cr2v;
446     uint8_t spansion_cr3v;
447     uint8_t spansion_cr4v;
448     bool write_enable;
449     bool four_bytes_address_mode;
450     bool reset_enable;
451     bool quad_enable;
452     uint8_t ear;
453 
454     int64_t dirty_page;
455 
456     const FlashPartInfo *pi;
457 
458 };
459 typedef struct Flash Flash;
460 
461 struct M25P80Class {
462     SSISlaveClass parent_class;
463     FlashPartInfo *pi;
464 };
465 typedef struct M25P80Class M25P80Class;
466 
467 #define TYPE_M25P80 "m25p80-generic"
468 DECLARE_OBJ_CHECKERS(Flash, M25P80Class,
469                      M25P80, TYPE_M25P80)
470 
471 static inline Manufacturer get_man(Flash *s)
472 {
473     switch (s->pi->id[0]) {
474     case 0x20:
475         return MAN_NUMONYX;
476     case 0xEF:
477         return MAN_WINBOND;
478     case 0x01:
479         return MAN_SPANSION;
480     case 0xC2:
481         return MAN_MACRONIX;
482     case 0xBF:
483         return MAN_SST;
484     default:
485         return MAN_GENERIC;
486     }
487 }
488 
489 static void blk_sync_complete(void *opaque, int ret)
490 {
491     QEMUIOVector *iov = opaque;
492 
493     qemu_iovec_destroy(iov);
494     g_free(iov);
495 
496     /* do nothing. Masters do not directly interact with the backing store,
497      * only the working copy so no mutexing required.
498      */
499 }
500 
501 static void flash_sync_page(Flash *s, int page)
502 {
503     QEMUIOVector *iov;
504 
505     if (!s->blk || blk_is_read_only(s->blk)) {
506         return;
507     }
508 
509     iov = g_new(QEMUIOVector, 1);
510     qemu_iovec_init(iov, 1);
511     qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
512                    s->pi->page_size);
513     blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
514                     blk_sync_complete, iov);
515 }
516 
517 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
518 {
519     QEMUIOVector *iov;
520 
521     if (!s->blk || blk_is_read_only(s->blk)) {
522         return;
523     }
524 
525     assert(!(len % BDRV_SECTOR_SIZE));
526     iov = g_new(QEMUIOVector, 1);
527     qemu_iovec_init(iov, 1);
528     qemu_iovec_add(iov, s->storage + off, len);
529     blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
530 }
531 
532 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
533 {
534     uint32_t len;
535     uint8_t capa_to_assert = 0;
536 
537     switch (cmd) {
538     case ERASE_4K:
539     case ERASE4_4K:
540         len = 4 * KiB;
541         capa_to_assert = ER_4K;
542         break;
543     case ERASE_32K:
544     case ERASE4_32K:
545         len = 32 * KiB;
546         capa_to_assert = ER_32K;
547         break;
548     case ERASE_SECTOR:
549     case ERASE4_SECTOR:
550         len = s->pi->sector_size;
551         break;
552     case BULK_ERASE:
553         len = s->size;
554         break;
555     case DIE_ERASE:
556         if (s->pi->die_cnt) {
557             len = s->size / s->pi->die_cnt;
558             offset = offset & (~(len - 1));
559         } else {
560             qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
561                           " by device\n");
562             return;
563         }
564         break;
565     default:
566         abort();
567     }
568 
569     trace_m25p80_flash_erase(s, offset, len);
570 
571     if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
572         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
573                       " device\n", len);
574     }
575 
576     if (!s->write_enable) {
577         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
578         return;
579     }
580     memset(s->storage + offset, 0xff, len);
581     flash_sync_area(s, offset, len);
582 }
583 
584 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
585 {
586     if (s->dirty_page >= 0 && s->dirty_page != newpage) {
587         flash_sync_page(s, s->dirty_page);
588         s->dirty_page = newpage;
589     }
590 }
591 
592 static inline
593 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
594 {
595     uint32_t page = addr / s->pi->page_size;
596     uint8_t prev = s->storage[s->cur_addr];
597 
598     if (!s->write_enable) {
599         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
600     }
601 
602     if ((prev ^ data) & data) {
603         trace_m25p80_programming_zero_to_one(s, addr, prev, data);
604     }
605 
606     if (s->pi->flags & EEPROM) {
607         s->storage[s->cur_addr] = data;
608     } else {
609         s->storage[s->cur_addr] &= data;
610     }
611 
612     flash_sync_dirty(s, page);
613     s->dirty_page = page;
614 }
615 
616 static inline int get_addr_length(Flash *s)
617 {
618    /* check if eeprom is in use */
619     if (s->pi->flags == EEPROM) {
620         return 2;
621     }
622 
623    switch (s->cmd_in_progress) {
624    case PP4:
625    case PP4_4:
626    case QPP_4:
627    case READ4:
628    case QIOR4:
629    case ERASE4_4K:
630    case ERASE4_32K:
631    case ERASE4_SECTOR:
632    case FAST_READ4:
633    case DOR4:
634    case QOR4:
635    case DIOR4:
636        return 4;
637    default:
638        return s->four_bytes_address_mode ? 4 : 3;
639    }
640 }
641 
642 static void complete_collecting_data(Flash *s)
643 {
644     int i, n;
645 
646     n = get_addr_length(s);
647     s->cur_addr = (n == 3 ? s->ear : 0);
648     for (i = 0; i < n; ++i) {
649         s->cur_addr <<= 8;
650         s->cur_addr |= s->data[i];
651     }
652 
653     s->cur_addr &= s->size - 1;
654 
655     s->state = STATE_IDLE;
656 
657     trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
658                                      s->cur_addr);
659 
660     switch (s->cmd_in_progress) {
661     case DPP:
662     case QPP:
663     case QPP_4:
664     case PP:
665     case PP4:
666     case PP4_4:
667         s->state = STATE_PAGE_PROGRAM;
668         break;
669     case READ:
670     case READ4:
671     case FAST_READ:
672     case FAST_READ4:
673     case DOR:
674     case DOR4:
675     case QOR:
676     case QOR4:
677     case DIOR:
678     case DIOR4:
679     case QIOR:
680     case QIOR4:
681         s->state = STATE_READ;
682         break;
683     case ERASE_4K:
684     case ERASE4_4K:
685     case ERASE_32K:
686     case ERASE4_32K:
687     case ERASE_SECTOR:
688     case ERASE4_SECTOR:
689     case DIE_ERASE:
690         flash_erase(s, s->cur_addr, s->cmd_in_progress);
691         break;
692     case WRSR:
693         switch (get_man(s)) {
694         case MAN_SPANSION:
695             s->quad_enable = !!(s->data[1] & 0x02);
696             break;
697         case MAN_MACRONIX:
698             s->quad_enable = extract32(s->data[0], 6, 1);
699             if (s->len > 1) {
700                 s->volatile_cfg = s->data[1];
701                 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
702             }
703             break;
704         default:
705             break;
706         }
707         if (s->write_enable) {
708             s->write_enable = false;
709         }
710         break;
711     case BRWR:
712     case EXTEND_ADDR_WRITE:
713         s->ear = s->data[0];
714         break;
715     case WNVCR:
716         s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
717         break;
718     case WVCR:
719         s->volatile_cfg = s->data[0];
720         break;
721     case WEVCR:
722         s->enh_volatile_cfg = s->data[0];
723         break;
724     case RDID_90:
725     case RDID_AB:
726         if (get_man(s) == MAN_SST) {
727             if (s->cur_addr <= 1) {
728                 if (s->cur_addr) {
729                     s->data[0] = s->pi->id[2];
730                     s->data[1] = s->pi->id[0];
731                 } else {
732                     s->data[0] = s->pi->id[0];
733                     s->data[1] = s->pi->id[2];
734                 }
735                 s->pos = 0;
736                 s->len = 2;
737                 s->data_read_loop = true;
738                 s->state = STATE_READING_DATA;
739             } else {
740                 qemu_log_mask(LOG_GUEST_ERROR,
741                               "M25P80: Invalid read id address\n");
742             }
743         } else {
744             qemu_log_mask(LOG_GUEST_ERROR,
745                           "M25P80: Read id (command 0x90/0xAB) is not supported"
746                           " by device\n");
747         }
748         break;
749     default:
750         break;
751     }
752 }
753 
754 static void reset_memory(Flash *s)
755 {
756     s->cmd_in_progress = NOP;
757     s->cur_addr = 0;
758     s->ear = 0;
759     s->four_bytes_address_mode = false;
760     s->len = 0;
761     s->needed_bytes = 0;
762     s->pos = 0;
763     s->state = STATE_IDLE;
764     s->write_enable = false;
765     s->reset_enable = false;
766     s->quad_enable = false;
767 
768     switch (get_man(s)) {
769     case MAN_NUMONYX:
770         s->volatile_cfg = 0;
771         s->volatile_cfg |= VCFG_DUMMY;
772         s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
773         if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
774                                 != NVCFG_XIP_MODE_DISABLED) {
775             s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
776         }
777         s->volatile_cfg |= deposit32(s->volatile_cfg,
778                             VCFG_DUMMY_CLK_POS,
779                             CFG_DUMMY_CLK_LEN,
780                             extract32(s->nonvolatile_cfg,
781                                         NVCFG_DUMMY_CLK_POS,
782                                         CFG_DUMMY_CLK_LEN)
783                             );
784 
785         s->enh_volatile_cfg = 0;
786         s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
787         s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
788         s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
789         if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
790             s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
791         }
792         if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
793             s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
794         }
795         if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
796             s->four_bytes_address_mode = true;
797         }
798         if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
799             s->ear = s->size / MAX_3BYTES_SIZE - 1;
800         }
801         break;
802     case MAN_MACRONIX:
803         s->volatile_cfg = 0x7;
804         break;
805     case MAN_SPANSION:
806         s->spansion_cr1v = s->spansion_cr1nv;
807         s->spansion_cr2v = s->spansion_cr2nv;
808         s->spansion_cr3v = s->spansion_cr3nv;
809         s->spansion_cr4v = s->spansion_cr4nv;
810         s->quad_enable = extract32(s->spansion_cr1v,
811                                    SPANSION_QUAD_CFG_POS,
812                                    SPANSION_QUAD_CFG_LEN
813                                    );
814         s->four_bytes_address_mode = extract32(s->spansion_cr2v,
815                 SPANSION_ADDR_LEN_POS,
816                 SPANSION_ADDR_LEN_LEN
817                 );
818         break;
819     default:
820         break;
821     }
822 
823     trace_m25p80_reset_done(s);
824 }
825 
826 static void decode_fast_read_cmd(Flash *s)
827 {
828     s->needed_bytes = get_addr_length(s);
829     switch (get_man(s)) {
830     /* Dummy cycles - modeled with bytes writes instead of bits */
831     case MAN_WINBOND:
832         s->needed_bytes += 8;
833         break;
834     case MAN_NUMONYX:
835         s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
836         break;
837     case MAN_MACRONIX:
838         if (extract32(s->volatile_cfg, 6, 2) == 1) {
839             s->needed_bytes += 6;
840         } else {
841             s->needed_bytes += 8;
842         }
843         break;
844     case MAN_SPANSION:
845         s->needed_bytes += extract32(s->spansion_cr2v,
846                                     SPANSION_DUMMY_CLK_POS,
847                                     SPANSION_DUMMY_CLK_LEN
848                                     );
849         break;
850     default:
851         break;
852     }
853     s->pos = 0;
854     s->len = 0;
855     s->state = STATE_COLLECTING_DATA;
856 }
857 
858 static void decode_dio_read_cmd(Flash *s)
859 {
860     s->needed_bytes = get_addr_length(s);
861     /* Dummy cycles modeled with bytes writes instead of bits */
862     switch (get_man(s)) {
863     case MAN_WINBOND:
864         s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
865         break;
866     case MAN_SPANSION:
867         s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
868         s->needed_bytes += extract32(s->spansion_cr2v,
869                                     SPANSION_DUMMY_CLK_POS,
870                                     SPANSION_DUMMY_CLK_LEN
871                                     );
872         break;
873     case MAN_NUMONYX:
874         s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
875         break;
876     case MAN_MACRONIX:
877         switch (extract32(s->volatile_cfg, 6, 2)) {
878         case 1:
879             s->needed_bytes += 6;
880             break;
881         case 2:
882             s->needed_bytes += 8;
883             break;
884         default:
885             s->needed_bytes += 4;
886             break;
887         }
888         break;
889     default:
890         break;
891     }
892     s->pos = 0;
893     s->len = 0;
894     s->state = STATE_COLLECTING_DATA;
895 }
896 
897 static void decode_qio_read_cmd(Flash *s)
898 {
899     s->needed_bytes = get_addr_length(s);
900     /* Dummy cycles modeled with bytes writes instead of bits */
901     switch (get_man(s)) {
902     case MAN_WINBOND:
903         s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
904         s->needed_bytes += 4;
905         break;
906     case MAN_SPANSION:
907         s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
908         s->needed_bytes += extract32(s->spansion_cr2v,
909                                     SPANSION_DUMMY_CLK_POS,
910                                     SPANSION_DUMMY_CLK_LEN
911                                     );
912         break;
913     case MAN_NUMONYX:
914         s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
915         break;
916     case MAN_MACRONIX:
917         switch (extract32(s->volatile_cfg, 6, 2)) {
918         case 1:
919             s->needed_bytes += 4;
920             break;
921         case 2:
922             s->needed_bytes += 8;
923             break;
924         default:
925             s->needed_bytes += 6;
926             break;
927         }
928         break;
929     default:
930         break;
931     }
932     s->pos = 0;
933     s->len = 0;
934     s->state = STATE_COLLECTING_DATA;
935 }
936 
937 static void decode_new_cmd(Flash *s, uint32_t value)
938 {
939     int i;
940 
941     s->cmd_in_progress = value;
942     trace_m25p80_command_decoded(s, value);
943 
944     if (value != RESET_MEMORY) {
945         s->reset_enable = false;
946     }
947 
948     switch (value) {
949 
950     case ERASE_4K:
951     case ERASE4_4K:
952     case ERASE_32K:
953     case ERASE4_32K:
954     case ERASE_SECTOR:
955     case ERASE4_SECTOR:
956     case READ:
957     case READ4:
958     case DPP:
959     case QPP:
960     case QPP_4:
961     case PP:
962     case PP4:
963     case PP4_4:
964     case DIE_ERASE:
965     case RDID_90:
966     case RDID_AB:
967         s->needed_bytes = get_addr_length(s);
968         s->pos = 0;
969         s->len = 0;
970         s->state = STATE_COLLECTING_DATA;
971         break;
972 
973     case FAST_READ:
974     case FAST_READ4:
975     case DOR:
976     case DOR4:
977     case QOR:
978     case QOR4:
979         decode_fast_read_cmd(s);
980         break;
981 
982     case DIOR:
983     case DIOR4:
984         decode_dio_read_cmd(s);
985         break;
986 
987     case QIOR:
988     case QIOR4:
989         decode_qio_read_cmd(s);
990         break;
991 
992     case WRSR:
993         if (s->write_enable) {
994             switch (get_man(s)) {
995             case MAN_SPANSION:
996                 s->needed_bytes = 2;
997                 s->state = STATE_COLLECTING_DATA;
998                 break;
999             case MAN_MACRONIX:
1000                 s->needed_bytes = 2;
1001                 s->state = STATE_COLLECTING_VAR_LEN_DATA;
1002                 break;
1003             default:
1004                 s->needed_bytes = 1;
1005                 s->state = STATE_COLLECTING_DATA;
1006             }
1007             s->pos = 0;
1008         }
1009         break;
1010 
1011     case WRDI:
1012         s->write_enable = false;
1013         break;
1014     case WREN:
1015         s->write_enable = true;
1016         break;
1017 
1018     case RDSR:
1019         s->data[0] = (!!s->write_enable) << 1;
1020         if (get_man(s) == MAN_MACRONIX) {
1021             s->data[0] |= (!!s->quad_enable) << 6;
1022         }
1023         s->pos = 0;
1024         s->len = 1;
1025         s->data_read_loop = true;
1026         s->state = STATE_READING_DATA;
1027         break;
1028 
1029     case READ_FSR:
1030         s->data[0] = FSR_FLASH_READY;
1031         if (s->four_bytes_address_mode) {
1032             s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
1033         }
1034         s->pos = 0;
1035         s->len = 1;
1036         s->data_read_loop = true;
1037         s->state = STATE_READING_DATA;
1038         break;
1039 
1040     case JEDEC_READ:
1041         trace_m25p80_populated_jedec(s);
1042         for (i = 0; i < s->pi->id_len; i++) {
1043             s->data[i] = s->pi->id[i];
1044         }
1045         for (; i < SPI_NOR_MAX_ID_LEN; i++) {
1046             s->data[i] = 0;
1047         }
1048 
1049         s->len = SPI_NOR_MAX_ID_LEN;
1050         s->pos = 0;
1051         s->state = STATE_READING_DATA;
1052         break;
1053 
1054     case RDCR:
1055         s->data[0] = s->volatile_cfg & 0xFF;
1056         s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1057         s->pos = 0;
1058         s->len = 1;
1059         s->state = STATE_READING_DATA;
1060         break;
1061 
1062     case BULK_ERASE_60:
1063     case BULK_ERASE:
1064         if (s->write_enable) {
1065             trace_m25p80_chip_erase(s);
1066             flash_erase(s, 0, BULK_ERASE);
1067         } else {
1068             qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1069                           "protect!\n");
1070         }
1071         break;
1072     case NOP:
1073         break;
1074     case EN_4BYTE_ADDR:
1075         s->four_bytes_address_mode = true;
1076         break;
1077     case EX_4BYTE_ADDR:
1078         s->four_bytes_address_mode = false;
1079         break;
1080     case BRRD:
1081     case EXTEND_ADDR_READ:
1082         s->data[0] = s->ear;
1083         s->pos = 0;
1084         s->len = 1;
1085         s->state = STATE_READING_DATA;
1086         break;
1087     case BRWR:
1088     case EXTEND_ADDR_WRITE:
1089         if (s->write_enable) {
1090             s->needed_bytes = 1;
1091             s->pos = 0;
1092             s->len = 0;
1093             s->state = STATE_COLLECTING_DATA;
1094         }
1095         break;
1096     case RNVCR:
1097         s->data[0] = s->nonvolatile_cfg & 0xFF;
1098         s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1099         s->pos = 0;
1100         s->len = 2;
1101         s->state = STATE_READING_DATA;
1102         break;
1103     case WNVCR:
1104         if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1105             s->needed_bytes = 2;
1106             s->pos = 0;
1107             s->len = 0;
1108             s->state = STATE_COLLECTING_DATA;
1109         }
1110         break;
1111     case RVCR:
1112         s->data[0] = s->volatile_cfg & 0xFF;
1113         s->pos = 0;
1114         s->len = 1;
1115         s->state = STATE_READING_DATA;
1116         break;
1117     case WVCR:
1118         if (s->write_enable) {
1119             s->needed_bytes = 1;
1120             s->pos = 0;
1121             s->len = 0;
1122             s->state = STATE_COLLECTING_DATA;
1123         }
1124         break;
1125     case REVCR:
1126         s->data[0] = s->enh_volatile_cfg & 0xFF;
1127         s->pos = 0;
1128         s->len = 1;
1129         s->state = STATE_READING_DATA;
1130         break;
1131     case WEVCR:
1132         if (s->write_enable) {
1133             s->needed_bytes = 1;
1134             s->pos = 0;
1135             s->len = 0;
1136             s->state = STATE_COLLECTING_DATA;
1137         }
1138         break;
1139     case RESET_ENABLE:
1140         s->reset_enable = true;
1141         break;
1142     case RESET_MEMORY:
1143         if (s->reset_enable) {
1144             reset_memory(s);
1145         }
1146         break;
1147     case RDCR_EQIO:
1148         switch (get_man(s)) {
1149         case MAN_SPANSION:
1150             s->data[0] = (!!s->quad_enable) << 1;
1151             s->pos = 0;
1152             s->len = 1;
1153             s->state = STATE_READING_DATA;
1154             break;
1155         case MAN_MACRONIX:
1156             s->quad_enable = true;
1157             break;
1158         default:
1159             break;
1160         }
1161         break;
1162     case RSTQIO:
1163         s->quad_enable = false;
1164         break;
1165     default:
1166         s->pos = 0;
1167         s->len = 1;
1168         s->state = STATE_READING_DATA;
1169         s->data_read_loop = true;
1170         s->data[0] = 0;
1171         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1172         break;
1173     }
1174 }
1175 
1176 static int m25p80_cs(SSISlave *ss, bool select)
1177 {
1178     Flash *s = M25P80(ss);
1179 
1180     if (select) {
1181         if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1182             complete_collecting_data(s);
1183         }
1184         s->len = 0;
1185         s->pos = 0;
1186         s->state = STATE_IDLE;
1187         flash_sync_dirty(s, -1);
1188         s->data_read_loop = false;
1189     }
1190 
1191     trace_m25p80_select(s, select ? "de" : "");
1192 
1193     return 0;
1194 }
1195 
1196 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
1197 {
1198     Flash *s = M25P80(ss);
1199     uint32_t r = 0;
1200 
1201     trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
1202                           s->cur_addr, (uint8_t)tx);
1203 
1204     switch (s->state) {
1205 
1206     case STATE_PAGE_PROGRAM:
1207         trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
1208         flash_write8(s, s->cur_addr, (uint8_t)tx);
1209         s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1210         break;
1211 
1212     case STATE_READ:
1213         r = s->storage[s->cur_addr];
1214         trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
1215         s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1216         break;
1217 
1218     case STATE_COLLECTING_DATA:
1219     case STATE_COLLECTING_VAR_LEN_DATA:
1220 
1221         if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1222             qemu_log_mask(LOG_GUEST_ERROR,
1223                           "M25P80: Write overrun internal data buffer. "
1224                           "SPI controller (QEMU emulator or guest driver) "
1225                           "is misbehaving\n");
1226             s->len = s->pos = 0;
1227             s->state = STATE_IDLE;
1228             break;
1229         }
1230 
1231         s->data[s->len] = (uint8_t)tx;
1232         s->len++;
1233 
1234         if (s->len == s->needed_bytes) {
1235             complete_collecting_data(s);
1236         }
1237         break;
1238 
1239     case STATE_READING_DATA:
1240 
1241         if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1242             qemu_log_mask(LOG_GUEST_ERROR,
1243                           "M25P80: Read overrun internal data buffer. "
1244                           "SPI controller (QEMU emulator or guest driver) "
1245                           "is misbehaving\n");
1246             s->len = s->pos = 0;
1247             s->state = STATE_IDLE;
1248             break;
1249         }
1250 
1251         r = s->data[s->pos];
1252         trace_m25p80_read_data(s, s->pos, (uint8_t)r);
1253         s->pos++;
1254         if (s->pos == s->len) {
1255             s->pos = 0;
1256             if (!s->data_read_loop) {
1257                 s->state = STATE_IDLE;
1258             }
1259         }
1260         break;
1261 
1262     default:
1263     case STATE_IDLE:
1264         decode_new_cmd(s, (uint8_t)tx);
1265         break;
1266     }
1267 
1268     return r;
1269 }
1270 
1271 static void m25p80_realize(SSISlave *ss, Error **errp)
1272 {
1273     Flash *s = M25P80(ss);
1274     M25P80Class *mc = M25P80_GET_CLASS(s);
1275     int ret;
1276 
1277     s->pi = mc->pi;
1278 
1279     s->size = s->pi->sector_size * s->pi->n_sectors;
1280     s->dirty_page = -1;
1281 
1282     if (s->blk) {
1283         uint64_t perm = BLK_PERM_CONSISTENT_READ |
1284                         (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
1285         ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
1286         if (ret < 0) {
1287             return;
1288         }
1289 
1290         trace_m25p80_binding(s);
1291         s->storage = blk_blockalign(s->blk, s->size);
1292 
1293         if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1294             error_setg(errp, "failed to read the initial flash content");
1295             return;
1296         }
1297     } else {
1298         trace_m25p80_binding_no_bdrv(s);
1299         s->storage = blk_blockalign(NULL, s->size);
1300         memset(s->storage, 0xFF, s->size);
1301     }
1302 }
1303 
1304 static void m25p80_reset(DeviceState *d)
1305 {
1306     Flash *s = M25P80(d);
1307 
1308     reset_memory(s);
1309 }
1310 
1311 static int m25p80_pre_save(void *opaque)
1312 {
1313     flash_sync_dirty((Flash *)opaque, -1);
1314 
1315     return 0;
1316 }
1317 
1318 static Property m25p80_properties[] = {
1319     /* This is default value for Micron flash */
1320     DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1321     DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1322     DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1323     DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1324     DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1325     DEFINE_PROP_DRIVE("drive", Flash, blk),
1326     DEFINE_PROP_END_OF_LIST(),
1327 };
1328 
1329 static int m25p80_pre_load(void *opaque)
1330 {
1331     Flash *s = (Flash *)opaque;
1332 
1333     s->data_read_loop = false;
1334     return 0;
1335 }
1336 
1337 static bool m25p80_data_read_loop_needed(void *opaque)
1338 {
1339     Flash *s = (Flash *)opaque;
1340 
1341     return s->data_read_loop;
1342 }
1343 
1344 static const VMStateDescription vmstate_m25p80_data_read_loop = {
1345     .name = "m25p80/data_read_loop",
1346     .version_id = 1,
1347     .minimum_version_id = 1,
1348     .needed = m25p80_data_read_loop_needed,
1349     .fields = (VMStateField[]) {
1350         VMSTATE_BOOL(data_read_loop, Flash),
1351         VMSTATE_END_OF_LIST()
1352     }
1353 };
1354 
1355 static const VMStateDescription vmstate_m25p80 = {
1356     .name = "m25p80",
1357     .version_id = 0,
1358     .minimum_version_id = 0,
1359     .pre_save = m25p80_pre_save,
1360     .pre_load = m25p80_pre_load,
1361     .fields = (VMStateField[]) {
1362         VMSTATE_UINT8(state, Flash),
1363         VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1364         VMSTATE_UINT32(len, Flash),
1365         VMSTATE_UINT32(pos, Flash),
1366         VMSTATE_UINT8(needed_bytes, Flash),
1367         VMSTATE_UINT8(cmd_in_progress, Flash),
1368         VMSTATE_UINT32(cur_addr, Flash),
1369         VMSTATE_BOOL(write_enable, Flash),
1370         VMSTATE_BOOL(reset_enable, Flash),
1371         VMSTATE_UINT8(ear, Flash),
1372         VMSTATE_BOOL(four_bytes_address_mode, Flash),
1373         VMSTATE_UINT32(nonvolatile_cfg, Flash),
1374         VMSTATE_UINT32(volatile_cfg, Flash),
1375         VMSTATE_UINT32(enh_volatile_cfg, Flash),
1376         VMSTATE_BOOL(quad_enable, Flash),
1377         VMSTATE_UINT8(spansion_cr1nv, Flash),
1378         VMSTATE_UINT8(spansion_cr2nv, Flash),
1379         VMSTATE_UINT8(spansion_cr3nv, Flash),
1380         VMSTATE_UINT8(spansion_cr4nv, Flash),
1381         VMSTATE_END_OF_LIST()
1382     },
1383     .subsections = (const VMStateDescription * []) {
1384         &vmstate_m25p80_data_read_loop,
1385         NULL
1386     }
1387 };
1388 
1389 static void m25p80_class_init(ObjectClass *klass, void *data)
1390 {
1391     DeviceClass *dc = DEVICE_CLASS(klass);
1392     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
1393     M25P80Class *mc = M25P80_CLASS(klass);
1394 
1395     k->realize = m25p80_realize;
1396     k->transfer = m25p80_transfer8;
1397     k->set_cs = m25p80_cs;
1398     k->cs_polarity = SSI_CS_LOW;
1399     dc->vmsd = &vmstate_m25p80;
1400     device_class_set_props(dc, m25p80_properties);
1401     dc->reset = m25p80_reset;
1402     mc->pi = data;
1403 }
1404 
1405 static const TypeInfo m25p80_info = {
1406     .name           = TYPE_M25P80,
1407     .parent         = TYPE_SSI_SLAVE,
1408     .instance_size  = sizeof(Flash),
1409     .class_size     = sizeof(M25P80Class),
1410     .abstract       = true,
1411 };
1412 
1413 static void m25p80_register_types(void)
1414 {
1415     int i;
1416 
1417     type_register_static(&m25p80_info);
1418     for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1419         TypeInfo ti = {
1420             .name       = known_devices[i].part_name,
1421             .parent     = TYPE_M25P80,
1422             .class_init = m25p80_class_init,
1423             .class_data = (void *)&known_devices[i],
1424         };
1425         type_register(&ti);
1426     }
1427 }
1428 
1429 type_init(m25p80_register_types)
1430