1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/block/block.h" 28 #include "hw/block/flash.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/qdev-properties-system.h" 31 #include "hw/ssi/ssi.h" 32 #include "migration/vmstate.h" 33 #include "qemu/bitops.h" 34 #include "qemu/log.h" 35 #include "qemu/module.h" 36 #include "qemu/error-report.h" 37 #include "qapi/error.h" 38 #include "trace.h" 39 #include "qom/object.h" 40 #include "m25p80_sfdp.h" 41 42 /* 16 MiB max in 3 byte address mode */ 43 #define MAX_3BYTES_SIZE 0x1000000 44 #define SPI_NOR_MAX_ID_LEN 6 45 46 /* Fields for FlashPartInfo->flags */ 47 enum spi_flash_option_flags { 48 ER_4K = BIT(0), 49 ER_32K = BIT(1), 50 EEPROM = BIT(2), 51 HAS_SR_TB = BIT(3), 52 HAS_SR_BP3_BIT6 = BIT(4), 53 }; 54 55 typedef struct FlashPartInfo { 56 const char *part_name; 57 /* 58 * This array stores the ID bytes. 59 * The first three bytes are the JEDIC ID. 60 * JEDEC ID zero means "no ID" (mostly older chips). 61 */ 62 uint8_t id[SPI_NOR_MAX_ID_LEN]; 63 uint8_t id_len; 64 /* there is confusion between manufacturers as to what a sector is. In this 65 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 66 * command (opcode 0xd8). 67 */ 68 uint32_t sector_size; 69 uint32_t n_sectors; 70 uint32_t page_size; 71 uint16_t flags; 72 /* 73 * Big sized spi nor are often stacked devices, thus sometime 74 * replace chip erase with die erase. 75 * This field inform how many die is in the chip. 76 */ 77 uint8_t die_cnt; 78 uint8_t (*sfdp_read)(uint32_t sfdp_addr); 79 } FlashPartInfo; 80 81 /* adapted from linux */ 82 /* Used when the "_ext_id" is two bytes at most */ 83 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 84 .part_name = _part_name,\ 85 .id = {\ 86 ((_jedec_id) >> 16) & 0xff,\ 87 ((_jedec_id) >> 8) & 0xff,\ 88 (_jedec_id) & 0xff,\ 89 ((_ext_id) >> 8) & 0xff,\ 90 (_ext_id) & 0xff,\ 91 },\ 92 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 93 .sector_size = (_sector_size),\ 94 .n_sectors = (_n_sectors),\ 95 .page_size = 256,\ 96 .flags = (_flags),\ 97 .die_cnt = 0 98 99 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 100 .part_name = _part_name,\ 101 .id = {\ 102 ((_jedec_id) >> 16) & 0xff,\ 103 ((_jedec_id) >> 8) & 0xff,\ 104 (_jedec_id) & 0xff,\ 105 ((_ext_id) >> 16) & 0xff,\ 106 ((_ext_id) >> 8) & 0xff,\ 107 (_ext_id) & 0xff,\ 108 },\ 109 .id_len = 6,\ 110 .sector_size = (_sector_size),\ 111 .n_sectors = (_n_sectors),\ 112 .page_size = 256,\ 113 .flags = (_flags),\ 114 .die_cnt = 0 115 116 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ 117 _flags, _die_cnt)\ 118 .part_name = _part_name,\ 119 .id = {\ 120 ((_jedec_id) >> 16) & 0xff,\ 121 ((_jedec_id) >> 8) & 0xff,\ 122 (_jedec_id) & 0xff,\ 123 ((_ext_id) >> 8) & 0xff,\ 124 (_ext_id) & 0xff,\ 125 },\ 126 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 127 .sector_size = (_sector_size),\ 128 .n_sectors = (_n_sectors),\ 129 .page_size = 256,\ 130 .flags = (_flags),\ 131 .die_cnt = _die_cnt 132 133 #define JEDEC_NUMONYX 0x20 134 #define JEDEC_WINBOND 0xEF 135 #define JEDEC_SPANSION 0x01 136 137 /* Numonyx (Micron) Configuration register macros */ 138 #define VCFG_DUMMY 0x1 139 #define VCFG_WRAP_SEQUENTIAL 0x2 140 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 141 #define NVCFG_XIP_MODE_MASK (7 << 9) 142 #define VCFG_XIP_MODE_DISABLED (1 << 3) 143 #define CFG_DUMMY_CLK_LEN 4 144 #define NVCFG_DUMMY_CLK_POS 12 145 #define VCFG_DUMMY_CLK_POS 4 146 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 147 #define EVCFG_VPP_ACCELERATOR (1 << 3) 148 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 149 #define NVCFG_DUAL_IO_MASK (1 << 2) 150 #define EVCFG_DUAL_IO_DISABLED (1 << 6) 151 #define NVCFG_QUAD_IO_MASK (1 << 3) 152 #define EVCFG_QUAD_IO_DISABLED (1 << 7) 153 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 154 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 155 156 /* Numonyx (Micron) Flag Status Register macros */ 157 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 158 #define FSR_FLASH_READY (1 << 7) 159 160 /* Spansion configuration registers macros. */ 161 #define SPANSION_QUAD_CFG_POS 0 162 #define SPANSION_QUAD_CFG_LEN 1 163 #define SPANSION_DUMMY_CLK_POS 0 164 #define SPANSION_DUMMY_CLK_LEN 4 165 #define SPANSION_ADDR_LEN_POS 7 166 #define SPANSION_ADDR_LEN_LEN 1 167 168 /* 169 * Spansion read mode command length in bytes, 170 * the mode is currently not supported. 171 */ 172 173 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 174 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 175 176 static const FlashPartInfo known_devices[] = { 177 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 178 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 179 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 180 181 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 182 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 183 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 184 185 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 186 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 187 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 188 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 189 190 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 191 192 /* Atmel EEPROMS - it is assumed, that don't care bit in command 193 * is set to 0. Block protection is not supported. 194 */ 195 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 196 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 197 198 /* EON -- en25xxx */ 199 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 200 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 201 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 202 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 203 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 204 205 /* GigaDevice */ 206 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 207 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 208 209 /* Intel/Numonyx -- xxxs33b */ 210 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 211 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 212 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 213 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 214 215 /* ISSI */ 216 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, 217 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, 218 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, 219 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, 220 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, 221 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, 222 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) }, 223 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) }, 224 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) }, 225 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) }, 226 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K), 227 .sfdp_read = m25p80_sfdp_is25wp256 }, 228 229 /* Macronix */ 230 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 231 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 232 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 233 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 234 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 235 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 236 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 237 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 238 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 239 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e }, 240 { INFO6("mx25l25635f", 0xc22019, 0xc22019, 64 << 10, 512, 241 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f }, 242 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 243 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 244 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 245 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 246 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K), 247 .sfdp_read = m25p80_sfdp_mx66l1g45g }, 248 249 /* Micron */ 250 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 251 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 252 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 253 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 254 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 255 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 256 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 257 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K), 258 .sfdp_read = m25p80_sfdp_n25q256a }, 259 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, 260 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 261 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 262 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, 263 ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB), 264 .sfdp_read = m25p80_sfdp_n25q256a }, 265 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 266 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, 267 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, 268 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024, 269 ER_4K | ER_32K, 2) }, 270 { INFO_STACKED("mt35xu02gbba", 0x2c5b1c, 0x104100, 128 << 10, 2048, 271 ER_4K | ER_32K, 4), 272 .sfdp_read = m25p80_sfdp_mt35xu02g }, 273 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 274 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 275 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 276 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 277 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 278 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 279 280 /* Spansion -- single (large) sector size only, at least 281 * for the chips listed here (without boot sectors). 282 */ 283 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 284 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 285 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 286 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 287 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 288 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 289 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 290 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 291 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 292 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 293 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 294 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 295 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 296 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 297 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 298 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 299 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 300 301 /* Spansion -- boot sectors support */ 302 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 303 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 304 305 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 306 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 307 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 308 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 309 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 310 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 311 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 312 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 313 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 314 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 315 316 /* ST Microelectronics -- newer production may have feature updates */ 317 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 318 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 319 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 320 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 321 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 322 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 323 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 324 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 325 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 326 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 327 328 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 329 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 330 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 331 332 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 333 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 334 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 335 336 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 337 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 338 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 339 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 340 341 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 342 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 343 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 344 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 345 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 346 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 347 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 348 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 349 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 350 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 351 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 352 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 353 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 354 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K), 355 .sfdp_read = m25p80_sfdp_w25q256 }, 356 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K), 357 .sfdp_read = m25p80_sfdp_w25q512jv }, 358 { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K), 359 .sfdp_read = m25p80_sfdp_w25q01jvq }, 360 }; 361 362 typedef enum { 363 NOP = 0, 364 WRSR = 0x1, 365 WRDI = 0x4, 366 RDSR = 0x5, 367 WREN = 0x6, 368 BRRD = 0x16, 369 BRWR = 0x17, 370 JEDEC_READ = 0x9f, 371 BULK_ERASE_60 = 0x60, 372 BULK_ERASE = 0xc7, 373 READ_FSR = 0x70, 374 RDCR = 0x15, 375 RDSFDP = 0x5a, 376 377 READ = 0x03, 378 READ4 = 0x13, 379 FAST_READ = 0x0b, 380 FAST_READ4 = 0x0c, 381 DOR = 0x3b, 382 DOR4 = 0x3c, 383 QOR = 0x6b, 384 QOR4 = 0x6c, 385 DIOR = 0xbb, 386 DIOR4 = 0xbc, 387 QIOR = 0xeb, 388 QIOR4 = 0xec, 389 390 PP = 0x02, 391 PP4 = 0x12, 392 PP4_4 = 0x3e, 393 DPP = 0xa2, 394 QPP = 0x32, 395 QPP_4 = 0x34, 396 RDID_90 = 0x90, 397 RDID_AB = 0xab, 398 AAI_WP = 0xad, 399 400 ERASE_4K = 0x20, 401 ERASE4_4K = 0x21, 402 ERASE_32K = 0x52, 403 ERASE4_32K = 0x5c, 404 ERASE_SECTOR = 0xd8, 405 ERASE4_SECTOR = 0xdc, 406 407 EN_4BYTE_ADDR = 0xB7, 408 EX_4BYTE_ADDR = 0xE9, 409 410 EXTEND_ADDR_READ = 0xC8, 411 EXTEND_ADDR_WRITE = 0xC5, 412 413 RESET_ENABLE = 0x66, 414 RESET_MEMORY = 0x99, 415 416 /* 417 * Micron: 0x35 - enable QPI 418 * Spansion: 0x35 - read control register 419 * Winbond: 0x35 - quad enable 420 */ 421 RDCR_EQIO = 0x35, 422 RSTQIO = 0xf5, 423 424 RNVCR = 0xB5, 425 WNVCR = 0xB1, 426 427 RVCR = 0x85, 428 WVCR = 0x81, 429 430 REVCR = 0x65, 431 WEVCR = 0x61, 432 433 DIE_ERASE = 0xC4, 434 } FlashCMD; 435 436 typedef enum { 437 STATE_IDLE, 438 STATE_PAGE_PROGRAM, 439 STATE_READ, 440 STATE_COLLECTING_DATA, 441 STATE_COLLECTING_VAR_LEN_DATA, 442 STATE_READING_DATA, 443 STATE_READING_SFDP, 444 } CMDState; 445 446 typedef enum { 447 MAN_SPANSION, 448 MAN_MACRONIX, 449 MAN_NUMONYX, 450 MAN_WINBOND, 451 MAN_SST, 452 MAN_ISSI, 453 MAN_GENERIC, 454 } Manufacturer; 455 456 typedef enum { 457 MODE_STD = 0, 458 MODE_DIO = 1, 459 MODE_QIO = 2 460 } SPIMode; 461 462 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 463 464 struct Flash { 465 SSIPeripheral parent_obj; 466 467 BlockBackend *blk; 468 469 uint8_t *storage; 470 uint32_t size; 471 int page_size; 472 473 uint8_t state; 474 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 475 uint32_t len; 476 uint32_t pos; 477 bool data_read_loop; 478 uint8_t needed_bytes; 479 uint8_t cmd_in_progress; 480 uint32_t cur_addr; 481 uint32_t nonvolatile_cfg; 482 /* Configuration register for Macronix */ 483 uint32_t volatile_cfg; 484 uint32_t enh_volatile_cfg; 485 /* Spansion cfg registers. */ 486 uint8_t spansion_cr1nv; 487 uint8_t spansion_cr2nv; 488 uint8_t spansion_cr3nv; 489 uint8_t spansion_cr4nv; 490 uint8_t spansion_cr1v; 491 uint8_t spansion_cr2v; 492 uint8_t spansion_cr3v; 493 uint8_t spansion_cr4v; 494 bool wp_level; 495 bool write_enable; 496 bool four_bytes_address_mode; 497 bool reset_enable; 498 bool quad_enable; 499 bool aai_enable; 500 bool block_protect0; 501 bool block_protect1; 502 bool block_protect2; 503 bool block_protect3; 504 bool top_bottom_bit; 505 bool status_register_write_disabled; 506 uint8_t ear; 507 508 int64_t dirty_page; 509 510 const FlashPartInfo *pi; 511 512 }; 513 514 struct M25P80Class { 515 SSIPeripheralClass parent_class; 516 FlashPartInfo *pi; 517 }; 518 519 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) 520 521 static inline Manufacturer get_man(Flash *s) 522 { 523 switch (s->pi->id[0]) { 524 case 0x20: 525 return MAN_NUMONYX; 526 case 0xEF: 527 return MAN_WINBOND; 528 case 0x01: 529 return MAN_SPANSION; 530 case 0xC2: 531 return MAN_MACRONIX; 532 case 0xBF: 533 return MAN_SST; 534 case 0x9D: 535 return MAN_ISSI; 536 default: 537 return MAN_GENERIC; 538 } 539 } 540 541 static void blk_sync_complete(void *opaque, int ret) 542 { 543 QEMUIOVector *iov = opaque; 544 545 qemu_iovec_destroy(iov); 546 g_free(iov); 547 548 /* do nothing. Masters do not directly interact with the backing store, 549 * only the working copy so no mutexing required. 550 */ 551 } 552 553 static void flash_sync_page(Flash *s, int page) 554 { 555 QEMUIOVector *iov; 556 557 if (!s->blk || !blk_is_writable(s->blk)) { 558 return; 559 } 560 561 iov = g_new(QEMUIOVector, 1); 562 qemu_iovec_init(iov, 1); 563 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 564 s->pi->page_size); 565 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 566 blk_sync_complete, iov); 567 } 568 569 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 570 { 571 QEMUIOVector *iov; 572 573 if (!s->blk || !blk_is_writable(s->blk)) { 574 return; 575 } 576 577 assert(!(len % BDRV_SECTOR_SIZE)); 578 iov = g_new(QEMUIOVector, 1); 579 qemu_iovec_init(iov, 1); 580 qemu_iovec_add(iov, s->storage + off, len); 581 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 582 } 583 584 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 585 { 586 uint32_t len; 587 uint8_t capa_to_assert = 0; 588 589 switch (cmd) { 590 case ERASE_4K: 591 case ERASE4_4K: 592 len = 4 * KiB; 593 capa_to_assert = ER_4K; 594 break; 595 case ERASE_32K: 596 case ERASE4_32K: 597 len = 32 * KiB; 598 capa_to_assert = ER_32K; 599 break; 600 case ERASE_SECTOR: 601 case ERASE4_SECTOR: 602 len = s->pi->sector_size; 603 break; 604 case BULK_ERASE: 605 len = s->size; 606 break; 607 case DIE_ERASE: 608 if (s->pi->die_cnt) { 609 len = s->size / s->pi->die_cnt; 610 offset = offset & (~(len - 1)); 611 } else { 612 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" 613 " by device\n"); 614 return; 615 } 616 break; 617 default: 618 abort(); 619 } 620 621 trace_m25p80_flash_erase(s, offset, len); 622 623 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 624 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 625 " device\n", len); 626 } 627 628 if (!s->write_enable) { 629 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 630 return; 631 } 632 memset(s->storage + offset, 0xff, len); 633 flash_sync_area(s, offset, len); 634 } 635 636 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 637 { 638 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 639 flash_sync_page(s, s->dirty_page); 640 s->dirty_page = newpage; 641 } 642 } 643 644 static inline 645 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 646 { 647 uint32_t page = addr / s->pi->page_size; 648 uint8_t prev = s->storage[s->cur_addr]; 649 uint32_t block_protect_value = (s->block_protect3 << 3) | 650 (s->block_protect2 << 2) | 651 (s->block_protect1 << 1) | 652 (s->block_protect0 << 0); 653 654 if (!s->write_enable) { 655 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 656 return; 657 } 658 659 if (block_protect_value > 0) { 660 uint32_t num_protected_sectors = 1 << (block_protect_value - 1); 661 uint32_t sector = addr / s->pi->sector_size; 662 663 /* top_bottom_bit == 0 means TOP */ 664 if (!s->top_bottom_bit) { 665 if (s->pi->n_sectors <= sector + num_protected_sectors) { 666 qemu_log_mask(LOG_GUEST_ERROR, 667 "M25P80: write with write protect!\n"); 668 return; 669 } 670 } else { 671 if (sector < num_protected_sectors) { 672 qemu_log_mask(LOG_GUEST_ERROR, 673 "M25P80: write with write protect!\n"); 674 return; 675 } 676 } 677 } 678 679 if ((prev ^ data) & data) { 680 trace_m25p80_programming_zero_to_one(s, addr, prev, data); 681 } 682 683 if (s->pi->flags & EEPROM) { 684 s->storage[s->cur_addr] = data; 685 } else { 686 s->storage[s->cur_addr] &= data; 687 } 688 689 flash_sync_dirty(s, page); 690 s->dirty_page = page; 691 } 692 693 static inline int get_addr_length(Flash *s) 694 { 695 /* check if eeprom is in use */ 696 if (s->pi->flags == EEPROM) { 697 return 2; 698 } 699 700 switch (s->cmd_in_progress) { 701 case RDSFDP: 702 return 3; 703 case PP4: 704 case PP4_4: 705 case QPP_4: 706 case READ4: 707 case QIOR4: 708 case ERASE4_4K: 709 case ERASE4_32K: 710 case ERASE4_SECTOR: 711 case FAST_READ4: 712 case DOR4: 713 case QOR4: 714 case DIOR4: 715 return 4; 716 default: 717 return s->four_bytes_address_mode ? 4 : 3; 718 } 719 } 720 721 static void complete_collecting_data(Flash *s) 722 { 723 int i, n; 724 725 n = get_addr_length(s); 726 s->cur_addr = (n == 3 ? s->ear : 0); 727 for (i = 0; i < n; ++i) { 728 s->cur_addr <<= 8; 729 s->cur_addr |= s->data[i]; 730 } 731 732 s->cur_addr &= s->size - 1; 733 734 s->state = STATE_IDLE; 735 736 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, 737 s->cur_addr); 738 739 switch (s->cmd_in_progress) { 740 case DPP: 741 case QPP: 742 case QPP_4: 743 case PP: 744 case PP4: 745 case PP4_4: 746 s->state = STATE_PAGE_PROGRAM; 747 break; 748 case AAI_WP: 749 /* AAI programming starts from the even address */ 750 s->cur_addr &= ~BIT(0); 751 s->state = STATE_PAGE_PROGRAM; 752 break; 753 case READ: 754 case READ4: 755 case FAST_READ: 756 case FAST_READ4: 757 case DOR: 758 case DOR4: 759 case QOR: 760 case QOR4: 761 case DIOR: 762 case DIOR4: 763 case QIOR: 764 case QIOR4: 765 s->state = STATE_READ; 766 break; 767 case ERASE_4K: 768 case ERASE4_4K: 769 case ERASE_32K: 770 case ERASE4_32K: 771 case ERASE_SECTOR: 772 case ERASE4_SECTOR: 773 case DIE_ERASE: 774 flash_erase(s, s->cur_addr, s->cmd_in_progress); 775 break; 776 case WRSR: 777 s->status_register_write_disabled = extract32(s->data[0], 7, 1); 778 s->block_protect0 = extract32(s->data[0], 2, 1); 779 s->block_protect1 = extract32(s->data[0], 3, 1); 780 s->block_protect2 = extract32(s->data[0], 4, 1); 781 if (s->pi->flags & HAS_SR_TB) { 782 s->top_bottom_bit = extract32(s->data[0], 5, 1); 783 } 784 if (s->pi->flags & HAS_SR_BP3_BIT6) { 785 s->block_protect3 = extract32(s->data[0], 6, 1); 786 } 787 788 switch (get_man(s)) { 789 case MAN_SPANSION: 790 s->quad_enable = !!(s->data[1] & 0x02); 791 break; 792 case MAN_ISSI: 793 s->quad_enable = extract32(s->data[0], 6, 1); 794 break; 795 case MAN_MACRONIX: 796 s->quad_enable = extract32(s->data[0], 6, 1); 797 if (s->len > 1) { 798 s->volatile_cfg = s->data[1]; 799 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 800 } 801 break; 802 case MAN_WINBOND: 803 if (s->len > 1) { 804 s->quad_enable = !!(s->data[1] & 0x02); 805 } 806 break; 807 default: 808 break; 809 } 810 if (s->write_enable) { 811 s->write_enable = false; 812 } 813 break; 814 case BRWR: 815 case EXTEND_ADDR_WRITE: 816 s->ear = s->data[0]; 817 break; 818 case WNVCR: 819 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 820 break; 821 case WVCR: 822 s->volatile_cfg = s->data[0]; 823 break; 824 case WEVCR: 825 s->enh_volatile_cfg = s->data[0]; 826 break; 827 case RDID_90: 828 case RDID_AB: 829 if (get_man(s) == MAN_SST) { 830 if (s->cur_addr <= 1) { 831 if (s->cur_addr) { 832 s->data[0] = s->pi->id[2]; 833 s->data[1] = s->pi->id[0]; 834 } else { 835 s->data[0] = s->pi->id[0]; 836 s->data[1] = s->pi->id[2]; 837 } 838 s->pos = 0; 839 s->len = 2; 840 s->data_read_loop = true; 841 s->state = STATE_READING_DATA; 842 } else { 843 qemu_log_mask(LOG_GUEST_ERROR, 844 "M25P80: Invalid read id address\n"); 845 } 846 } else { 847 qemu_log_mask(LOG_GUEST_ERROR, 848 "M25P80: Read id (command 0x90/0xAB) is not supported" 849 " by device\n"); 850 } 851 break; 852 853 case RDSFDP: 854 s->state = STATE_READING_SFDP; 855 break; 856 857 default: 858 break; 859 } 860 } 861 862 static void reset_memory(Flash *s) 863 { 864 s->cmd_in_progress = NOP; 865 s->cur_addr = 0; 866 s->ear = 0; 867 s->four_bytes_address_mode = false; 868 s->len = 0; 869 s->needed_bytes = 0; 870 s->pos = 0; 871 s->state = STATE_IDLE; 872 s->write_enable = false; 873 s->reset_enable = false; 874 s->quad_enable = false; 875 s->aai_enable = false; 876 877 switch (get_man(s)) { 878 case MAN_NUMONYX: 879 s->volatile_cfg = 0; 880 s->volatile_cfg |= VCFG_DUMMY; 881 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 882 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 883 == NVCFG_XIP_MODE_DISABLED) { 884 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; 885 } 886 s->volatile_cfg |= deposit32(s->volatile_cfg, 887 VCFG_DUMMY_CLK_POS, 888 CFG_DUMMY_CLK_LEN, 889 extract32(s->nonvolatile_cfg, 890 NVCFG_DUMMY_CLK_POS, 891 CFG_DUMMY_CLK_LEN) 892 ); 893 894 s->enh_volatile_cfg = 0; 895 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; 896 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 897 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 898 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 899 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; 900 } 901 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 902 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; 903 } 904 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 905 s->four_bytes_address_mode = true; 906 } 907 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 908 s->ear = s->size / MAX_3BYTES_SIZE - 1; 909 } 910 break; 911 case MAN_MACRONIX: 912 s->volatile_cfg = 0x7; 913 break; 914 case MAN_SPANSION: 915 s->spansion_cr1v = s->spansion_cr1nv; 916 s->spansion_cr2v = s->spansion_cr2nv; 917 s->spansion_cr3v = s->spansion_cr3nv; 918 s->spansion_cr4v = s->spansion_cr4nv; 919 s->quad_enable = extract32(s->spansion_cr1v, 920 SPANSION_QUAD_CFG_POS, 921 SPANSION_QUAD_CFG_LEN 922 ); 923 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 924 SPANSION_ADDR_LEN_POS, 925 SPANSION_ADDR_LEN_LEN 926 ); 927 break; 928 default: 929 break; 930 } 931 932 trace_m25p80_reset_done(s); 933 } 934 935 static uint8_t numonyx_mode(Flash *s) 936 { 937 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { 938 return MODE_QIO; 939 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { 940 return MODE_DIO; 941 } else { 942 return MODE_STD; 943 } 944 } 945 946 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s) 947 { 948 uint8_t num_dummies; 949 uint8_t mode; 950 assert(get_man(s) == MAN_NUMONYX); 951 952 mode = numonyx_mode(s); 953 num_dummies = extract32(s->volatile_cfg, 4, 4); 954 955 if (num_dummies == 0x0 || num_dummies == 0xf) { 956 switch (s->cmd_in_progress) { 957 case QIOR: 958 case QIOR4: 959 num_dummies = 10; 960 break; 961 default: 962 num_dummies = (mode == MODE_QIO) ? 10 : 8; 963 break; 964 } 965 } 966 967 return num_dummies; 968 } 969 970 static void decode_fast_read_cmd(Flash *s) 971 { 972 s->needed_bytes = get_addr_length(s); 973 switch (get_man(s)) { 974 /* Dummy cycles - modeled with bytes writes instead of bits */ 975 case MAN_SST: 976 s->needed_bytes += 1; 977 break; 978 case MAN_WINBOND: 979 s->needed_bytes += 8; 980 break; 981 case MAN_NUMONYX: 982 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 983 break; 984 case MAN_MACRONIX: 985 if (extract32(s->volatile_cfg, 6, 2) == 1) { 986 s->needed_bytes += 6; 987 } else { 988 s->needed_bytes += 8; 989 } 990 break; 991 case MAN_SPANSION: 992 s->needed_bytes += extract32(s->spansion_cr2v, 993 SPANSION_DUMMY_CLK_POS, 994 SPANSION_DUMMY_CLK_LEN 995 ); 996 break; 997 case MAN_ISSI: 998 /* 999 * The Fast Read instruction code is followed by address bytes and 1000 * dummy cycles, transmitted via the SI line. 1001 * 1002 * The number of dummy cycles is configurable but this is currently 1003 * unmodeled, hence the default value 8 is used. 1004 * 1005 * QPI (Quad Peripheral Interface) mode has different default value 1006 * of dummy cycles, but this is unsupported at the time being. 1007 */ 1008 s->needed_bytes += 1; 1009 break; 1010 default: 1011 break; 1012 } 1013 s->pos = 0; 1014 s->len = 0; 1015 s->state = STATE_COLLECTING_DATA; 1016 } 1017 1018 static void decode_dio_read_cmd(Flash *s) 1019 { 1020 s->needed_bytes = get_addr_length(s); 1021 /* Dummy cycles modeled with bytes writes instead of bits */ 1022 switch (get_man(s)) { 1023 case MAN_WINBOND: 1024 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1025 break; 1026 case MAN_SPANSION: 1027 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1028 s->needed_bytes += extract32(s->spansion_cr2v, 1029 SPANSION_DUMMY_CLK_POS, 1030 SPANSION_DUMMY_CLK_LEN 1031 ); 1032 break; 1033 case MAN_NUMONYX: 1034 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1035 break; 1036 case MAN_MACRONIX: 1037 switch (extract32(s->volatile_cfg, 6, 2)) { 1038 case 1: 1039 s->needed_bytes += 6; 1040 break; 1041 case 2: 1042 s->needed_bytes += 8; 1043 break; 1044 default: 1045 s->needed_bytes += 4; 1046 break; 1047 } 1048 break; 1049 case MAN_ISSI: 1050 /* 1051 * The Fast Read Dual I/O instruction code is followed by address bytes 1052 * and dummy cycles, transmitted via the IO1 and IO0 line. 1053 * 1054 * The number of dummy cycles is configurable but this is currently 1055 * unmodeled, hence the default value 4 is used. 1056 */ 1057 s->needed_bytes += 1; 1058 break; 1059 default: 1060 break; 1061 } 1062 s->pos = 0; 1063 s->len = 0; 1064 s->state = STATE_COLLECTING_DATA; 1065 } 1066 1067 static void decode_qio_read_cmd(Flash *s) 1068 { 1069 s->needed_bytes = get_addr_length(s); 1070 /* Dummy cycles modeled with bytes writes instead of bits */ 1071 switch (get_man(s)) { 1072 case MAN_WINBOND: 1073 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1074 s->needed_bytes += 4; 1075 break; 1076 case MAN_SPANSION: 1077 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1078 s->needed_bytes += extract32(s->spansion_cr2v, 1079 SPANSION_DUMMY_CLK_POS, 1080 SPANSION_DUMMY_CLK_LEN 1081 ); 1082 break; 1083 case MAN_NUMONYX: 1084 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1085 break; 1086 case MAN_MACRONIX: 1087 switch (extract32(s->volatile_cfg, 6, 2)) { 1088 case 1: 1089 s->needed_bytes += 4; 1090 break; 1091 case 2: 1092 s->needed_bytes += 8; 1093 break; 1094 default: 1095 s->needed_bytes += 6; 1096 break; 1097 } 1098 break; 1099 case MAN_ISSI: 1100 /* 1101 * The Fast Read Quad I/O instruction code is followed by address bytes 1102 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line. 1103 * 1104 * The number of dummy cycles is configurable but this is currently 1105 * unmodeled, hence the default value 6 is used. 1106 * 1107 * QPI (Quad Peripheral Interface) mode has different default value 1108 * of dummy cycles, but this is unsupported at the time being. 1109 */ 1110 s->needed_bytes += 3; 1111 break; 1112 default: 1113 break; 1114 } 1115 s->pos = 0; 1116 s->len = 0; 1117 s->state = STATE_COLLECTING_DATA; 1118 } 1119 1120 static bool is_valid_aai_cmd(uint32_t cmd) 1121 { 1122 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR; 1123 } 1124 1125 static void decode_new_cmd(Flash *s, uint32_t value) 1126 { 1127 int i; 1128 1129 s->cmd_in_progress = value; 1130 trace_m25p80_command_decoded(s, value); 1131 1132 if (value != RESET_MEMORY) { 1133 s->reset_enable = false; 1134 } 1135 1136 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) { 1137 qemu_log_mask(LOG_GUEST_ERROR, 1138 "M25P80: Invalid cmd within AAI programming sequence"); 1139 } 1140 1141 switch (value) { 1142 1143 case ERASE_4K: 1144 case ERASE4_4K: 1145 case ERASE_32K: 1146 case ERASE4_32K: 1147 case ERASE_SECTOR: 1148 case ERASE4_SECTOR: 1149 case PP: 1150 case PP4: 1151 case DIE_ERASE: 1152 case RDID_90: 1153 case RDID_AB: 1154 s->needed_bytes = get_addr_length(s); 1155 s->pos = 0; 1156 s->len = 0; 1157 s->state = STATE_COLLECTING_DATA; 1158 break; 1159 case READ: 1160 case READ4: 1161 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1162 s->needed_bytes = get_addr_length(s); 1163 s->pos = 0; 1164 s->len = 0; 1165 s->state = STATE_COLLECTING_DATA; 1166 } else { 1167 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1168 "DIO or QIO mode\n", s->cmd_in_progress); 1169 } 1170 break; 1171 case DPP: 1172 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1173 s->needed_bytes = get_addr_length(s); 1174 s->pos = 0; 1175 s->len = 0; 1176 s->state = STATE_COLLECTING_DATA; 1177 } else { 1178 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1179 "QIO mode\n", s->cmd_in_progress); 1180 } 1181 break; 1182 case QPP: 1183 case QPP_4: 1184 case PP4_4: 1185 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1186 s->needed_bytes = get_addr_length(s); 1187 s->pos = 0; 1188 s->len = 0; 1189 s->state = STATE_COLLECTING_DATA; 1190 } else { 1191 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1192 "DIO mode\n", s->cmd_in_progress); 1193 } 1194 break; 1195 1196 case FAST_READ: 1197 case FAST_READ4: 1198 decode_fast_read_cmd(s); 1199 break; 1200 case DOR: 1201 case DOR4: 1202 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1203 decode_fast_read_cmd(s); 1204 } else { 1205 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1206 "QIO mode\n", s->cmd_in_progress); 1207 } 1208 break; 1209 case QOR: 1210 case QOR4: 1211 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1212 decode_fast_read_cmd(s); 1213 } else { 1214 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1215 "DIO mode\n", s->cmd_in_progress); 1216 } 1217 break; 1218 1219 case DIOR: 1220 case DIOR4: 1221 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1222 decode_dio_read_cmd(s); 1223 } else { 1224 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1225 "QIO mode\n", s->cmd_in_progress); 1226 } 1227 break; 1228 1229 case QIOR: 1230 case QIOR4: 1231 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1232 decode_qio_read_cmd(s); 1233 } else { 1234 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1235 "DIO mode\n", s->cmd_in_progress); 1236 } 1237 break; 1238 1239 case WRSR: 1240 /* 1241 * If WP# is low and status_register_write_disabled is high, 1242 * status register writes are disabled. 1243 * This is also called "hardware protected mode" (HPM). All other 1244 * combinations of the two states are called "software protected mode" 1245 * (SPM), and status register writes are permitted. 1246 */ 1247 if ((s->wp_level == 0 && s->status_register_write_disabled) 1248 || !s->write_enable) { 1249 qemu_log_mask(LOG_GUEST_ERROR, 1250 "M25P80: Status register write is disabled!\n"); 1251 break; 1252 } 1253 1254 switch (get_man(s)) { 1255 case MAN_SPANSION: 1256 s->needed_bytes = 2; 1257 s->state = STATE_COLLECTING_DATA; 1258 break; 1259 case MAN_MACRONIX: 1260 s->needed_bytes = 2; 1261 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1262 break; 1263 case MAN_WINBOND: 1264 s->needed_bytes = 2; 1265 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1266 break; 1267 default: 1268 s->needed_bytes = 1; 1269 s->state = STATE_COLLECTING_DATA; 1270 } 1271 s->pos = 0; 1272 break; 1273 1274 case WRDI: 1275 s->write_enable = false; 1276 if (get_man(s) == MAN_SST) { 1277 s->aai_enable = false; 1278 } 1279 break; 1280 case WREN: 1281 s->write_enable = true; 1282 break; 1283 1284 case RDSR: 1285 s->data[0] = (!!s->write_enable) << 1; 1286 s->data[0] |= (!!s->status_register_write_disabled) << 7; 1287 s->data[0] |= (!!s->block_protect0) << 2; 1288 s->data[0] |= (!!s->block_protect1) << 3; 1289 s->data[0] |= (!!s->block_protect2) << 4; 1290 if (s->pi->flags & HAS_SR_TB) { 1291 s->data[0] |= (!!s->top_bottom_bit) << 5; 1292 } 1293 if (s->pi->flags & HAS_SR_BP3_BIT6) { 1294 s->data[0] |= (!!s->block_protect3) << 6; 1295 } 1296 1297 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) { 1298 s->data[0] |= (!!s->quad_enable) << 6; 1299 } 1300 if (get_man(s) == MAN_SST) { 1301 s->data[0] |= (!!s->aai_enable) << 6; 1302 } 1303 1304 s->pos = 0; 1305 s->len = 1; 1306 s->data_read_loop = true; 1307 s->state = STATE_READING_DATA; 1308 break; 1309 1310 case READ_FSR: 1311 s->data[0] = FSR_FLASH_READY; 1312 if (s->four_bytes_address_mode) { 1313 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 1314 } 1315 s->pos = 0; 1316 s->len = 1; 1317 s->data_read_loop = true; 1318 s->state = STATE_READING_DATA; 1319 break; 1320 1321 case JEDEC_READ: 1322 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1323 trace_m25p80_populated_jedec(s); 1324 for (i = 0; i < s->pi->id_len; i++) { 1325 s->data[i] = s->pi->id[i]; 1326 } 1327 for (; i < SPI_NOR_MAX_ID_LEN; i++) { 1328 s->data[i] = 0; 1329 } 1330 1331 s->len = SPI_NOR_MAX_ID_LEN; 1332 s->pos = 0; 1333 s->state = STATE_READING_DATA; 1334 } else { 1335 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read " 1336 "in DIO or QIO mode\n"); 1337 } 1338 break; 1339 1340 case RDCR: 1341 s->data[0] = s->volatile_cfg & 0xFF; 1342 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 1343 s->pos = 0; 1344 s->len = 1; 1345 s->state = STATE_READING_DATA; 1346 break; 1347 1348 case BULK_ERASE_60: 1349 case BULK_ERASE: 1350 if (s->write_enable) { 1351 trace_m25p80_chip_erase(s); 1352 flash_erase(s, 0, BULK_ERASE); 1353 } else { 1354 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 1355 "protect!\n"); 1356 } 1357 break; 1358 case NOP: 1359 break; 1360 case EN_4BYTE_ADDR: 1361 s->four_bytes_address_mode = true; 1362 break; 1363 case EX_4BYTE_ADDR: 1364 s->four_bytes_address_mode = false; 1365 break; 1366 case BRRD: 1367 case EXTEND_ADDR_READ: 1368 s->data[0] = s->ear; 1369 s->pos = 0; 1370 s->len = 1; 1371 s->state = STATE_READING_DATA; 1372 break; 1373 case BRWR: 1374 case EXTEND_ADDR_WRITE: 1375 if (s->write_enable) { 1376 s->needed_bytes = 1; 1377 s->pos = 0; 1378 s->len = 0; 1379 s->state = STATE_COLLECTING_DATA; 1380 } 1381 break; 1382 case RNVCR: 1383 s->data[0] = s->nonvolatile_cfg & 0xFF; 1384 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1385 s->pos = 0; 1386 s->len = 2; 1387 s->state = STATE_READING_DATA; 1388 break; 1389 case WNVCR: 1390 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1391 s->needed_bytes = 2; 1392 s->pos = 0; 1393 s->len = 0; 1394 s->state = STATE_COLLECTING_DATA; 1395 } 1396 break; 1397 case RVCR: 1398 s->data[0] = s->volatile_cfg & 0xFF; 1399 s->pos = 0; 1400 s->len = 1; 1401 s->state = STATE_READING_DATA; 1402 break; 1403 case WVCR: 1404 if (s->write_enable) { 1405 s->needed_bytes = 1; 1406 s->pos = 0; 1407 s->len = 0; 1408 s->state = STATE_COLLECTING_DATA; 1409 } 1410 break; 1411 case REVCR: 1412 s->data[0] = s->enh_volatile_cfg & 0xFF; 1413 s->pos = 0; 1414 s->len = 1; 1415 s->state = STATE_READING_DATA; 1416 break; 1417 case WEVCR: 1418 if (s->write_enable) { 1419 s->needed_bytes = 1; 1420 s->pos = 0; 1421 s->len = 0; 1422 s->state = STATE_COLLECTING_DATA; 1423 } 1424 break; 1425 case RESET_ENABLE: 1426 s->reset_enable = true; 1427 break; 1428 case RESET_MEMORY: 1429 if (s->reset_enable) { 1430 reset_memory(s); 1431 } 1432 break; 1433 case RDCR_EQIO: 1434 switch (get_man(s)) { 1435 case MAN_SPANSION: 1436 s->data[0] = (!!s->quad_enable) << 1; 1437 s->pos = 0; 1438 s->len = 1; 1439 s->state = STATE_READING_DATA; 1440 break; 1441 case MAN_MACRONIX: 1442 s->quad_enable = true; 1443 break; 1444 case MAN_WINBOND: 1445 s->data[0] = (!!s->quad_enable) << 1; 1446 s->pos = 0; 1447 s->len = 1; 1448 s->state = STATE_READING_DATA; 1449 break; 1450 default: 1451 break; 1452 } 1453 break; 1454 case RSTQIO: 1455 s->quad_enable = false; 1456 break; 1457 case AAI_WP: 1458 if (get_man(s) == MAN_SST) { 1459 if (s->write_enable) { 1460 if (s->aai_enable) { 1461 s->state = STATE_PAGE_PROGRAM; 1462 } else { 1463 s->aai_enable = true; 1464 s->needed_bytes = get_addr_length(s); 1465 s->state = STATE_COLLECTING_DATA; 1466 } 1467 } else { 1468 qemu_log_mask(LOG_GUEST_ERROR, 1469 "M25P80: AAI_WP with write protect\n"); 1470 } 1471 } else { 1472 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1473 } 1474 break; 1475 case RDSFDP: 1476 if (s->pi->sfdp_read) { 1477 s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */ 1478 s->pos = 0; 1479 s->len = 0; 1480 s->state = STATE_COLLECTING_DATA; 1481 break; 1482 } 1483 /* Fallthrough */ 1484 1485 default: 1486 s->pos = 0; 1487 s->len = 1; 1488 s->state = STATE_READING_DATA; 1489 s->data_read_loop = true; 1490 s->data[0] = 0; 1491 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1492 break; 1493 } 1494 } 1495 1496 static int m25p80_cs(SSIPeripheral *ss, bool select) 1497 { 1498 Flash *s = M25P80(ss); 1499 1500 if (select) { 1501 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1502 complete_collecting_data(s); 1503 } 1504 s->len = 0; 1505 s->pos = 0; 1506 s->state = STATE_IDLE; 1507 flash_sync_dirty(s, -1); 1508 s->data_read_loop = false; 1509 } 1510 1511 trace_m25p80_select(s, select ? "de" : ""); 1512 1513 return 0; 1514 } 1515 1516 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) 1517 { 1518 Flash *s = M25P80(ss); 1519 uint32_t r = 0; 1520 1521 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, 1522 s->cur_addr, (uint8_t)tx); 1523 1524 switch (s->state) { 1525 1526 case STATE_PAGE_PROGRAM: 1527 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); 1528 flash_write8(s, s->cur_addr, (uint8_t)tx); 1529 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1530 1531 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) { 1532 /* 1533 * There is no wrap mode during AAI programming once the highest 1534 * unprotected memory address is reached. The Write-Enable-Latch 1535 * bit is automatically reset, and AAI programming mode aborts. 1536 */ 1537 s->write_enable = false; 1538 s->aai_enable = false; 1539 } 1540 1541 break; 1542 1543 case STATE_READ: 1544 r = s->storage[s->cur_addr]; 1545 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); 1546 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1547 break; 1548 1549 case STATE_COLLECTING_DATA: 1550 case STATE_COLLECTING_VAR_LEN_DATA: 1551 1552 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1553 qemu_log_mask(LOG_GUEST_ERROR, 1554 "M25P80: Write overrun internal data buffer. " 1555 "SPI controller (QEMU emulator or guest driver) " 1556 "is misbehaving\n"); 1557 s->len = s->pos = 0; 1558 s->state = STATE_IDLE; 1559 break; 1560 } 1561 1562 s->data[s->len] = (uint8_t)tx; 1563 s->len++; 1564 1565 if (s->len == s->needed_bytes) { 1566 complete_collecting_data(s); 1567 } 1568 break; 1569 1570 case STATE_READING_DATA: 1571 1572 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1573 qemu_log_mask(LOG_GUEST_ERROR, 1574 "M25P80: Read overrun internal data buffer. " 1575 "SPI controller (QEMU emulator or guest driver) " 1576 "is misbehaving\n"); 1577 s->len = s->pos = 0; 1578 s->state = STATE_IDLE; 1579 break; 1580 } 1581 1582 r = s->data[s->pos]; 1583 trace_m25p80_read_data(s, s->pos, (uint8_t)r); 1584 s->pos++; 1585 if (s->pos == s->len) { 1586 s->pos = 0; 1587 if (!s->data_read_loop) { 1588 s->state = STATE_IDLE; 1589 } 1590 } 1591 break; 1592 case STATE_READING_SFDP: 1593 assert(s->pi->sfdp_read); 1594 r = s->pi->sfdp_read(s->cur_addr); 1595 trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r); 1596 s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1); 1597 break; 1598 1599 default: 1600 case STATE_IDLE: 1601 decode_new_cmd(s, (uint8_t)tx); 1602 break; 1603 } 1604 1605 return r; 1606 } 1607 1608 static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level) 1609 { 1610 Flash *s = M25P80(opaque); 1611 /* WP# is just a single pin. */ 1612 assert(n == 0); 1613 s->wp_level = !!level; 1614 } 1615 1616 static void m25p80_realize(SSIPeripheral *ss, Error **errp) 1617 { 1618 Flash *s = M25P80(ss); 1619 M25P80Class *mc = M25P80_GET_CLASS(s); 1620 int ret; 1621 1622 s->pi = mc->pi; 1623 1624 s->size = s->pi->sector_size * s->pi->n_sectors; 1625 s->dirty_page = -1; 1626 1627 if (s->blk) { 1628 uint64_t perm = BLK_PERM_CONSISTENT_READ | 1629 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0); 1630 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); 1631 if (ret < 0) { 1632 return; 1633 } 1634 1635 trace_m25p80_binding(s); 1636 s->storage = blk_blockalign(s->blk, s->size); 1637 1638 if (!blk_check_size_and_read_all(s->blk, DEVICE(s), 1639 s->storage, s->size, errp)) { 1640 return; 1641 } 1642 } else { 1643 trace_m25p80_binding_no_bdrv(s); 1644 s->storage = blk_blockalign(NULL, s->size); 1645 memset(s->storage, 0xFF, s->size); 1646 } 1647 1648 qdev_init_gpio_in_named(DEVICE(s), 1649 m25p80_write_protect_pin_irq_handler, "WP#", 1); 1650 } 1651 1652 static void m25p80_reset(DeviceState *d) 1653 { 1654 Flash *s = M25P80(d); 1655 1656 s->wp_level = true; 1657 s->status_register_write_disabled = false; 1658 s->block_protect0 = false; 1659 s->block_protect1 = false; 1660 s->block_protect2 = false; 1661 s->block_protect3 = false; 1662 s->top_bottom_bit = false; 1663 1664 reset_memory(s); 1665 } 1666 1667 static int m25p80_pre_save(void *opaque) 1668 { 1669 flash_sync_dirty((Flash *)opaque, -1); 1670 1671 return 0; 1672 } 1673 1674 static Property m25p80_properties[] = { 1675 /* This is default value for Micron flash */ 1676 DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false), 1677 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1678 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1679 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1680 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1681 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1682 DEFINE_PROP_DRIVE("drive", Flash, blk), 1683 DEFINE_PROP_END_OF_LIST(), 1684 }; 1685 1686 static int m25p80_pre_load(void *opaque) 1687 { 1688 Flash *s = (Flash *)opaque; 1689 1690 s->data_read_loop = false; 1691 return 0; 1692 } 1693 1694 static bool m25p80_data_read_loop_needed(void *opaque) 1695 { 1696 Flash *s = (Flash *)opaque; 1697 1698 return s->data_read_loop; 1699 } 1700 1701 static const VMStateDescription vmstate_m25p80_data_read_loop = { 1702 .name = "m25p80/data_read_loop", 1703 .version_id = 1, 1704 .minimum_version_id = 1, 1705 .needed = m25p80_data_read_loop_needed, 1706 .fields = (const VMStateField[]) { 1707 VMSTATE_BOOL(data_read_loop, Flash), 1708 VMSTATE_END_OF_LIST() 1709 } 1710 }; 1711 1712 static bool m25p80_aai_enable_needed(void *opaque) 1713 { 1714 Flash *s = (Flash *)opaque; 1715 1716 return s->aai_enable; 1717 } 1718 1719 static const VMStateDescription vmstate_m25p80_aai_enable = { 1720 .name = "m25p80/aai_enable", 1721 .version_id = 1, 1722 .minimum_version_id = 1, 1723 .needed = m25p80_aai_enable_needed, 1724 .fields = (const VMStateField[]) { 1725 VMSTATE_BOOL(aai_enable, Flash), 1726 VMSTATE_END_OF_LIST() 1727 } 1728 }; 1729 1730 static bool m25p80_wp_level_srwd_needed(void *opaque) 1731 { 1732 Flash *s = (Flash *)opaque; 1733 1734 return !s->wp_level || s->status_register_write_disabled; 1735 } 1736 1737 static const VMStateDescription vmstate_m25p80_write_protect = { 1738 .name = "m25p80/write_protect", 1739 .version_id = 1, 1740 .minimum_version_id = 1, 1741 .needed = m25p80_wp_level_srwd_needed, 1742 .fields = (const VMStateField[]) { 1743 VMSTATE_BOOL(wp_level, Flash), 1744 VMSTATE_BOOL(status_register_write_disabled, Flash), 1745 VMSTATE_END_OF_LIST() 1746 } 1747 }; 1748 1749 static bool m25p80_block_protect_needed(void *opaque) 1750 { 1751 Flash *s = (Flash *)opaque; 1752 1753 return s->block_protect0 || 1754 s->block_protect1 || 1755 s->block_protect2 || 1756 s->block_protect3 || 1757 s->top_bottom_bit; 1758 } 1759 1760 static const VMStateDescription vmstate_m25p80_block_protect = { 1761 .name = "m25p80/block_protect", 1762 .version_id = 1, 1763 .minimum_version_id = 1, 1764 .needed = m25p80_block_protect_needed, 1765 .fields = (const VMStateField[]) { 1766 VMSTATE_BOOL(block_protect0, Flash), 1767 VMSTATE_BOOL(block_protect1, Flash), 1768 VMSTATE_BOOL(block_protect2, Flash), 1769 VMSTATE_BOOL(block_protect3, Flash), 1770 VMSTATE_BOOL(top_bottom_bit, Flash), 1771 VMSTATE_END_OF_LIST() 1772 } 1773 }; 1774 1775 static const VMStateDescription vmstate_m25p80 = { 1776 .name = "m25p80", 1777 .version_id = 0, 1778 .minimum_version_id = 0, 1779 .pre_save = m25p80_pre_save, 1780 .pre_load = m25p80_pre_load, 1781 .fields = (const VMStateField[]) { 1782 VMSTATE_UINT8(state, Flash), 1783 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1784 VMSTATE_UINT32(len, Flash), 1785 VMSTATE_UINT32(pos, Flash), 1786 VMSTATE_UINT8(needed_bytes, Flash), 1787 VMSTATE_UINT8(cmd_in_progress, Flash), 1788 VMSTATE_UINT32(cur_addr, Flash), 1789 VMSTATE_BOOL(write_enable, Flash), 1790 VMSTATE_BOOL(reset_enable, Flash), 1791 VMSTATE_UINT8(ear, Flash), 1792 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1793 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1794 VMSTATE_UINT32(volatile_cfg, Flash), 1795 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1796 VMSTATE_BOOL(quad_enable, Flash), 1797 VMSTATE_UINT8(spansion_cr1nv, Flash), 1798 VMSTATE_UINT8(spansion_cr2nv, Flash), 1799 VMSTATE_UINT8(spansion_cr3nv, Flash), 1800 VMSTATE_UINT8(spansion_cr4nv, Flash), 1801 VMSTATE_END_OF_LIST() 1802 }, 1803 .subsections = (const VMStateDescription * const []) { 1804 &vmstate_m25p80_data_read_loop, 1805 &vmstate_m25p80_aai_enable, 1806 &vmstate_m25p80_write_protect, 1807 &vmstate_m25p80_block_protect, 1808 NULL 1809 } 1810 }; 1811 1812 static void m25p80_class_init(ObjectClass *klass, void *data) 1813 { 1814 DeviceClass *dc = DEVICE_CLASS(klass); 1815 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); 1816 M25P80Class *mc = M25P80_CLASS(klass); 1817 1818 k->realize = m25p80_realize; 1819 k->transfer = m25p80_transfer8; 1820 k->set_cs = m25p80_cs; 1821 k->cs_polarity = SSI_CS_LOW; 1822 dc->vmsd = &vmstate_m25p80; 1823 device_class_set_props(dc, m25p80_properties); 1824 dc->reset = m25p80_reset; 1825 mc->pi = data; 1826 } 1827 1828 static const TypeInfo m25p80_info = { 1829 .name = TYPE_M25P80, 1830 .parent = TYPE_SSI_PERIPHERAL, 1831 .instance_size = sizeof(Flash), 1832 .class_size = sizeof(M25P80Class), 1833 .abstract = true, 1834 }; 1835 1836 static void m25p80_register_types(void) 1837 { 1838 int i; 1839 1840 type_register_static(&m25p80_info); 1841 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1842 TypeInfo ti = { 1843 .name = known_devices[i].part_name, 1844 .parent = TYPE_M25P80, 1845 .class_init = m25p80_class_init, 1846 .class_data = (void *)&known_devices[i], 1847 }; 1848 type_register(&ti); 1849 } 1850 } 1851 1852 type_init(m25p80_register_types) 1853 1854 BlockBackend *m25p80_get_blk(DeviceState *dev) 1855 { 1856 return M25P80(dev)->blk; 1857 } 1858