1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/ssi/ssi.h" 29 #include "migration/vmstate.h" 30 #include "qemu/bitops.h" 31 #include "qemu/log.h" 32 #include "qemu/module.h" 33 #include "qemu/error-report.h" 34 #include "qapi/error.h" 35 #include "trace.h" 36 #include "qom/object.h" 37 38 /* Fields for FlashPartInfo->flags */ 39 40 /* erase capabilities */ 41 #define ER_4K 1 42 #define ER_32K 2 43 /* set to allow the page program command to write 0s back to 1. Useful for 44 * modelling EEPROM with SPI flash command set 45 */ 46 #define EEPROM 0x100 47 48 /* 16 MiB max in 3 byte address mode */ 49 #define MAX_3BYTES_SIZE 0x1000000 50 51 #define SPI_NOR_MAX_ID_LEN 6 52 53 typedef struct FlashPartInfo { 54 const char *part_name; 55 /* 56 * This array stores the ID bytes. 57 * The first three bytes are the JEDIC ID. 58 * JEDEC ID zero means "no ID" (mostly older chips). 59 */ 60 uint8_t id[SPI_NOR_MAX_ID_LEN]; 61 uint8_t id_len; 62 /* there is confusion between manufacturers as to what a sector is. In this 63 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 64 * command (opcode 0xd8). 65 */ 66 uint32_t sector_size; 67 uint32_t n_sectors; 68 uint32_t page_size; 69 uint16_t flags; 70 /* 71 * Big sized spi nor are often stacked devices, thus sometime 72 * replace chip erase with die erase. 73 * This field inform how many die is in the chip. 74 */ 75 uint8_t die_cnt; 76 } FlashPartInfo; 77 78 /* adapted from linux */ 79 /* Used when the "_ext_id" is two bytes at most */ 80 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 81 .part_name = _part_name,\ 82 .id = {\ 83 ((_jedec_id) >> 16) & 0xff,\ 84 ((_jedec_id) >> 8) & 0xff,\ 85 (_jedec_id) & 0xff,\ 86 ((_ext_id) >> 8) & 0xff,\ 87 (_ext_id) & 0xff,\ 88 },\ 89 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 90 .sector_size = (_sector_size),\ 91 .n_sectors = (_n_sectors),\ 92 .page_size = 256,\ 93 .flags = (_flags),\ 94 .die_cnt = 0 95 96 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 97 .part_name = _part_name,\ 98 .id = {\ 99 ((_jedec_id) >> 16) & 0xff,\ 100 ((_jedec_id) >> 8) & 0xff,\ 101 (_jedec_id) & 0xff,\ 102 ((_ext_id) >> 16) & 0xff,\ 103 ((_ext_id) >> 8) & 0xff,\ 104 (_ext_id) & 0xff,\ 105 },\ 106 .id_len = 6,\ 107 .sector_size = (_sector_size),\ 108 .n_sectors = (_n_sectors),\ 109 .page_size = 256,\ 110 .flags = (_flags),\ 111 .die_cnt = 0 112 113 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ 114 _flags, _die_cnt)\ 115 .part_name = _part_name,\ 116 .id = {\ 117 ((_jedec_id) >> 16) & 0xff,\ 118 ((_jedec_id) >> 8) & 0xff,\ 119 (_jedec_id) & 0xff,\ 120 ((_ext_id) >> 8) & 0xff,\ 121 (_ext_id) & 0xff,\ 122 },\ 123 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 124 .sector_size = (_sector_size),\ 125 .n_sectors = (_n_sectors),\ 126 .page_size = 256,\ 127 .flags = (_flags),\ 128 .die_cnt = _die_cnt 129 130 #define JEDEC_NUMONYX 0x20 131 #define JEDEC_WINBOND 0xEF 132 #define JEDEC_SPANSION 0x01 133 134 /* Numonyx (Micron) Configuration register macros */ 135 #define VCFG_DUMMY 0x1 136 #define VCFG_WRAP_SEQUENTIAL 0x2 137 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 138 #define NVCFG_XIP_MODE_MASK (7 << 9) 139 #define VCFG_XIP_MODE_ENABLED (1 << 3) 140 #define CFG_DUMMY_CLK_LEN 4 141 #define NVCFG_DUMMY_CLK_POS 12 142 #define VCFG_DUMMY_CLK_POS 4 143 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 144 #define EVCFG_VPP_ACCELERATOR (1 << 3) 145 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 146 #define NVCFG_DUAL_IO_MASK (1 << 2) 147 #define EVCFG_DUAL_IO_ENABLED (1 << 6) 148 #define NVCFG_QUAD_IO_MASK (1 << 3) 149 #define EVCFG_QUAD_IO_ENABLED (1 << 7) 150 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 151 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 152 153 /* Numonyx (Micron) Flag Status Register macros */ 154 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 155 #define FSR_FLASH_READY (1 << 7) 156 157 /* Spansion configuration registers macros. */ 158 #define SPANSION_QUAD_CFG_POS 0 159 #define SPANSION_QUAD_CFG_LEN 1 160 #define SPANSION_DUMMY_CLK_POS 0 161 #define SPANSION_DUMMY_CLK_LEN 4 162 #define SPANSION_ADDR_LEN_POS 7 163 #define SPANSION_ADDR_LEN_LEN 1 164 165 /* 166 * Spansion read mode command length in bytes, 167 * the mode is currently not supported. 168 */ 169 170 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 171 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 172 173 static const FlashPartInfo known_devices[] = { 174 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 175 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 176 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 177 178 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 179 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 180 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 181 182 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 183 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 184 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 185 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 186 187 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 188 189 /* Atmel EEPROMS - it is assumed, that don't care bit in command 190 * is set to 0. Block protection is not supported. 191 */ 192 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 193 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 194 195 /* EON -- en25xxx */ 196 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 197 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 198 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 199 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 200 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 201 202 /* GigaDevice */ 203 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 204 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 205 206 /* Intel/Numonyx -- xxxs33b */ 207 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 208 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 209 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 210 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 211 212 /* Macronix */ 213 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 214 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 215 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 216 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 217 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 218 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 219 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 220 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 221 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) }, 222 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 223 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 224 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 225 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 226 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 227 228 /* Micron */ 229 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 230 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 231 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 232 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 233 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 234 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 235 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 236 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 237 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, 238 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 239 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 240 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 241 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 242 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, 243 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, 244 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 245 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 246 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 247 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 248 249 /* Spansion -- single (large) sector size only, at least 250 * for the chips listed here (without boot sectors). 251 */ 252 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 253 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 254 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 255 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 256 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 257 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 258 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 259 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 260 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 261 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 262 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 263 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 264 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 265 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 266 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 267 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 268 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 269 270 /* Spansion -- boot sectors support */ 271 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 272 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 273 274 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 275 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 276 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 277 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 278 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 279 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 280 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 281 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 282 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 283 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 284 285 /* ST Microelectronics -- newer production may have feature updates */ 286 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 287 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 288 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 289 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 290 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 291 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 292 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 293 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 294 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 295 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 296 297 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 298 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 299 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 300 301 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 302 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 303 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 304 305 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 306 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 307 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 308 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 309 310 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 311 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 312 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 313 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 314 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 315 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 316 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 317 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 318 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 319 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 320 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 321 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 322 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 323 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, 324 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) }, 325 }; 326 327 typedef enum { 328 NOP = 0, 329 WRSR = 0x1, 330 WRDI = 0x4, 331 RDSR = 0x5, 332 WREN = 0x6, 333 BRRD = 0x16, 334 BRWR = 0x17, 335 JEDEC_READ = 0x9f, 336 BULK_ERASE_60 = 0x60, 337 BULK_ERASE = 0xc7, 338 READ_FSR = 0x70, 339 RDCR = 0x15, 340 341 READ = 0x03, 342 READ4 = 0x13, 343 FAST_READ = 0x0b, 344 FAST_READ4 = 0x0c, 345 DOR = 0x3b, 346 DOR4 = 0x3c, 347 QOR = 0x6b, 348 QOR4 = 0x6c, 349 DIOR = 0xbb, 350 DIOR4 = 0xbc, 351 QIOR = 0xeb, 352 QIOR4 = 0xec, 353 354 PP = 0x02, 355 PP4 = 0x12, 356 PP4_4 = 0x3e, 357 DPP = 0xa2, 358 QPP = 0x32, 359 QPP_4 = 0x34, 360 RDID_90 = 0x90, 361 RDID_AB = 0xab, 362 363 ERASE_4K = 0x20, 364 ERASE4_4K = 0x21, 365 ERASE_32K = 0x52, 366 ERASE4_32K = 0x5c, 367 ERASE_SECTOR = 0xd8, 368 ERASE4_SECTOR = 0xdc, 369 370 EN_4BYTE_ADDR = 0xB7, 371 EX_4BYTE_ADDR = 0xE9, 372 373 EXTEND_ADDR_READ = 0xC8, 374 EXTEND_ADDR_WRITE = 0xC5, 375 376 RESET_ENABLE = 0x66, 377 RESET_MEMORY = 0x99, 378 379 /* 380 * Micron: 0x35 - enable QPI 381 * Spansion: 0x35 - read control register 382 */ 383 RDCR_EQIO = 0x35, 384 RSTQIO = 0xf5, 385 386 RNVCR = 0xB5, 387 WNVCR = 0xB1, 388 389 RVCR = 0x85, 390 WVCR = 0x81, 391 392 REVCR = 0x65, 393 WEVCR = 0x61, 394 395 DIE_ERASE = 0xC4, 396 } FlashCMD; 397 398 typedef enum { 399 STATE_IDLE, 400 STATE_PAGE_PROGRAM, 401 STATE_READ, 402 STATE_COLLECTING_DATA, 403 STATE_COLLECTING_VAR_LEN_DATA, 404 STATE_READING_DATA, 405 } CMDState; 406 407 typedef enum { 408 MAN_SPANSION, 409 MAN_MACRONIX, 410 MAN_NUMONYX, 411 MAN_WINBOND, 412 MAN_SST, 413 MAN_GENERIC, 414 } Manufacturer; 415 416 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 417 418 struct Flash { 419 SSIPeripheral parent_obj; 420 421 BlockBackend *blk; 422 423 uint8_t *storage; 424 uint32_t size; 425 int page_size; 426 427 uint8_t state; 428 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 429 uint32_t len; 430 uint32_t pos; 431 bool data_read_loop; 432 uint8_t needed_bytes; 433 uint8_t cmd_in_progress; 434 uint32_t cur_addr; 435 uint32_t nonvolatile_cfg; 436 /* Configuration register for Macronix */ 437 uint32_t volatile_cfg; 438 uint32_t enh_volatile_cfg; 439 /* Spansion cfg registers. */ 440 uint8_t spansion_cr1nv; 441 uint8_t spansion_cr2nv; 442 uint8_t spansion_cr3nv; 443 uint8_t spansion_cr4nv; 444 uint8_t spansion_cr1v; 445 uint8_t spansion_cr2v; 446 uint8_t spansion_cr3v; 447 uint8_t spansion_cr4v; 448 bool write_enable; 449 bool four_bytes_address_mode; 450 bool reset_enable; 451 bool quad_enable; 452 uint8_t ear; 453 454 int64_t dirty_page; 455 456 const FlashPartInfo *pi; 457 458 }; 459 460 struct M25P80Class { 461 SSIPeripheralClass parent_class; 462 FlashPartInfo *pi; 463 }; 464 465 #define TYPE_M25P80 "m25p80-generic" 466 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) 467 468 static inline Manufacturer get_man(Flash *s) 469 { 470 switch (s->pi->id[0]) { 471 case 0x20: 472 return MAN_NUMONYX; 473 case 0xEF: 474 return MAN_WINBOND; 475 case 0x01: 476 return MAN_SPANSION; 477 case 0xC2: 478 return MAN_MACRONIX; 479 case 0xBF: 480 return MAN_SST; 481 default: 482 return MAN_GENERIC; 483 } 484 } 485 486 static void blk_sync_complete(void *opaque, int ret) 487 { 488 QEMUIOVector *iov = opaque; 489 490 qemu_iovec_destroy(iov); 491 g_free(iov); 492 493 /* do nothing. Masters do not directly interact with the backing store, 494 * only the working copy so no mutexing required. 495 */ 496 } 497 498 static void flash_sync_page(Flash *s, int page) 499 { 500 QEMUIOVector *iov; 501 502 if (!s->blk || blk_is_read_only(s->blk)) { 503 return; 504 } 505 506 iov = g_new(QEMUIOVector, 1); 507 qemu_iovec_init(iov, 1); 508 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 509 s->pi->page_size); 510 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 511 blk_sync_complete, iov); 512 } 513 514 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 515 { 516 QEMUIOVector *iov; 517 518 if (!s->blk || blk_is_read_only(s->blk)) { 519 return; 520 } 521 522 assert(!(len % BDRV_SECTOR_SIZE)); 523 iov = g_new(QEMUIOVector, 1); 524 qemu_iovec_init(iov, 1); 525 qemu_iovec_add(iov, s->storage + off, len); 526 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 527 } 528 529 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 530 { 531 uint32_t len; 532 uint8_t capa_to_assert = 0; 533 534 switch (cmd) { 535 case ERASE_4K: 536 case ERASE4_4K: 537 len = 4 * KiB; 538 capa_to_assert = ER_4K; 539 break; 540 case ERASE_32K: 541 case ERASE4_32K: 542 len = 32 * KiB; 543 capa_to_assert = ER_32K; 544 break; 545 case ERASE_SECTOR: 546 case ERASE4_SECTOR: 547 len = s->pi->sector_size; 548 break; 549 case BULK_ERASE: 550 len = s->size; 551 break; 552 case DIE_ERASE: 553 if (s->pi->die_cnt) { 554 len = s->size / s->pi->die_cnt; 555 offset = offset & (~(len - 1)); 556 } else { 557 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" 558 " by device\n"); 559 return; 560 } 561 break; 562 default: 563 abort(); 564 } 565 566 trace_m25p80_flash_erase(s, offset, len); 567 568 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 569 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 570 " device\n", len); 571 } 572 573 if (!s->write_enable) { 574 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 575 return; 576 } 577 memset(s->storage + offset, 0xff, len); 578 flash_sync_area(s, offset, len); 579 } 580 581 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 582 { 583 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 584 flash_sync_page(s, s->dirty_page); 585 s->dirty_page = newpage; 586 } 587 } 588 589 static inline 590 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 591 { 592 uint32_t page = addr / s->pi->page_size; 593 uint8_t prev = s->storage[s->cur_addr]; 594 595 if (!s->write_enable) { 596 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 597 } 598 599 if ((prev ^ data) & data) { 600 trace_m25p80_programming_zero_to_one(s, addr, prev, data); 601 } 602 603 if (s->pi->flags & EEPROM) { 604 s->storage[s->cur_addr] = data; 605 } else { 606 s->storage[s->cur_addr] &= data; 607 } 608 609 flash_sync_dirty(s, page); 610 s->dirty_page = page; 611 } 612 613 static inline int get_addr_length(Flash *s) 614 { 615 /* check if eeprom is in use */ 616 if (s->pi->flags == EEPROM) { 617 return 2; 618 } 619 620 switch (s->cmd_in_progress) { 621 case PP4: 622 case PP4_4: 623 case QPP_4: 624 case READ4: 625 case QIOR4: 626 case ERASE4_4K: 627 case ERASE4_32K: 628 case ERASE4_SECTOR: 629 case FAST_READ4: 630 case DOR4: 631 case QOR4: 632 case DIOR4: 633 return 4; 634 default: 635 return s->four_bytes_address_mode ? 4 : 3; 636 } 637 } 638 639 static void complete_collecting_data(Flash *s) 640 { 641 int i, n; 642 643 n = get_addr_length(s); 644 s->cur_addr = (n == 3 ? s->ear : 0); 645 for (i = 0; i < n; ++i) { 646 s->cur_addr <<= 8; 647 s->cur_addr |= s->data[i]; 648 } 649 650 s->cur_addr &= s->size - 1; 651 652 s->state = STATE_IDLE; 653 654 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, 655 s->cur_addr); 656 657 switch (s->cmd_in_progress) { 658 case DPP: 659 case QPP: 660 case QPP_4: 661 case PP: 662 case PP4: 663 case PP4_4: 664 s->state = STATE_PAGE_PROGRAM; 665 break; 666 case READ: 667 case READ4: 668 case FAST_READ: 669 case FAST_READ4: 670 case DOR: 671 case DOR4: 672 case QOR: 673 case QOR4: 674 case DIOR: 675 case DIOR4: 676 case QIOR: 677 case QIOR4: 678 s->state = STATE_READ; 679 break; 680 case ERASE_4K: 681 case ERASE4_4K: 682 case ERASE_32K: 683 case ERASE4_32K: 684 case ERASE_SECTOR: 685 case ERASE4_SECTOR: 686 case DIE_ERASE: 687 flash_erase(s, s->cur_addr, s->cmd_in_progress); 688 break; 689 case WRSR: 690 switch (get_man(s)) { 691 case MAN_SPANSION: 692 s->quad_enable = !!(s->data[1] & 0x02); 693 break; 694 case MAN_MACRONIX: 695 s->quad_enable = extract32(s->data[0], 6, 1); 696 if (s->len > 1) { 697 s->volatile_cfg = s->data[1]; 698 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 699 } 700 break; 701 default: 702 break; 703 } 704 if (s->write_enable) { 705 s->write_enable = false; 706 } 707 break; 708 case BRWR: 709 case EXTEND_ADDR_WRITE: 710 s->ear = s->data[0]; 711 break; 712 case WNVCR: 713 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 714 break; 715 case WVCR: 716 s->volatile_cfg = s->data[0]; 717 break; 718 case WEVCR: 719 s->enh_volatile_cfg = s->data[0]; 720 break; 721 case RDID_90: 722 case RDID_AB: 723 if (get_man(s) == MAN_SST) { 724 if (s->cur_addr <= 1) { 725 if (s->cur_addr) { 726 s->data[0] = s->pi->id[2]; 727 s->data[1] = s->pi->id[0]; 728 } else { 729 s->data[0] = s->pi->id[0]; 730 s->data[1] = s->pi->id[2]; 731 } 732 s->pos = 0; 733 s->len = 2; 734 s->data_read_loop = true; 735 s->state = STATE_READING_DATA; 736 } else { 737 qemu_log_mask(LOG_GUEST_ERROR, 738 "M25P80: Invalid read id address\n"); 739 } 740 } else { 741 qemu_log_mask(LOG_GUEST_ERROR, 742 "M25P80: Read id (command 0x90/0xAB) is not supported" 743 " by device\n"); 744 } 745 break; 746 default: 747 break; 748 } 749 } 750 751 static void reset_memory(Flash *s) 752 { 753 s->cmd_in_progress = NOP; 754 s->cur_addr = 0; 755 s->ear = 0; 756 s->four_bytes_address_mode = false; 757 s->len = 0; 758 s->needed_bytes = 0; 759 s->pos = 0; 760 s->state = STATE_IDLE; 761 s->write_enable = false; 762 s->reset_enable = false; 763 s->quad_enable = false; 764 765 switch (get_man(s)) { 766 case MAN_NUMONYX: 767 s->volatile_cfg = 0; 768 s->volatile_cfg |= VCFG_DUMMY; 769 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 770 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 771 != NVCFG_XIP_MODE_DISABLED) { 772 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED; 773 } 774 s->volatile_cfg |= deposit32(s->volatile_cfg, 775 VCFG_DUMMY_CLK_POS, 776 CFG_DUMMY_CLK_LEN, 777 extract32(s->nonvolatile_cfg, 778 NVCFG_DUMMY_CLK_POS, 779 CFG_DUMMY_CLK_LEN) 780 ); 781 782 s->enh_volatile_cfg = 0; 783 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; 784 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 785 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 786 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 787 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; 788 } 789 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 790 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; 791 } 792 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 793 s->four_bytes_address_mode = true; 794 } 795 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 796 s->ear = s->size / MAX_3BYTES_SIZE - 1; 797 } 798 break; 799 case MAN_MACRONIX: 800 s->volatile_cfg = 0x7; 801 break; 802 case MAN_SPANSION: 803 s->spansion_cr1v = s->spansion_cr1nv; 804 s->spansion_cr2v = s->spansion_cr2nv; 805 s->spansion_cr3v = s->spansion_cr3nv; 806 s->spansion_cr4v = s->spansion_cr4nv; 807 s->quad_enable = extract32(s->spansion_cr1v, 808 SPANSION_QUAD_CFG_POS, 809 SPANSION_QUAD_CFG_LEN 810 ); 811 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 812 SPANSION_ADDR_LEN_POS, 813 SPANSION_ADDR_LEN_LEN 814 ); 815 break; 816 default: 817 break; 818 } 819 820 trace_m25p80_reset_done(s); 821 } 822 823 static void decode_fast_read_cmd(Flash *s) 824 { 825 s->needed_bytes = get_addr_length(s); 826 switch (get_man(s)) { 827 /* Dummy cycles - modeled with bytes writes instead of bits */ 828 case MAN_WINBOND: 829 s->needed_bytes += 8; 830 break; 831 case MAN_NUMONYX: 832 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 833 break; 834 case MAN_MACRONIX: 835 if (extract32(s->volatile_cfg, 6, 2) == 1) { 836 s->needed_bytes += 6; 837 } else { 838 s->needed_bytes += 8; 839 } 840 break; 841 case MAN_SPANSION: 842 s->needed_bytes += extract32(s->spansion_cr2v, 843 SPANSION_DUMMY_CLK_POS, 844 SPANSION_DUMMY_CLK_LEN 845 ); 846 break; 847 default: 848 break; 849 } 850 s->pos = 0; 851 s->len = 0; 852 s->state = STATE_COLLECTING_DATA; 853 } 854 855 static void decode_dio_read_cmd(Flash *s) 856 { 857 s->needed_bytes = get_addr_length(s); 858 /* Dummy cycles modeled with bytes writes instead of bits */ 859 switch (get_man(s)) { 860 case MAN_WINBOND: 861 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 862 break; 863 case MAN_SPANSION: 864 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 865 s->needed_bytes += extract32(s->spansion_cr2v, 866 SPANSION_DUMMY_CLK_POS, 867 SPANSION_DUMMY_CLK_LEN 868 ); 869 break; 870 case MAN_NUMONYX: 871 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 872 break; 873 case MAN_MACRONIX: 874 switch (extract32(s->volatile_cfg, 6, 2)) { 875 case 1: 876 s->needed_bytes += 6; 877 break; 878 case 2: 879 s->needed_bytes += 8; 880 break; 881 default: 882 s->needed_bytes += 4; 883 break; 884 } 885 break; 886 default: 887 break; 888 } 889 s->pos = 0; 890 s->len = 0; 891 s->state = STATE_COLLECTING_DATA; 892 } 893 894 static void decode_qio_read_cmd(Flash *s) 895 { 896 s->needed_bytes = get_addr_length(s); 897 /* Dummy cycles modeled with bytes writes instead of bits */ 898 switch (get_man(s)) { 899 case MAN_WINBOND: 900 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 901 s->needed_bytes += 4; 902 break; 903 case MAN_SPANSION: 904 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 905 s->needed_bytes += extract32(s->spansion_cr2v, 906 SPANSION_DUMMY_CLK_POS, 907 SPANSION_DUMMY_CLK_LEN 908 ); 909 break; 910 case MAN_NUMONYX: 911 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 912 break; 913 case MAN_MACRONIX: 914 switch (extract32(s->volatile_cfg, 6, 2)) { 915 case 1: 916 s->needed_bytes += 4; 917 break; 918 case 2: 919 s->needed_bytes += 8; 920 break; 921 default: 922 s->needed_bytes += 6; 923 break; 924 } 925 break; 926 default: 927 break; 928 } 929 s->pos = 0; 930 s->len = 0; 931 s->state = STATE_COLLECTING_DATA; 932 } 933 934 static void decode_new_cmd(Flash *s, uint32_t value) 935 { 936 int i; 937 938 s->cmd_in_progress = value; 939 trace_m25p80_command_decoded(s, value); 940 941 if (value != RESET_MEMORY) { 942 s->reset_enable = false; 943 } 944 945 switch (value) { 946 947 case ERASE_4K: 948 case ERASE4_4K: 949 case ERASE_32K: 950 case ERASE4_32K: 951 case ERASE_SECTOR: 952 case ERASE4_SECTOR: 953 case READ: 954 case READ4: 955 case DPP: 956 case QPP: 957 case QPP_4: 958 case PP: 959 case PP4: 960 case PP4_4: 961 case DIE_ERASE: 962 case RDID_90: 963 case RDID_AB: 964 s->needed_bytes = get_addr_length(s); 965 s->pos = 0; 966 s->len = 0; 967 s->state = STATE_COLLECTING_DATA; 968 break; 969 970 case FAST_READ: 971 case FAST_READ4: 972 case DOR: 973 case DOR4: 974 case QOR: 975 case QOR4: 976 decode_fast_read_cmd(s); 977 break; 978 979 case DIOR: 980 case DIOR4: 981 decode_dio_read_cmd(s); 982 break; 983 984 case QIOR: 985 case QIOR4: 986 decode_qio_read_cmd(s); 987 break; 988 989 case WRSR: 990 if (s->write_enable) { 991 switch (get_man(s)) { 992 case MAN_SPANSION: 993 s->needed_bytes = 2; 994 s->state = STATE_COLLECTING_DATA; 995 break; 996 case MAN_MACRONIX: 997 s->needed_bytes = 2; 998 s->state = STATE_COLLECTING_VAR_LEN_DATA; 999 break; 1000 default: 1001 s->needed_bytes = 1; 1002 s->state = STATE_COLLECTING_DATA; 1003 } 1004 s->pos = 0; 1005 } 1006 break; 1007 1008 case WRDI: 1009 s->write_enable = false; 1010 break; 1011 case WREN: 1012 s->write_enable = true; 1013 break; 1014 1015 case RDSR: 1016 s->data[0] = (!!s->write_enable) << 1; 1017 if (get_man(s) == MAN_MACRONIX) { 1018 s->data[0] |= (!!s->quad_enable) << 6; 1019 } 1020 s->pos = 0; 1021 s->len = 1; 1022 s->data_read_loop = true; 1023 s->state = STATE_READING_DATA; 1024 break; 1025 1026 case READ_FSR: 1027 s->data[0] = FSR_FLASH_READY; 1028 if (s->four_bytes_address_mode) { 1029 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 1030 } 1031 s->pos = 0; 1032 s->len = 1; 1033 s->data_read_loop = true; 1034 s->state = STATE_READING_DATA; 1035 break; 1036 1037 case JEDEC_READ: 1038 trace_m25p80_populated_jedec(s); 1039 for (i = 0; i < s->pi->id_len; i++) { 1040 s->data[i] = s->pi->id[i]; 1041 } 1042 for (; i < SPI_NOR_MAX_ID_LEN; i++) { 1043 s->data[i] = 0; 1044 } 1045 1046 s->len = SPI_NOR_MAX_ID_LEN; 1047 s->pos = 0; 1048 s->state = STATE_READING_DATA; 1049 break; 1050 1051 case RDCR: 1052 s->data[0] = s->volatile_cfg & 0xFF; 1053 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 1054 s->pos = 0; 1055 s->len = 1; 1056 s->state = STATE_READING_DATA; 1057 break; 1058 1059 case BULK_ERASE_60: 1060 case BULK_ERASE: 1061 if (s->write_enable) { 1062 trace_m25p80_chip_erase(s); 1063 flash_erase(s, 0, BULK_ERASE); 1064 } else { 1065 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 1066 "protect!\n"); 1067 } 1068 break; 1069 case NOP: 1070 break; 1071 case EN_4BYTE_ADDR: 1072 s->four_bytes_address_mode = true; 1073 break; 1074 case EX_4BYTE_ADDR: 1075 s->four_bytes_address_mode = false; 1076 break; 1077 case BRRD: 1078 case EXTEND_ADDR_READ: 1079 s->data[0] = s->ear; 1080 s->pos = 0; 1081 s->len = 1; 1082 s->state = STATE_READING_DATA; 1083 break; 1084 case BRWR: 1085 case EXTEND_ADDR_WRITE: 1086 if (s->write_enable) { 1087 s->needed_bytes = 1; 1088 s->pos = 0; 1089 s->len = 0; 1090 s->state = STATE_COLLECTING_DATA; 1091 } 1092 break; 1093 case RNVCR: 1094 s->data[0] = s->nonvolatile_cfg & 0xFF; 1095 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1096 s->pos = 0; 1097 s->len = 2; 1098 s->state = STATE_READING_DATA; 1099 break; 1100 case WNVCR: 1101 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1102 s->needed_bytes = 2; 1103 s->pos = 0; 1104 s->len = 0; 1105 s->state = STATE_COLLECTING_DATA; 1106 } 1107 break; 1108 case RVCR: 1109 s->data[0] = s->volatile_cfg & 0xFF; 1110 s->pos = 0; 1111 s->len = 1; 1112 s->state = STATE_READING_DATA; 1113 break; 1114 case WVCR: 1115 if (s->write_enable) { 1116 s->needed_bytes = 1; 1117 s->pos = 0; 1118 s->len = 0; 1119 s->state = STATE_COLLECTING_DATA; 1120 } 1121 break; 1122 case REVCR: 1123 s->data[0] = s->enh_volatile_cfg & 0xFF; 1124 s->pos = 0; 1125 s->len = 1; 1126 s->state = STATE_READING_DATA; 1127 break; 1128 case WEVCR: 1129 if (s->write_enable) { 1130 s->needed_bytes = 1; 1131 s->pos = 0; 1132 s->len = 0; 1133 s->state = STATE_COLLECTING_DATA; 1134 } 1135 break; 1136 case RESET_ENABLE: 1137 s->reset_enable = true; 1138 break; 1139 case RESET_MEMORY: 1140 if (s->reset_enable) { 1141 reset_memory(s); 1142 } 1143 break; 1144 case RDCR_EQIO: 1145 switch (get_man(s)) { 1146 case MAN_SPANSION: 1147 s->data[0] = (!!s->quad_enable) << 1; 1148 s->pos = 0; 1149 s->len = 1; 1150 s->state = STATE_READING_DATA; 1151 break; 1152 case MAN_MACRONIX: 1153 s->quad_enable = true; 1154 break; 1155 default: 1156 break; 1157 } 1158 break; 1159 case RSTQIO: 1160 s->quad_enable = false; 1161 break; 1162 default: 1163 s->pos = 0; 1164 s->len = 1; 1165 s->state = STATE_READING_DATA; 1166 s->data_read_loop = true; 1167 s->data[0] = 0; 1168 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1169 break; 1170 } 1171 } 1172 1173 static int m25p80_cs(SSIPeripheral *ss, bool select) 1174 { 1175 Flash *s = M25P80(ss); 1176 1177 if (select) { 1178 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1179 complete_collecting_data(s); 1180 } 1181 s->len = 0; 1182 s->pos = 0; 1183 s->state = STATE_IDLE; 1184 flash_sync_dirty(s, -1); 1185 s->data_read_loop = false; 1186 } 1187 1188 trace_m25p80_select(s, select ? "de" : ""); 1189 1190 return 0; 1191 } 1192 1193 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) 1194 { 1195 Flash *s = M25P80(ss); 1196 uint32_t r = 0; 1197 1198 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, 1199 s->cur_addr, (uint8_t)tx); 1200 1201 switch (s->state) { 1202 1203 case STATE_PAGE_PROGRAM: 1204 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); 1205 flash_write8(s, s->cur_addr, (uint8_t)tx); 1206 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1207 break; 1208 1209 case STATE_READ: 1210 r = s->storage[s->cur_addr]; 1211 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); 1212 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1213 break; 1214 1215 case STATE_COLLECTING_DATA: 1216 case STATE_COLLECTING_VAR_LEN_DATA: 1217 1218 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1219 qemu_log_mask(LOG_GUEST_ERROR, 1220 "M25P80: Write overrun internal data buffer. " 1221 "SPI controller (QEMU emulator or guest driver) " 1222 "is misbehaving\n"); 1223 s->len = s->pos = 0; 1224 s->state = STATE_IDLE; 1225 break; 1226 } 1227 1228 s->data[s->len] = (uint8_t)tx; 1229 s->len++; 1230 1231 if (s->len == s->needed_bytes) { 1232 complete_collecting_data(s); 1233 } 1234 break; 1235 1236 case STATE_READING_DATA: 1237 1238 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1239 qemu_log_mask(LOG_GUEST_ERROR, 1240 "M25P80: Read overrun internal data buffer. " 1241 "SPI controller (QEMU emulator or guest driver) " 1242 "is misbehaving\n"); 1243 s->len = s->pos = 0; 1244 s->state = STATE_IDLE; 1245 break; 1246 } 1247 1248 r = s->data[s->pos]; 1249 trace_m25p80_read_data(s, s->pos, (uint8_t)r); 1250 s->pos++; 1251 if (s->pos == s->len) { 1252 s->pos = 0; 1253 if (!s->data_read_loop) { 1254 s->state = STATE_IDLE; 1255 } 1256 } 1257 break; 1258 1259 default: 1260 case STATE_IDLE: 1261 decode_new_cmd(s, (uint8_t)tx); 1262 break; 1263 } 1264 1265 return r; 1266 } 1267 1268 static void m25p80_realize(SSIPeripheral *ss, Error **errp) 1269 { 1270 Flash *s = M25P80(ss); 1271 M25P80Class *mc = M25P80_GET_CLASS(s); 1272 int ret; 1273 1274 s->pi = mc->pi; 1275 1276 s->size = s->pi->sector_size * s->pi->n_sectors; 1277 s->dirty_page = -1; 1278 1279 if (s->blk) { 1280 uint64_t perm = BLK_PERM_CONSISTENT_READ | 1281 (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE); 1282 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); 1283 if (ret < 0) { 1284 return; 1285 } 1286 1287 trace_m25p80_binding(s); 1288 s->storage = blk_blockalign(s->blk, s->size); 1289 1290 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) { 1291 error_setg(errp, "failed to read the initial flash content"); 1292 return; 1293 } 1294 } else { 1295 trace_m25p80_binding_no_bdrv(s); 1296 s->storage = blk_blockalign(NULL, s->size); 1297 memset(s->storage, 0xFF, s->size); 1298 } 1299 } 1300 1301 static void m25p80_reset(DeviceState *d) 1302 { 1303 Flash *s = M25P80(d); 1304 1305 reset_memory(s); 1306 } 1307 1308 static int m25p80_pre_save(void *opaque) 1309 { 1310 flash_sync_dirty((Flash *)opaque, -1); 1311 1312 return 0; 1313 } 1314 1315 static Property m25p80_properties[] = { 1316 /* This is default value for Micron flash */ 1317 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1318 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1319 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1320 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1321 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1322 DEFINE_PROP_DRIVE("drive", Flash, blk), 1323 DEFINE_PROP_END_OF_LIST(), 1324 }; 1325 1326 static int m25p80_pre_load(void *opaque) 1327 { 1328 Flash *s = (Flash *)opaque; 1329 1330 s->data_read_loop = false; 1331 return 0; 1332 } 1333 1334 static bool m25p80_data_read_loop_needed(void *opaque) 1335 { 1336 Flash *s = (Flash *)opaque; 1337 1338 return s->data_read_loop; 1339 } 1340 1341 static const VMStateDescription vmstate_m25p80_data_read_loop = { 1342 .name = "m25p80/data_read_loop", 1343 .version_id = 1, 1344 .minimum_version_id = 1, 1345 .needed = m25p80_data_read_loop_needed, 1346 .fields = (VMStateField[]) { 1347 VMSTATE_BOOL(data_read_loop, Flash), 1348 VMSTATE_END_OF_LIST() 1349 } 1350 }; 1351 1352 static const VMStateDescription vmstate_m25p80 = { 1353 .name = "m25p80", 1354 .version_id = 0, 1355 .minimum_version_id = 0, 1356 .pre_save = m25p80_pre_save, 1357 .pre_load = m25p80_pre_load, 1358 .fields = (VMStateField[]) { 1359 VMSTATE_UINT8(state, Flash), 1360 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1361 VMSTATE_UINT32(len, Flash), 1362 VMSTATE_UINT32(pos, Flash), 1363 VMSTATE_UINT8(needed_bytes, Flash), 1364 VMSTATE_UINT8(cmd_in_progress, Flash), 1365 VMSTATE_UINT32(cur_addr, Flash), 1366 VMSTATE_BOOL(write_enable, Flash), 1367 VMSTATE_BOOL(reset_enable, Flash), 1368 VMSTATE_UINT8(ear, Flash), 1369 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1370 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1371 VMSTATE_UINT32(volatile_cfg, Flash), 1372 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1373 VMSTATE_BOOL(quad_enable, Flash), 1374 VMSTATE_UINT8(spansion_cr1nv, Flash), 1375 VMSTATE_UINT8(spansion_cr2nv, Flash), 1376 VMSTATE_UINT8(spansion_cr3nv, Flash), 1377 VMSTATE_UINT8(spansion_cr4nv, Flash), 1378 VMSTATE_END_OF_LIST() 1379 }, 1380 .subsections = (const VMStateDescription * []) { 1381 &vmstate_m25p80_data_read_loop, 1382 NULL 1383 } 1384 }; 1385 1386 static void m25p80_class_init(ObjectClass *klass, void *data) 1387 { 1388 DeviceClass *dc = DEVICE_CLASS(klass); 1389 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); 1390 M25P80Class *mc = M25P80_CLASS(klass); 1391 1392 k->realize = m25p80_realize; 1393 k->transfer = m25p80_transfer8; 1394 k->set_cs = m25p80_cs; 1395 k->cs_polarity = SSI_CS_LOW; 1396 dc->vmsd = &vmstate_m25p80; 1397 device_class_set_props(dc, m25p80_properties); 1398 dc->reset = m25p80_reset; 1399 mc->pi = data; 1400 } 1401 1402 static const TypeInfo m25p80_info = { 1403 .name = TYPE_M25P80, 1404 .parent = TYPE_SSI_PERIPHERAL, 1405 .instance_size = sizeof(Flash), 1406 .class_size = sizeof(M25P80Class), 1407 .abstract = true, 1408 }; 1409 1410 static void m25p80_register_types(void) 1411 { 1412 int i; 1413 1414 type_register_static(&m25p80_info); 1415 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1416 TypeInfo ti = { 1417 .name = known_devices[i].part_name, 1418 .parent = TYPE_M25P80, 1419 .class_init = m25p80_class_init, 1420 .class_data = (void *)&known_devices[i], 1421 }; 1422 type_register(&ti); 1423 } 1424 } 1425 1426 type_init(m25p80_register_types) 1427