1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/blockdev.h" 28 #include "hw/ssi/ssi.h" 29 #include "qemu/bitops.h" 30 #include "qemu/log.h" 31 #include "qemu/error-report.h" 32 #include "qapi/error.h" 33 34 #ifndef M25P80_ERR_DEBUG 35 #define M25P80_ERR_DEBUG 0 36 #endif 37 38 #define DB_PRINT_L(level, ...) do { \ 39 if (M25P80_ERR_DEBUG > (level)) { \ 40 fprintf(stderr, ": %s: ", __func__); \ 41 fprintf(stderr, ## __VA_ARGS__); \ 42 } \ 43 } while (0); 44 45 /* Fields for FlashPartInfo->flags */ 46 47 /* erase capabilities */ 48 #define ER_4K 1 49 #define ER_32K 2 50 /* set to allow the page program command to write 0s back to 1. Useful for 51 * modelling EEPROM with SPI flash command set 52 */ 53 #define EEPROM 0x100 54 55 /* 16 MiB max in 3 byte address mode */ 56 #define MAX_3BYTES_SIZE 0x1000000 57 58 #define SPI_NOR_MAX_ID_LEN 6 59 60 typedef struct FlashPartInfo { 61 const char *part_name; 62 /* 63 * This array stores the ID bytes. 64 * The first three bytes are the JEDIC ID. 65 * JEDEC ID zero means "no ID" (mostly older chips). 66 */ 67 uint8_t id[SPI_NOR_MAX_ID_LEN]; 68 uint8_t id_len; 69 /* there is confusion between manufacturers as to what a sector is. In this 70 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 71 * command (opcode 0xd8). 72 */ 73 uint32_t sector_size; 74 uint32_t n_sectors; 75 uint32_t page_size; 76 uint16_t flags; 77 } FlashPartInfo; 78 79 /* adapted from linux */ 80 /* Used when the "_ext_id" is two bytes at most */ 81 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 82 .part_name = _part_name,\ 83 .id = {\ 84 ((_jedec_id) >> 16) & 0xff,\ 85 ((_jedec_id) >> 8) & 0xff,\ 86 (_jedec_id) & 0xff,\ 87 ((_ext_id) >> 8) & 0xff,\ 88 (_ext_id) & 0xff,\ 89 },\ 90 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 91 .sector_size = (_sector_size),\ 92 .n_sectors = (_n_sectors),\ 93 .page_size = 256,\ 94 .flags = (_flags), 95 96 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 97 .part_name = _part_name,\ 98 .id = {\ 99 ((_jedec_id) >> 16) & 0xff,\ 100 ((_jedec_id) >> 8) & 0xff,\ 101 (_jedec_id) & 0xff,\ 102 ((_ext_id) >> 16) & 0xff,\ 103 ((_ext_id) >> 8) & 0xff,\ 104 (_ext_id) & 0xff,\ 105 },\ 106 .id_len = 6,\ 107 .sector_size = (_sector_size),\ 108 .n_sectors = (_n_sectors),\ 109 .page_size = 256,\ 110 .flags = (_flags),\ 111 112 #define JEDEC_NUMONYX 0x20 113 #define JEDEC_WINBOND 0xEF 114 #define JEDEC_SPANSION 0x01 115 116 /* Numonyx (Micron) Configuration register macros */ 117 #define VCFG_DUMMY 0x1 118 #define VCFG_WRAP_SEQUENTIAL 0x2 119 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 120 #define NVCFG_XIP_MODE_MASK (7 << 9) 121 #define VCFG_XIP_MODE_ENABLED (1 << 3) 122 #define CFG_DUMMY_CLK_LEN 4 123 #define NVCFG_DUMMY_CLK_POS 12 124 #define VCFG_DUMMY_CLK_POS 4 125 #define EVCFG_OUT_DRIVER_STRENGHT_DEF 7 126 #define EVCFG_VPP_ACCELERATOR (1 << 3) 127 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 128 #define NVCFG_DUAL_IO_MASK (1 << 2) 129 #define EVCFG_DUAL_IO_ENABLED (1 << 6) 130 #define NVCFG_QUAD_IO_MASK (1 << 3) 131 #define EVCFG_QUAD_IO_ENABLED (1 << 7) 132 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 133 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 134 135 /* Numonyx (Micron) Flag Status Register macros */ 136 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 137 #define FSR_FLASH_READY (1 << 7) 138 139 /* Spansion configuration registers macros. */ 140 #define SPANSION_QUAD_CFG_POS 0 141 #define SPANSION_QUAD_CFG_LEN 1 142 #define SPANSION_DUMMY_CLK_POS 0 143 #define SPANSION_DUMMY_CLK_LEN 4 144 #define SPANSION_ADDR_LEN_POS 7 145 #define SPANSION_ADDR_LEN_LEN 1 146 147 /* 148 * Spansion read mode command length in bytes, 149 * the mode is currently not supported. 150 */ 151 152 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 153 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 154 155 static const FlashPartInfo known_devices[] = { 156 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 157 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 158 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 159 160 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 161 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 162 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 163 164 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 165 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 166 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 167 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 168 169 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 170 171 /* Atmel EEPROMS - it is assumed, that don't care bit in command 172 * is set to 0. Block protection is not supported. 173 */ 174 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 175 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 176 177 /* EON -- en25xxx */ 178 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 179 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 180 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 181 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 182 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 183 184 /* GigaDevice */ 185 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 186 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 187 188 /* Intel/Numonyx -- xxxs33b */ 189 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 190 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 191 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 192 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 193 194 /* Macronix */ 195 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 196 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 197 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 198 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 199 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 200 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 201 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 202 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 203 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) }, 204 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 205 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 206 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 207 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 208 209 /* Micron */ 210 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 211 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 212 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 213 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 214 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 215 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 216 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 217 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 218 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 219 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 220 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 221 { INFO("mt25ql01g", 0x20ba21, 0, 64 << 10, 2048, ER_4K) }, 222 { INFO("mt25qu01g", 0x20bb21, 0, 64 << 10, 2048, ER_4K) }, 223 224 /* Spansion -- single (large) sector size only, at least 225 * for the chips listed here (without boot sectors). 226 */ 227 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 228 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 229 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 230 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 231 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 232 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 233 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 234 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 235 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 236 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 237 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 238 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 239 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 240 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 241 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 242 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 243 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 244 245 /* Spansion -- boot sectors support */ 246 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 247 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 248 249 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 250 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 251 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 252 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 253 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 254 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 255 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 256 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 257 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 258 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 259 260 /* ST Microelectronics -- newer production may have feature updates */ 261 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 262 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 263 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 264 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 265 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 266 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 267 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 268 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 269 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 270 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 271 272 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 273 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 274 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 275 276 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 277 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 278 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 279 280 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 281 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 282 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 283 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 284 285 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 286 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 287 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 288 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 289 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 290 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 291 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 292 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 293 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 294 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 295 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 296 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 297 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 298 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, 299 }; 300 301 typedef enum { 302 NOP = 0, 303 WRSR = 0x1, 304 WRDI = 0x4, 305 RDSR = 0x5, 306 WREN = 0x6, 307 JEDEC_READ = 0x9f, 308 BULK_ERASE = 0xc7, 309 READ_FSR = 0x70, 310 RDCR = 0x15, 311 312 READ = 0x03, 313 READ4 = 0x13, 314 FAST_READ = 0x0b, 315 FAST_READ4 = 0x0c, 316 DOR = 0x3b, 317 DOR4 = 0x3c, 318 QOR = 0x6b, 319 QOR4 = 0x6c, 320 DIOR = 0xbb, 321 DIOR4 = 0xbc, 322 QIOR = 0xeb, 323 QIOR4 = 0xec, 324 325 PP = 0x02, 326 PP4 = 0x12, 327 PP4_4 = 0x3e, 328 DPP = 0xa2, 329 QPP = 0x32, 330 331 ERASE_4K = 0x20, 332 ERASE4_4K = 0x21, 333 ERASE_32K = 0x52, 334 ERASE4_32K = 0x5c, 335 ERASE_SECTOR = 0xd8, 336 ERASE4_SECTOR = 0xdc, 337 338 EN_4BYTE_ADDR = 0xB7, 339 EX_4BYTE_ADDR = 0xE9, 340 341 EXTEND_ADDR_READ = 0xC8, 342 EXTEND_ADDR_WRITE = 0xC5, 343 344 RESET_ENABLE = 0x66, 345 RESET_MEMORY = 0x99, 346 347 /* 348 * Micron: 0x35 - enable QPI 349 * Spansion: 0x35 - read control register 350 */ 351 RDCR_EQIO = 0x35, 352 RSTQIO = 0xf5, 353 354 RNVCR = 0xB5, 355 WNVCR = 0xB1, 356 357 RVCR = 0x85, 358 WVCR = 0x81, 359 360 REVCR = 0x65, 361 WEVCR = 0x61, 362 } FlashCMD; 363 364 typedef enum { 365 STATE_IDLE, 366 STATE_PAGE_PROGRAM, 367 STATE_READ, 368 STATE_COLLECTING_DATA, 369 STATE_COLLECTING_VAR_LEN_DATA, 370 STATE_READING_DATA, 371 } CMDState; 372 373 typedef enum { 374 MAN_SPANSION, 375 MAN_MACRONIX, 376 MAN_NUMONYX, 377 MAN_WINBOND, 378 MAN_GENERIC, 379 } Manufacturer; 380 381 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 382 383 typedef struct Flash { 384 SSISlave parent_obj; 385 386 BlockBackend *blk; 387 388 uint8_t *storage; 389 uint32_t size; 390 int page_size; 391 392 uint8_t state; 393 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 394 uint32_t len; 395 uint32_t pos; 396 uint8_t needed_bytes; 397 uint8_t cmd_in_progress; 398 uint32_t cur_addr; 399 uint32_t nonvolatile_cfg; 400 /* Configuration register for Macronix */ 401 uint32_t volatile_cfg; 402 uint32_t enh_volatile_cfg; 403 /* Spansion cfg registers. */ 404 uint8_t spansion_cr1nv; 405 uint8_t spansion_cr2nv; 406 uint8_t spansion_cr3nv; 407 uint8_t spansion_cr4nv; 408 uint8_t spansion_cr1v; 409 uint8_t spansion_cr2v; 410 uint8_t spansion_cr3v; 411 uint8_t spansion_cr4v; 412 bool write_enable; 413 bool four_bytes_address_mode; 414 bool reset_enable; 415 bool quad_enable; 416 uint8_t ear; 417 418 int64_t dirty_page; 419 420 const FlashPartInfo *pi; 421 422 } Flash; 423 424 typedef struct M25P80Class { 425 SSISlaveClass parent_class; 426 FlashPartInfo *pi; 427 } M25P80Class; 428 429 #define TYPE_M25P80 "m25p80-generic" 430 #define M25P80(obj) \ 431 OBJECT_CHECK(Flash, (obj), TYPE_M25P80) 432 #define M25P80_CLASS(klass) \ 433 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80) 434 #define M25P80_GET_CLASS(obj) \ 435 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80) 436 437 static inline Manufacturer get_man(Flash *s) 438 { 439 switch (s->pi->id[0]) { 440 case 0x20: 441 return MAN_NUMONYX; 442 case 0xEF: 443 return MAN_WINBOND; 444 case 0x01: 445 return MAN_SPANSION; 446 case 0xC2: 447 return MAN_MACRONIX; 448 default: 449 return MAN_GENERIC; 450 } 451 } 452 453 static void blk_sync_complete(void *opaque, int ret) 454 { 455 QEMUIOVector *iov = opaque; 456 457 qemu_iovec_destroy(iov); 458 g_free(iov); 459 460 /* do nothing. Masters do not directly interact with the backing store, 461 * only the working copy so no mutexing required. 462 */ 463 } 464 465 static void flash_sync_page(Flash *s, int page) 466 { 467 QEMUIOVector *iov; 468 469 if (!s->blk || blk_is_read_only(s->blk)) { 470 return; 471 } 472 473 iov = g_new(QEMUIOVector, 1); 474 qemu_iovec_init(iov, 1); 475 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 476 s->pi->page_size); 477 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 478 blk_sync_complete, iov); 479 } 480 481 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 482 { 483 QEMUIOVector *iov; 484 485 if (!s->blk || blk_is_read_only(s->blk)) { 486 return; 487 } 488 489 assert(!(len % BDRV_SECTOR_SIZE)); 490 iov = g_new(QEMUIOVector, 1); 491 qemu_iovec_init(iov, 1); 492 qemu_iovec_add(iov, s->storage + off, len); 493 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 494 } 495 496 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 497 { 498 uint32_t len; 499 uint8_t capa_to_assert = 0; 500 501 switch (cmd) { 502 case ERASE_4K: 503 case ERASE4_4K: 504 len = 4 << 10; 505 capa_to_assert = ER_4K; 506 break; 507 case ERASE_32K: 508 case ERASE4_32K: 509 len = 32 << 10; 510 capa_to_assert = ER_32K; 511 break; 512 case ERASE_SECTOR: 513 case ERASE4_SECTOR: 514 len = s->pi->sector_size; 515 break; 516 case BULK_ERASE: 517 len = s->size; 518 break; 519 default: 520 abort(); 521 } 522 523 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len); 524 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 525 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 526 " device\n", len); 527 } 528 529 if (!s->write_enable) { 530 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 531 return; 532 } 533 memset(s->storage + offset, 0xff, len); 534 flash_sync_area(s, offset, len); 535 } 536 537 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 538 { 539 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 540 flash_sync_page(s, s->dirty_page); 541 s->dirty_page = newpage; 542 } 543 } 544 545 static inline 546 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 547 { 548 uint32_t page = addr / s->pi->page_size; 549 uint8_t prev = s->storage[s->cur_addr]; 550 551 if (!s->write_enable) { 552 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 553 } 554 555 if ((prev ^ data) & data) { 556 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8 557 " -> %" PRIx8 "\n", addr, prev, data); 558 } 559 560 if (s->pi->flags & EEPROM) { 561 s->storage[s->cur_addr] = data; 562 } else { 563 s->storage[s->cur_addr] &= data; 564 } 565 566 flash_sync_dirty(s, page); 567 s->dirty_page = page; 568 } 569 570 static inline int get_addr_length(Flash *s) 571 { 572 /* check if eeprom is in use */ 573 if (s->pi->flags == EEPROM) { 574 return 2; 575 } 576 577 switch (s->cmd_in_progress) { 578 case PP4: 579 case PP4_4: 580 case READ4: 581 case QIOR4: 582 case ERASE4_4K: 583 case ERASE4_32K: 584 case ERASE4_SECTOR: 585 case FAST_READ4: 586 case DOR4: 587 case QOR4: 588 case DIOR4: 589 return 4; 590 default: 591 return s->four_bytes_address_mode ? 4 : 3; 592 } 593 } 594 595 static void complete_collecting_data(Flash *s) 596 { 597 int i, n; 598 599 n = get_addr_length(s); 600 s->cur_addr = (n == 3 ? s->ear : 0); 601 for (i = 0; i < n; ++i) { 602 s->cur_addr <<= 8; 603 s->cur_addr |= s->data[i]; 604 } 605 606 s->cur_addr &= s->size - 1; 607 608 s->state = STATE_IDLE; 609 610 switch (s->cmd_in_progress) { 611 case DPP: 612 case QPP: 613 case PP: 614 case PP4: 615 case PP4_4: 616 s->state = STATE_PAGE_PROGRAM; 617 break; 618 case READ: 619 case READ4: 620 case FAST_READ: 621 case FAST_READ4: 622 case DOR: 623 case DOR4: 624 case QOR: 625 case QOR4: 626 case DIOR: 627 case DIOR4: 628 case QIOR: 629 case QIOR4: 630 s->state = STATE_READ; 631 break; 632 case ERASE_4K: 633 case ERASE4_4K: 634 case ERASE_32K: 635 case ERASE4_32K: 636 case ERASE_SECTOR: 637 case ERASE4_SECTOR: 638 flash_erase(s, s->cur_addr, s->cmd_in_progress); 639 break; 640 case WRSR: 641 switch (get_man(s)) { 642 case MAN_SPANSION: 643 s->quad_enable = !!(s->data[1] & 0x02); 644 break; 645 case MAN_MACRONIX: 646 s->quad_enable = extract32(s->data[0], 6, 1); 647 if (s->len > 1) { 648 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 649 } 650 break; 651 default: 652 break; 653 } 654 if (s->write_enable) { 655 s->write_enable = false; 656 } 657 break; 658 case EXTEND_ADDR_WRITE: 659 s->ear = s->data[0]; 660 break; 661 case WNVCR: 662 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 663 break; 664 case WVCR: 665 s->volatile_cfg = s->data[0]; 666 break; 667 case WEVCR: 668 s->enh_volatile_cfg = s->data[0]; 669 break; 670 default: 671 break; 672 } 673 } 674 675 static void reset_memory(Flash *s) 676 { 677 s->cmd_in_progress = NOP; 678 s->cur_addr = 0; 679 s->ear = 0; 680 s->four_bytes_address_mode = false; 681 s->len = 0; 682 s->needed_bytes = 0; 683 s->pos = 0; 684 s->state = STATE_IDLE; 685 s->write_enable = false; 686 s->reset_enable = false; 687 s->quad_enable = false; 688 689 switch (get_man(s)) { 690 case MAN_NUMONYX: 691 s->volatile_cfg = 0; 692 s->volatile_cfg |= VCFG_DUMMY; 693 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 694 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 695 != NVCFG_XIP_MODE_DISABLED) { 696 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED; 697 } 698 s->volatile_cfg |= deposit32(s->volatile_cfg, 699 VCFG_DUMMY_CLK_POS, 700 CFG_DUMMY_CLK_LEN, 701 extract32(s->nonvolatile_cfg, 702 NVCFG_DUMMY_CLK_POS, 703 CFG_DUMMY_CLK_LEN) 704 ); 705 706 s->enh_volatile_cfg = 0; 707 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF; 708 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 709 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 710 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 711 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; 712 } 713 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 714 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; 715 } 716 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 717 s->four_bytes_address_mode = true; 718 } 719 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 720 s->ear = s->size / MAX_3BYTES_SIZE - 1; 721 } 722 break; 723 case MAN_MACRONIX: 724 s->volatile_cfg = 0x7; 725 break; 726 case MAN_SPANSION: 727 s->spansion_cr1v = s->spansion_cr1nv; 728 s->spansion_cr2v = s->spansion_cr2nv; 729 s->spansion_cr3v = s->spansion_cr3nv; 730 s->spansion_cr4v = s->spansion_cr4nv; 731 s->quad_enable = extract32(s->spansion_cr1v, 732 SPANSION_QUAD_CFG_POS, 733 SPANSION_QUAD_CFG_LEN 734 ); 735 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 736 SPANSION_ADDR_LEN_POS, 737 SPANSION_ADDR_LEN_LEN 738 ); 739 break; 740 default: 741 break; 742 } 743 744 DB_PRINT_L(0, "Reset done.\n"); 745 } 746 747 static void decode_fast_read_cmd(Flash *s) 748 { 749 s->needed_bytes = get_addr_length(s); 750 switch (get_man(s)) { 751 /* Dummy cycles - modeled with bytes writes instead of bits */ 752 case MAN_WINBOND: 753 s->needed_bytes += 8; 754 break; 755 case MAN_NUMONYX: 756 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 757 break; 758 case MAN_MACRONIX: 759 if (extract32(s->volatile_cfg, 6, 2) == 1) { 760 s->needed_bytes += 6; 761 } else { 762 s->needed_bytes += 8; 763 } 764 break; 765 case MAN_SPANSION: 766 s->needed_bytes += extract32(s->spansion_cr2v, 767 SPANSION_DUMMY_CLK_POS, 768 SPANSION_DUMMY_CLK_LEN 769 ); 770 break; 771 default: 772 break; 773 } 774 s->pos = 0; 775 s->len = 0; 776 s->state = STATE_COLLECTING_DATA; 777 } 778 779 static void decode_dio_read_cmd(Flash *s) 780 { 781 s->needed_bytes = get_addr_length(s); 782 /* Dummy cycles modeled with bytes writes instead of bits */ 783 switch (get_man(s)) { 784 case MAN_WINBOND: 785 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 786 break; 787 case MAN_SPANSION: 788 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 789 s->needed_bytes += extract32(s->spansion_cr2v, 790 SPANSION_DUMMY_CLK_POS, 791 SPANSION_DUMMY_CLK_LEN 792 ); 793 break; 794 case MAN_NUMONYX: 795 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 796 break; 797 case MAN_MACRONIX: 798 switch (extract32(s->volatile_cfg, 6, 2)) { 799 case 1: 800 s->needed_bytes += 6; 801 break; 802 case 2: 803 s->needed_bytes += 8; 804 break; 805 default: 806 s->needed_bytes += 4; 807 break; 808 } 809 break; 810 default: 811 break; 812 } 813 s->pos = 0; 814 s->len = 0; 815 s->state = STATE_COLLECTING_DATA; 816 } 817 818 static void decode_qio_read_cmd(Flash *s) 819 { 820 s->needed_bytes = get_addr_length(s); 821 /* Dummy cycles modeled with bytes writes instead of bits */ 822 switch (get_man(s)) { 823 case MAN_WINBOND: 824 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 825 s->needed_bytes += 4; 826 break; 827 case MAN_SPANSION: 828 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 829 s->needed_bytes += extract32(s->spansion_cr2v, 830 SPANSION_DUMMY_CLK_POS, 831 SPANSION_DUMMY_CLK_LEN 832 ); 833 break; 834 case MAN_NUMONYX: 835 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 836 break; 837 case MAN_MACRONIX: 838 switch (extract32(s->volatile_cfg, 6, 2)) { 839 case 1: 840 s->needed_bytes += 4; 841 break; 842 case 2: 843 s->needed_bytes += 8; 844 break; 845 default: 846 s->needed_bytes += 6; 847 break; 848 } 849 break; 850 default: 851 break; 852 } 853 s->pos = 0; 854 s->len = 0; 855 s->state = STATE_COLLECTING_DATA; 856 } 857 858 static void decode_new_cmd(Flash *s, uint32_t value) 859 { 860 s->cmd_in_progress = value; 861 int i; 862 DB_PRINT_L(0, "decoded new command:%x\n", value); 863 864 if (value != RESET_MEMORY) { 865 s->reset_enable = false; 866 } 867 868 switch (value) { 869 870 case ERASE_4K: 871 case ERASE4_4K: 872 case ERASE_32K: 873 case ERASE4_32K: 874 case ERASE_SECTOR: 875 case ERASE4_SECTOR: 876 case READ: 877 case READ4: 878 case DPP: 879 case QPP: 880 case PP: 881 case PP4: 882 case PP4_4: 883 s->needed_bytes = get_addr_length(s); 884 s->pos = 0; 885 s->len = 0; 886 s->state = STATE_COLLECTING_DATA; 887 break; 888 889 case FAST_READ: 890 case FAST_READ4: 891 case DOR: 892 case DOR4: 893 case QOR: 894 case QOR4: 895 decode_fast_read_cmd(s); 896 break; 897 898 case DIOR: 899 case DIOR4: 900 decode_dio_read_cmd(s); 901 break; 902 903 case QIOR: 904 case QIOR4: 905 decode_qio_read_cmd(s); 906 break; 907 908 case WRSR: 909 if (s->write_enable) { 910 switch (get_man(s)) { 911 case MAN_SPANSION: 912 s->needed_bytes = 2; 913 s->state = STATE_COLLECTING_DATA; 914 break; 915 case MAN_MACRONIX: 916 s->needed_bytes = 2; 917 s->state = STATE_COLLECTING_VAR_LEN_DATA; 918 break; 919 default: 920 s->needed_bytes = 1; 921 s->state = STATE_COLLECTING_DATA; 922 } 923 s->pos = 0; 924 } 925 break; 926 927 case WRDI: 928 s->write_enable = false; 929 break; 930 case WREN: 931 s->write_enable = true; 932 break; 933 934 case RDSR: 935 s->data[0] = (!!s->write_enable) << 1; 936 if (get_man(s) == MAN_MACRONIX) { 937 s->data[0] |= (!!s->quad_enable) << 6; 938 } 939 s->pos = 0; 940 s->len = 1; 941 s->state = STATE_READING_DATA; 942 break; 943 944 case READ_FSR: 945 s->data[0] = FSR_FLASH_READY; 946 if (s->four_bytes_address_mode) { 947 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 948 } 949 s->pos = 0; 950 s->len = 1; 951 s->state = STATE_READING_DATA; 952 break; 953 954 case JEDEC_READ: 955 DB_PRINT_L(0, "populated jedec code\n"); 956 for (i = 0; i < s->pi->id_len; i++) { 957 s->data[i] = s->pi->id[i]; 958 } 959 960 s->len = s->pi->id_len; 961 s->pos = 0; 962 s->state = STATE_READING_DATA; 963 break; 964 965 case RDCR: 966 s->data[0] = s->volatile_cfg & 0xFF; 967 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 968 s->pos = 0; 969 s->len = 1; 970 s->state = STATE_READING_DATA; 971 break; 972 973 case BULK_ERASE: 974 if (s->write_enable) { 975 DB_PRINT_L(0, "chip erase\n"); 976 flash_erase(s, 0, BULK_ERASE); 977 } else { 978 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 979 "protect!\n"); 980 } 981 break; 982 case NOP: 983 break; 984 case EN_4BYTE_ADDR: 985 s->four_bytes_address_mode = true; 986 break; 987 case EX_4BYTE_ADDR: 988 s->four_bytes_address_mode = false; 989 break; 990 case EXTEND_ADDR_READ: 991 s->data[0] = s->ear; 992 s->pos = 0; 993 s->len = 1; 994 s->state = STATE_READING_DATA; 995 break; 996 case EXTEND_ADDR_WRITE: 997 if (s->write_enable) { 998 s->needed_bytes = 1; 999 s->pos = 0; 1000 s->len = 0; 1001 s->state = STATE_COLLECTING_DATA; 1002 } 1003 break; 1004 case RNVCR: 1005 s->data[0] = s->nonvolatile_cfg & 0xFF; 1006 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1007 s->pos = 0; 1008 s->len = 2; 1009 s->state = STATE_READING_DATA; 1010 break; 1011 case WNVCR: 1012 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1013 s->needed_bytes = 2; 1014 s->pos = 0; 1015 s->len = 0; 1016 s->state = STATE_COLLECTING_DATA; 1017 } 1018 break; 1019 case RVCR: 1020 s->data[0] = s->volatile_cfg & 0xFF; 1021 s->pos = 0; 1022 s->len = 1; 1023 s->state = STATE_READING_DATA; 1024 break; 1025 case WVCR: 1026 if (s->write_enable) { 1027 s->needed_bytes = 1; 1028 s->pos = 0; 1029 s->len = 0; 1030 s->state = STATE_COLLECTING_DATA; 1031 } 1032 break; 1033 case REVCR: 1034 s->data[0] = s->enh_volatile_cfg & 0xFF; 1035 s->pos = 0; 1036 s->len = 1; 1037 s->state = STATE_READING_DATA; 1038 break; 1039 case WEVCR: 1040 if (s->write_enable) { 1041 s->needed_bytes = 1; 1042 s->pos = 0; 1043 s->len = 0; 1044 s->state = STATE_COLLECTING_DATA; 1045 } 1046 break; 1047 case RESET_ENABLE: 1048 s->reset_enable = true; 1049 break; 1050 case RESET_MEMORY: 1051 if (s->reset_enable) { 1052 reset_memory(s); 1053 } 1054 break; 1055 case RDCR_EQIO: 1056 switch (get_man(s)) { 1057 case MAN_SPANSION: 1058 s->data[0] = (!!s->quad_enable) << 1; 1059 s->pos = 0; 1060 s->len = 1; 1061 s->state = STATE_READING_DATA; 1062 break; 1063 case MAN_MACRONIX: 1064 s->quad_enable = true; 1065 break; 1066 default: 1067 break; 1068 } 1069 break; 1070 case RSTQIO: 1071 s->quad_enable = false; 1072 break; 1073 default: 1074 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1075 break; 1076 } 1077 } 1078 1079 static int m25p80_cs(SSISlave *ss, bool select) 1080 { 1081 Flash *s = M25P80(ss); 1082 1083 if (select) { 1084 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1085 complete_collecting_data(s); 1086 } 1087 s->len = 0; 1088 s->pos = 0; 1089 s->state = STATE_IDLE; 1090 flash_sync_dirty(s, -1); 1091 } 1092 1093 DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); 1094 1095 return 0; 1096 } 1097 1098 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) 1099 { 1100 Flash *s = M25P80(ss); 1101 uint32_t r = 0; 1102 1103 switch (s->state) { 1104 1105 case STATE_PAGE_PROGRAM: 1106 DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n", 1107 s->cur_addr, (uint8_t)tx); 1108 flash_write8(s, s->cur_addr, (uint8_t)tx); 1109 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1110 break; 1111 1112 case STATE_READ: 1113 r = s->storage[s->cur_addr]; 1114 DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr, 1115 (uint8_t)r); 1116 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1117 break; 1118 1119 case STATE_COLLECTING_DATA: 1120 case STATE_COLLECTING_VAR_LEN_DATA: 1121 1122 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1123 qemu_log_mask(LOG_GUEST_ERROR, 1124 "M25P80: Write overrun internal data buffer. " 1125 "SPI controller (QEMU emulator or guest driver) " 1126 "is misbehaving\n"); 1127 s->len = s->pos = 0; 1128 s->state = STATE_IDLE; 1129 break; 1130 } 1131 1132 s->data[s->len] = (uint8_t)tx; 1133 s->len++; 1134 1135 if (s->len == s->needed_bytes) { 1136 complete_collecting_data(s); 1137 } 1138 break; 1139 1140 case STATE_READING_DATA: 1141 1142 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1143 qemu_log_mask(LOG_GUEST_ERROR, 1144 "M25P80: Read overrun internal data buffer. " 1145 "SPI controller (QEMU emulator or guest driver) " 1146 "is misbehaving\n"); 1147 s->len = s->pos = 0; 1148 s->state = STATE_IDLE; 1149 break; 1150 } 1151 1152 r = s->data[s->pos]; 1153 s->pos++; 1154 if (s->pos == s->len) { 1155 s->pos = 0; 1156 s->state = STATE_IDLE; 1157 } 1158 break; 1159 1160 default: 1161 case STATE_IDLE: 1162 decode_new_cmd(s, (uint8_t)tx); 1163 break; 1164 } 1165 1166 return r; 1167 } 1168 1169 static void m25p80_realize(SSISlave *ss, Error **errp) 1170 { 1171 Flash *s = M25P80(ss); 1172 M25P80Class *mc = M25P80_GET_CLASS(s); 1173 1174 s->pi = mc->pi; 1175 1176 s->size = s->pi->sector_size * s->pi->n_sectors; 1177 s->dirty_page = -1; 1178 1179 if (s->blk) { 1180 DB_PRINT_L(0, "Binding to IF_MTD drive\n"); 1181 s->storage = blk_blockalign(s->blk, s->size); 1182 1183 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) { 1184 error_setg(errp, "failed to read the initial flash content"); 1185 return; 1186 } 1187 } else { 1188 DB_PRINT_L(0, "No BDRV - binding to RAM\n"); 1189 s->storage = blk_blockalign(NULL, s->size); 1190 memset(s->storage, 0xFF, s->size); 1191 } 1192 } 1193 1194 static void m25p80_reset(DeviceState *d) 1195 { 1196 Flash *s = M25P80(d); 1197 1198 reset_memory(s); 1199 } 1200 1201 static void m25p80_pre_save(void *opaque) 1202 { 1203 flash_sync_dirty((Flash *)opaque, -1); 1204 } 1205 1206 static Property m25p80_properties[] = { 1207 /* This is default value for Micron flash */ 1208 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1209 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1210 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1211 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1212 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1213 DEFINE_PROP_DRIVE("drive", Flash, blk), 1214 DEFINE_PROP_END_OF_LIST(), 1215 }; 1216 1217 static const VMStateDescription vmstate_m25p80 = { 1218 .name = "m25p80", 1219 .version_id = 0, 1220 .minimum_version_id = 0, 1221 .pre_save = m25p80_pre_save, 1222 .fields = (VMStateField[]) { 1223 VMSTATE_UINT8(state, Flash), 1224 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1225 VMSTATE_UINT32(len, Flash), 1226 VMSTATE_UINT32(pos, Flash), 1227 VMSTATE_UINT8(needed_bytes, Flash), 1228 VMSTATE_UINT8(cmd_in_progress, Flash), 1229 VMSTATE_UINT32(cur_addr, Flash), 1230 VMSTATE_BOOL(write_enable, Flash), 1231 VMSTATE_BOOL(reset_enable, Flash), 1232 VMSTATE_UINT8(ear, Flash), 1233 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1234 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1235 VMSTATE_UINT32(volatile_cfg, Flash), 1236 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1237 VMSTATE_BOOL(quad_enable, Flash), 1238 VMSTATE_UINT8(spansion_cr1nv, Flash), 1239 VMSTATE_UINT8(spansion_cr2nv, Flash), 1240 VMSTATE_UINT8(spansion_cr3nv, Flash), 1241 VMSTATE_UINT8(spansion_cr4nv, Flash), 1242 VMSTATE_END_OF_LIST() 1243 } 1244 }; 1245 1246 static void m25p80_class_init(ObjectClass *klass, void *data) 1247 { 1248 DeviceClass *dc = DEVICE_CLASS(klass); 1249 SSISlaveClass *k = SSI_SLAVE_CLASS(klass); 1250 M25P80Class *mc = M25P80_CLASS(klass); 1251 1252 k->realize = m25p80_realize; 1253 k->transfer = m25p80_transfer8; 1254 k->set_cs = m25p80_cs; 1255 k->cs_polarity = SSI_CS_LOW; 1256 dc->vmsd = &vmstate_m25p80; 1257 dc->props = m25p80_properties; 1258 dc->reset = m25p80_reset; 1259 mc->pi = data; 1260 } 1261 1262 static const TypeInfo m25p80_info = { 1263 .name = TYPE_M25P80, 1264 .parent = TYPE_SSI_SLAVE, 1265 .instance_size = sizeof(Flash), 1266 .class_size = sizeof(M25P80Class), 1267 .abstract = true, 1268 }; 1269 1270 static void m25p80_register_types(void) 1271 { 1272 int i; 1273 1274 type_register_static(&m25p80_info); 1275 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1276 TypeInfo ti = { 1277 .name = known_devices[i].part_name, 1278 .parent = TYPE_M25P80, 1279 .class_init = m25p80_class_init, 1280 .class_data = (void *)&known_devices[i], 1281 }; 1282 type_register(&ti); 1283 } 1284 } 1285 1286 type_init(m25p80_register_types) 1287