1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/blockdev.h" 28 #include "hw/ssi/ssi.h" 29 #include "qemu/bitops.h" 30 31 #ifndef M25P80_ERR_DEBUG 32 #define M25P80_ERR_DEBUG 0 33 #endif 34 35 #define DB_PRINT_L(level, ...) do { \ 36 if (M25P80_ERR_DEBUG > (level)) { \ 37 fprintf(stderr, ": %s: ", __func__); \ 38 fprintf(stderr, ## __VA_ARGS__); \ 39 } \ 40 } while (0); 41 42 /* Fields for FlashPartInfo->flags */ 43 44 /* erase capabilities */ 45 #define ER_4K 1 46 #define ER_32K 2 47 /* set to allow the page program command to write 0s back to 1. Useful for 48 * modelling EEPROM with SPI flash command set 49 */ 50 #define EEPROM 0x100 51 52 /* 16 MiB max in 3 byte address mode */ 53 #define MAX_3BYTES_SIZE 0x1000000 54 55 typedef struct FlashPartInfo { 56 const char *part_name; 57 /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */ 58 uint32_t jedec; 59 /* extended jedec code */ 60 uint16_t ext_jedec; 61 /* there is confusion between manufacturers as to what a sector is. In this 62 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 63 * command (opcode 0xd8). 64 */ 65 uint32_t sector_size; 66 uint32_t n_sectors; 67 uint32_t page_size; 68 uint16_t flags; 69 } FlashPartInfo; 70 71 /* adapted from linux */ 72 73 #define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\ 74 .part_name = (_part_name),\ 75 .jedec = (_jedec),\ 76 .ext_jedec = (_ext_jedec),\ 77 .sector_size = (_sector_size),\ 78 .n_sectors = (_n_sectors),\ 79 .page_size = 256,\ 80 .flags = (_flags),\ 81 82 #define JEDEC_NUMONYX 0x20 83 #define JEDEC_WINBOND 0xEF 84 #define JEDEC_SPANSION 0x01 85 86 /* Numonyx (Micron) Configuration register macros */ 87 #define VCFG_DUMMY 0x1 88 #define VCFG_WRAP_SEQUENTIAL 0x2 89 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 90 #define NVCFG_XIP_MODE_MASK (7 << 9) 91 #define VCFG_XIP_MODE_ENABLED (1 << 3) 92 #define CFG_DUMMY_CLK_LEN 4 93 #define NVCFG_DUMMY_CLK_POS 12 94 #define VCFG_DUMMY_CLK_POS 4 95 #define EVCFG_OUT_DRIVER_STRENGHT_DEF 7 96 #define EVCFG_VPP_ACCELERATOR (1 << 3) 97 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 98 #define NVCFG_DUAL_IO_MASK (1 << 2) 99 #define EVCFG_DUAL_IO_ENABLED (1 << 6) 100 #define NVCFG_QUAD_IO_MASK (1 << 3) 101 #define EVCFG_QUAD_IO_ENABLED (1 << 7) 102 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 103 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 104 #define CFG_UPPER_128MB_SEG_ENABLED 0x3 105 106 /* Numonyx (Micron) Flag Status Register macros */ 107 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 108 #define FSR_FLASH_READY (1 << 7) 109 110 static const FlashPartInfo known_devices[] = { 111 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 112 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 113 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 114 115 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 116 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 117 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 118 119 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 120 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 121 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 122 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 123 124 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 125 126 /* Atmel EEPROMS - it is assumed, that don't care bit in command 127 * is set to 0. Block protection is not supported. 128 */ 129 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 130 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 131 132 /* EON -- en25xxx */ 133 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 134 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 135 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 136 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 137 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 138 139 /* GigaDevice */ 140 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 141 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 142 143 /* Intel/Numonyx -- xxxs33b */ 144 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 145 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 146 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 147 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 148 149 /* Macronix */ 150 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 151 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 152 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 153 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 154 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 155 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 156 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 157 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 158 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) }, 159 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 160 161 /* Micron */ 162 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 163 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 164 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 165 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 166 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 167 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 168 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 169 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 170 171 /* Spansion -- single (large) sector size only, at least 172 * for the chips listed here (without boot sectors). 173 */ 174 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 175 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 176 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 177 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 178 { INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) }, 179 { INFO("s70fl01gs", 0x010221, 0x4d00, 256 << 10, 256, 0) }, 180 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 181 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 182 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 183 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 184 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 185 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 186 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 187 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 188 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 189 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 190 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 191 192 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 193 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 194 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 195 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 196 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 197 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 198 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 199 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 200 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 201 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 202 203 /* ST Microelectronics -- newer production may have feature updates */ 204 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 205 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 206 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 207 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 208 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 209 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 210 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 211 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 212 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 213 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 214 215 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 216 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 217 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 218 219 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 220 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 221 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 222 223 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 224 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 225 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 226 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 227 228 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 229 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 230 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 231 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 232 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 233 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 234 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 235 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 236 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 237 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 238 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 239 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 240 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 241 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, 242 243 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 244 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 245 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 246 }; 247 248 typedef enum { 249 NOP = 0, 250 WRSR = 0x1, 251 WRDI = 0x4, 252 RDSR = 0x5, 253 WREN = 0x6, 254 JEDEC_READ = 0x9f, 255 BULK_ERASE = 0xc7, 256 READ_FSR = 0x70, 257 258 READ = 0x03, 259 READ4 = 0x13, 260 FAST_READ = 0x0b, 261 FAST_READ4 = 0x0c, 262 DOR = 0x3b, 263 DOR4 = 0x3c, 264 QOR = 0x6b, 265 QOR4 = 0x6c, 266 DIOR = 0xbb, 267 DIOR4 = 0xbc, 268 QIOR = 0xeb, 269 QIOR4 = 0xec, 270 271 PP = 0x02, 272 PP4 = 0x12, 273 DPP = 0xa2, 274 QPP = 0x32, 275 276 ERASE_4K = 0x20, 277 ERASE4_4K = 0x21, 278 ERASE_32K = 0x52, 279 ERASE_SECTOR = 0xd8, 280 ERASE4_SECTOR = 0xdc, 281 282 EN_4BYTE_ADDR = 0xB7, 283 EX_4BYTE_ADDR = 0xE9, 284 285 EXTEND_ADDR_READ = 0xC8, 286 EXTEND_ADDR_WRITE = 0xC5, 287 288 RESET_ENABLE = 0x66, 289 RESET_MEMORY = 0x99, 290 291 RNVCR = 0xB5, 292 WNVCR = 0xB1, 293 294 RVCR = 0x85, 295 WVCR = 0x81, 296 297 REVCR = 0x65, 298 WEVCR = 0x61, 299 } FlashCMD; 300 301 typedef enum { 302 STATE_IDLE, 303 STATE_PAGE_PROGRAM, 304 STATE_READ, 305 STATE_COLLECTING_DATA, 306 STATE_READING_DATA, 307 } CMDState; 308 309 typedef struct Flash { 310 SSISlave parent_obj; 311 312 BlockBackend *blk; 313 314 uint8_t *storage; 315 uint32_t size; 316 int page_size; 317 318 uint8_t state; 319 uint8_t data[16]; 320 uint32_t len; 321 uint32_t pos; 322 uint8_t needed_bytes; 323 uint8_t cmd_in_progress; 324 uint64_t cur_addr; 325 uint32_t nonvolatile_cfg; 326 uint32_t volatile_cfg; 327 uint32_t enh_volatile_cfg; 328 bool write_enable; 329 bool four_bytes_address_mode; 330 bool reset_enable; 331 uint8_t ear; 332 333 int64_t dirty_page; 334 335 const FlashPartInfo *pi; 336 337 } Flash; 338 339 typedef struct M25P80Class { 340 SSISlaveClass parent_class; 341 FlashPartInfo *pi; 342 } M25P80Class; 343 344 #define TYPE_M25P80 "m25p80-generic" 345 #define M25P80(obj) \ 346 OBJECT_CHECK(Flash, (obj), TYPE_M25P80) 347 #define M25P80_CLASS(klass) \ 348 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80) 349 #define M25P80_GET_CLASS(obj) \ 350 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80) 351 352 static void blk_sync_complete(void *opaque, int ret) 353 { 354 /* do nothing. Masters do not directly interact with the backing store, 355 * only the working copy so no mutexing required. 356 */ 357 } 358 359 static void flash_sync_page(Flash *s, int page) 360 { 361 QEMUIOVector iov; 362 363 if (!s->blk || blk_is_read_only(s->blk)) { 364 return; 365 } 366 367 qemu_iovec_init(&iov, 1); 368 qemu_iovec_add(&iov, s->storage + page * s->pi->page_size, 369 s->pi->page_size); 370 blk_aio_pwritev(s->blk, page * s->pi->page_size, &iov, 0, 371 blk_sync_complete, NULL); 372 } 373 374 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 375 { 376 QEMUIOVector iov; 377 378 if (!s->blk || blk_is_read_only(s->blk)) { 379 return; 380 } 381 382 assert(!(len % BDRV_SECTOR_SIZE)); 383 qemu_iovec_init(&iov, 1); 384 qemu_iovec_add(&iov, s->storage + off, len); 385 blk_aio_pwritev(s->blk, off, &iov, 0, blk_sync_complete, NULL); 386 } 387 388 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 389 { 390 uint32_t len; 391 uint8_t capa_to_assert = 0; 392 393 switch (cmd) { 394 case ERASE_4K: 395 case ERASE4_4K: 396 len = 4 << 10; 397 capa_to_assert = ER_4K; 398 break; 399 case ERASE_32K: 400 len = 32 << 10; 401 capa_to_assert = ER_32K; 402 break; 403 case ERASE_SECTOR: 404 case ERASE4_SECTOR: 405 len = s->pi->sector_size; 406 break; 407 case BULK_ERASE: 408 len = s->size; 409 break; 410 default: 411 abort(); 412 } 413 414 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len); 415 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 416 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 417 " device\n", len); 418 } 419 420 if (!s->write_enable) { 421 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 422 return; 423 } 424 memset(s->storage + offset, 0xff, len); 425 flash_sync_area(s, offset, len); 426 } 427 428 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 429 { 430 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 431 flash_sync_page(s, s->dirty_page); 432 s->dirty_page = newpage; 433 } 434 } 435 436 static inline 437 void flash_write8(Flash *s, uint64_t addr, uint8_t data) 438 { 439 int64_t page = addr / s->pi->page_size; 440 uint8_t prev = s->storage[s->cur_addr]; 441 442 if (!s->write_enable) { 443 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 444 } 445 446 if ((prev ^ data) & data) { 447 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8 448 " -> %" PRIx8 "\n", addr, prev, data); 449 } 450 451 if (s->pi->flags & EEPROM) { 452 s->storage[s->cur_addr] = data; 453 } else { 454 s->storage[s->cur_addr] &= data; 455 } 456 457 flash_sync_dirty(s, page); 458 s->dirty_page = page; 459 } 460 461 static inline int get_addr_length(Flash *s) 462 { 463 /* check if eeprom is in use */ 464 if (s->pi->flags == EEPROM) { 465 return 2; 466 } 467 468 switch (s->cmd_in_progress) { 469 case PP4: 470 case READ4: 471 case QIOR4: 472 case ERASE4_4K: 473 case ERASE4_SECTOR: 474 case FAST_READ4: 475 case DOR4: 476 case QOR4: 477 case DIOR4: 478 return 4; 479 default: 480 return s->four_bytes_address_mode ? 4 : 3; 481 } 482 } 483 484 static void complete_collecting_data(Flash *s) 485 { 486 int i; 487 488 s->cur_addr = 0; 489 490 for (i = 0; i < get_addr_length(s); ++i) { 491 s->cur_addr <<= 8; 492 s->cur_addr |= s->data[i]; 493 } 494 495 if (get_addr_length(s) == 3) { 496 s->cur_addr += (s->ear & 0x3) * MAX_3BYTES_SIZE; 497 } 498 499 s->state = STATE_IDLE; 500 501 switch (s->cmd_in_progress) { 502 case DPP: 503 case QPP: 504 case PP: 505 case PP4: 506 s->state = STATE_PAGE_PROGRAM; 507 break; 508 case READ: 509 case READ4: 510 case FAST_READ: 511 case FAST_READ4: 512 case DOR: 513 case DOR4: 514 case QOR: 515 case QOR4: 516 case DIOR: 517 case DIOR4: 518 case QIOR: 519 case QIOR4: 520 s->state = STATE_READ; 521 break; 522 case ERASE_4K: 523 case ERASE4_4K: 524 case ERASE_32K: 525 case ERASE_SECTOR: 526 case ERASE4_SECTOR: 527 flash_erase(s, s->cur_addr, s->cmd_in_progress); 528 break; 529 case WRSR: 530 if (s->write_enable) { 531 s->write_enable = false; 532 } 533 break; 534 case EXTEND_ADDR_WRITE: 535 s->ear = s->data[0]; 536 break; 537 case WNVCR: 538 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 539 break; 540 case WVCR: 541 s->volatile_cfg = s->data[0]; 542 break; 543 case WEVCR: 544 s->enh_volatile_cfg = s->data[0]; 545 break; 546 default: 547 break; 548 } 549 } 550 551 static void reset_memory(Flash *s) 552 { 553 s->cmd_in_progress = NOP; 554 s->cur_addr = 0; 555 s->ear = 0; 556 s->four_bytes_address_mode = false; 557 s->len = 0; 558 s->needed_bytes = 0; 559 s->pos = 0; 560 s->state = STATE_IDLE; 561 s->write_enable = false; 562 s->reset_enable = false; 563 564 if (((s->pi->jedec >> 16) & 0xFF) == JEDEC_NUMONYX) { 565 s->volatile_cfg = 0; 566 s->volatile_cfg |= VCFG_DUMMY; 567 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 568 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 569 != NVCFG_XIP_MODE_DISABLED) { 570 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED; 571 } 572 s->volatile_cfg |= deposit32(s->volatile_cfg, 573 VCFG_DUMMY_CLK_POS, 574 CFG_DUMMY_CLK_LEN, 575 extract32(s->nonvolatile_cfg, 576 NVCFG_DUMMY_CLK_POS, 577 CFG_DUMMY_CLK_LEN) 578 ); 579 580 s->enh_volatile_cfg = 0; 581 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF; 582 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 583 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 584 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 585 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; 586 } 587 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 588 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; 589 } 590 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 591 s->four_bytes_address_mode = true; 592 } 593 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 594 s->ear = CFG_UPPER_128MB_SEG_ENABLED; 595 } 596 } 597 598 DB_PRINT_L(0, "Reset done.\n"); 599 } 600 601 static void decode_new_cmd(Flash *s, uint32_t value) 602 { 603 s->cmd_in_progress = value; 604 DB_PRINT_L(0, "decoded new command:%x\n", value); 605 606 if (value != RESET_MEMORY) { 607 s->reset_enable = false; 608 } 609 610 switch (value) { 611 612 case ERASE_4K: 613 case ERASE4_4K: 614 case ERASE_32K: 615 case ERASE_SECTOR: 616 case ERASE4_SECTOR: 617 case READ: 618 case READ4: 619 case DPP: 620 case QPP: 621 case PP: 622 case PP4: 623 s->needed_bytes = get_addr_length(s); 624 s->pos = 0; 625 s->len = 0; 626 s->state = STATE_COLLECTING_DATA; 627 break; 628 629 case FAST_READ: 630 case FAST_READ4: 631 case DOR: 632 case DOR4: 633 case QOR: 634 case QOR4: 635 s->needed_bytes = get_addr_length(s); 636 if (((s->pi->jedec >> 16) & 0xFF) == JEDEC_NUMONYX) { 637 /* Dummy cycles modeled with bytes writes instead of bits */ 638 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 639 } 640 s->pos = 0; 641 s->len = 0; 642 s->state = STATE_COLLECTING_DATA; 643 break; 644 645 case DIOR: 646 case DIOR4: 647 switch ((s->pi->jedec >> 16) & 0xFF) { 648 case JEDEC_WINBOND: 649 case JEDEC_SPANSION: 650 s->needed_bytes = 4; 651 break; 652 default: 653 s->needed_bytes = get_addr_length(s); 654 /* Dummy cycles modeled with bytes writes instead of bits */ 655 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 656 } 657 s->pos = 0; 658 s->len = 0; 659 s->state = STATE_COLLECTING_DATA; 660 break; 661 662 case QIOR: 663 case QIOR4: 664 switch ((s->pi->jedec >> 16) & 0xFF) { 665 case JEDEC_WINBOND: 666 case JEDEC_SPANSION: 667 s->needed_bytes = 6; 668 break; 669 default: 670 s->needed_bytes = get_addr_length(s); 671 /* Dummy cycles modeled with bytes writes instead of bits */ 672 s->needed_bytes += extract32(s->volatile_cfg, 4, 4); 673 } 674 s->pos = 0; 675 s->len = 0; 676 s->state = STATE_COLLECTING_DATA; 677 break; 678 679 case WRSR: 680 if (s->write_enable) { 681 s->needed_bytes = 1; 682 s->pos = 0; 683 s->len = 0; 684 s->state = STATE_COLLECTING_DATA; 685 } 686 break; 687 688 case WRDI: 689 s->write_enable = false; 690 break; 691 case WREN: 692 s->write_enable = true; 693 break; 694 695 case RDSR: 696 s->data[0] = (!!s->write_enable) << 1; 697 s->pos = 0; 698 s->len = 1; 699 s->state = STATE_READING_DATA; 700 break; 701 702 case READ_FSR: 703 s->data[0] = FSR_FLASH_READY; 704 if (s->four_bytes_address_mode) { 705 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 706 } 707 s->pos = 0; 708 s->len = 1; 709 s->state = STATE_READING_DATA; 710 break; 711 712 case JEDEC_READ: 713 DB_PRINT_L(0, "populated jedec code\n"); 714 s->data[0] = (s->pi->jedec >> 16) & 0xff; 715 s->data[1] = (s->pi->jedec >> 8) & 0xff; 716 s->data[2] = s->pi->jedec & 0xff; 717 if (s->pi->ext_jedec) { 718 s->data[3] = (s->pi->ext_jedec >> 8) & 0xff; 719 s->data[4] = s->pi->ext_jedec & 0xff; 720 s->len = 5; 721 } else { 722 s->len = 3; 723 } 724 s->pos = 0; 725 s->state = STATE_READING_DATA; 726 break; 727 728 case BULK_ERASE: 729 if (s->write_enable) { 730 DB_PRINT_L(0, "chip erase\n"); 731 flash_erase(s, 0, BULK_ERASE); 732 } else { 733 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 734 "protect!\n"); 735 } 736 break; 737 case NOP: 738 break; 739 case EN_4BYTE_ADDR: 740 s->four_bytes_address_mode = true; 741 break; 742 case EX_4BYTE_ADDR: 743 s->four_bytes_address_mode = false; 744 break; 745 case EXTEND_ADDR_READ: 746 s->data[0] = s->ear; 747 s->pos = 0; 748 s->len = 1; 749 s->state = STATE_READING_DATA; 750 break; 751 case EXTEND_ADDR_WRITE: 752 if (s->write_enable) { 753 s->needed_bytes = 1; 754 s->pos = 0; 755 s->len = 0; 756 s->state = STATE_COLLECTING_DATA; 757 } 758 break; 759 case RNVCR: 760 s->data[0] = s->nonvolatile_cfg & 0xFF; 761 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 762 s->pos = 0; 763 s->len = 2; 764 s->state = STATE_READING_DATA; 765 break; 766 case WNVCR: 767 if (s->write_enable) { 768 s->needed_bytes = 2; 769 s->pos = 0; 770 s->len = 0; 771 s->state = STATE_COLLECTING_DATA; 772 } 773 break; 774 case RVCR: 775 s->data[0] = s->volatile_cfg & 0xFF; 776 s->pos = 0; 777 s->len = 1; 778 s->state = STATE_READING_DATA; 779 break; 780 case WVCR: 781 if (s->write_enable) { 782 s->needed_bytes = 1; 783 s->pos = 0; 784 s->len = 0; 785 s->state = STATE_COLLECTING_DATA; 786 } 787 break; 788 case REVCR: 789 s->data[0] = s->enh_volatile_cfg & 0xFF; 790 s->pos = 0; 791 s->len = 1; 792 s->state = STATE_READING_DATA; 793 break; 794 case WEVCR: 795 if (s->write_enable) { 796 s->needed_bytes = 1; 797 s->pos = 0; 798 s->len = 0; 799 s->state = STATE_COLLECTING_DATA; 800 } 801 break; 802 case RESET_ENABLE: 803 s->reset_enable = true; 804 break; 805 case RESET_MEMORY: 806 if (s->reset_enable) { 807 reset_memory(s); 808 } 809 break; 810 default: 811 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 812 break; 813 } 814 } 815 816 static int m25p80_cs(SSISlave *ss, bool select) 817 { 818 Flash *s = M25P80(ss); 819 820 if (select) { 821 s->len = 0; 822 s->pos = 0; 823 s->state = STATE_IDLE; 824 flash_sync_dirty(s, -1); 825 } 826 827 DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); 828 829 return 0; 830 } 831 832 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) 833 { 834 Flash *s = M25P80(ss); 835 uint32_t r = 0; 836 837 switch (s->state) { 838 839 case STATE_PAGE_PROGRAM: 840 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n", 841 s->cur_addr, (uint8_t)tx); 842 flash_write8(s, s->cur_addr, (uint8_t)tx); 843 s->cur_addr++; 844 break; 845 846 case STATE_READ: 847 r = s->storage[s->cur_addr]; 848 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr, 849 (uint8_t)r); 850 s->cur_addr = (s->cur_addr + 1) % s->size; 851 break; 852 853 case STATE_COLLECTING_DATA: 854 s->data[s->len] = (uint8_t)tx; 855 s->len++; 856 857 if (s->len == s->needed_bytes) { 858 complete_collecting_data(s); 859 } 860 break; 861 862 case STATE_READING_DATA: 863 r = s->data[s->pos]; 864 s->pos++; 865 if (s->pos == s->len) { 866 s->pos = 0; 867 s->state = STATE_IDLE; 868 } 869 break; 870 871 default: 872 case STATE_IDLE: 873 decode_new_cmd(s, (uint8_t)tx); 874 break; 875 } 876 877 return r; 878 } 879 880 static int m25p80_init(SSISlave *ss) 881 { 882 DriveInfo *dinfo; 883 Flash *s = M25P80(ss); 884 M25P80Class *mc = M25P80_GET_CLASS(s); 885 886 s->pi = mc->pi; 887 888 s->size = s->pi->sector_size * s->pi->n_sectors; 889 s->dirty_page = -1; 890 891 /* FIXME use a qdev drive property instead of drive_get_next() */ 892 dinfo = drive_get_next(IF_MTD); 893 894 if (dinfo) { 895 DB_PRINT_L(0, "Binding to IF_MTD drive\n"); 896 s->blk = blk_by_legacy_dinfo(dinfo); 897 blk_attach_dev_nofail(s->blk, s); 898 899 s->storage = blk_blockalign(s->blk, s->size); 900 901 /* FIXME: Move to late init */ 902 if (blk_pread(s->blk, 0, s->storage, s->size)) { 903 fprintf(stderr, "Failed to initialize SPI flash!\n"); 904 return 1; 905 } 906 } else { 907 DB_PRINT_L(0, "No BDRV - binding to RAM\n"); 908 s->storage = blk_blockalign(NULL, s->size); 909 memset(s->storage, 0xFF, s->size); 910 } 911 912 return 0; 913 } 914 915 static void m25p80_reset(DeviceState *d) 916 { 917 Flash *s = M25P80(d); 918 919 reset_memory(s); 920 } 921 922 static void m25p80_pre_save(void *opaque) 923 { 924 flash_sync_dirty((Flash *)opaque, -1); 925 } 926 927 static Property m25p80_properties[] = { 928 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 929 DEFINE_PROP_END_OF_LIST(), 930 }; 931 932 static const VMStateDescription vmstate_m25p80 = { 933 .name = "xilinx_spi", 934 .version_id = 2, 935 .minimum_version_id = 1, 936 .pre_save = m25p80_pre_save, 937 .fields = (VMStateField[]) { 938 VMSTATE_UINT8(state, Flash), 939 VMSTATE_UINT8_ARRAY(data, Flash, 16), 940 VMSTATE_UINT32(len, Flash), 941 VMSTATE_UINT32(pos, Flash), 942 VMSTATE_UINT8(needed_bytes, Flash), 943 VMSTATE_UINT8(cmd_in_progress, Flash), 944 VMSTATE_UINT64(cur_addr, Flash), 945 VMSTATE_BOOL(write_enable, Flash), 946 VMSTATE_BOOL_V(reset_enable, Flash, 2), 947 VMSTATE_UINT8_V(ear, Flash, 2), 948 VMSTATE_BOOL_V(four_bytes_address_mode, Flash, 2), 949 VMSTATE_UINT32_V(nonvolatile_cfg, Flash, 2), 950 VMSTATE_UINT32_V(volatile_cfg, Flash, 2), 951 VMSTATE_UINT32_V(enh_volatile_cfg, Flash, 2), 952 VMSTATE_END_OF_LIST() 953 } 954 }; 955 956 static void m25p80_class_init(ObjectClass *klass, void *data) 957 { 958 DeviceClass *dc = DEVICE_CLASS(klass); 959 SSISlaveClass *k = SSI_SLAVE_CLASS(klass); 960 M25P80Class *mc = M25P80_CLASS(klass); 961 962 k->init = m25p80_init; 963 k->transfer = m25p80_transfer8; 964 k->set_cs = m25p80_cs; 965 k->cs_polarity = SSI_CS_LOW; 966 dc->vmsd = &vmstate_m25p80; 967 dc->props = m25p80_properties; 968 dc->reset = m25p80_reset; 969 mc->pi = data; 970 } 971 972 static const TypeInfo m25p80_info = { 973 .name = TYPE_M25P80, 974 .parent = TYPE_SSI_SLAVE, 975 .instance_size = sizeof(Flash), 976 .class_size = sizeof(M25P80Class), 977 .abstract = true, 978 }; 979 980 static void m25p80_register_types(void) 981 { 982 int i; 983 984 type_register_static(&m25p80_info); 985 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 986 TypeInfo ti = { 987 .name = known_devices[i].part_name, 988 .parent = TYPE_M25P80, 989 .class_init = m25p80_class_init, 990 .class_data = (void *)&known_devices[i], 991 }; 992 type_register(&ti); 993 } 994 } 995 996 type_init(m25p80_register_types) 997