1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/blockdev.h" 28 #include "hw/ssi.h" 29 30 #ifndef M25P80_ERR_DEBUG 31 #define M25P80_ERR_DEBUG 0 32 #endif 33 34 #define DB_PRINT_L(level, ...) do { \ 35 if (M25P80_ERR_DEBUG > (level)) { \ 36 fprintf(stderr, ": %s: ", __func__); \ 37 fprintf(stderr, ## __VA_ARGS__); \ 38 } \ 39 } while (0); 40 41 /* Fields for FlashPartInfo->flags */ 42 43 /* erase capabilities */ 44 #define ER_4K 1 45 #define ER_32K 2 46 /* set to allow the page program command to write 0s back to 1. Useful for 47 * modelling EEPROM with SPI flash command set 48 */ 49 #define WR_1 0x100 50 51 typedef struct FlashPartInfo { 52 const char *part_name; 53 /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */ 54 uint32_t jedec; 55 /* extended jedec code */ 56 uint16_t ext_jedec; 57 /* there is confusion between manufacturers as to what a sector is. In this 58 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 59 * command (opcode 0xd8). 60 */ 61 uint32_t sector_size; 62 uint32_t n_sectors; 63 uint32_t page_size; 64 uint8_t flags; 65 } FlashPartInfo; 66 67 /* adapted from linux */ 68 69 #define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\ 70 .part_name = (_part_name),\ 71 .jedec = (_jedec),\ 72 .ext_jedec = (_ext_jedec),\ 73 .sector_size = (_sector_size),\ 74 .n_sectors = (_n_sectors),\ 75 .page_size = 256,\ 76 .flags = (_flags),\ 77 78 #define JEDEC_NUMONYX 0x20 79 #define JEDEC_WINBOND 0xEF 80 #define JEDEC_SPANSION 0x01 81 82 static const FlashPartInfo known_devices[] = { 83 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 84 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 85 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 86 87 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 88 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 89 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 90 91 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 92 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 93 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 94 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 95 96 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 97 98 /* EON -- en25xxx */ 99 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 100 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 101 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 102 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 103 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 104 105 /* GigaDevice */ 106 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 107 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 108 109 /* Intel/Numonyx -- xxxs33b */ 110 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 111 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 112 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 113 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 114 115 /* Macronix */ 116 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 117 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 118 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 119 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 120 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 121 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 122 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 123 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 124 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) }, 125 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 126 127 /* Micron */ 128 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 129 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 130 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 131 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 132 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 133 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 134 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 135 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, 136 137 /* Spansion -- single (large) sector size only, at least 138 * for the chips listed here (without boot sectors). 139 */ 140 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 141 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 142 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 143 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 144 { INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) }, 145 { INFO("s70fl01gs", 0x010221, 0x4d00, 256 << 10, 256, 0) }, 146 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 147 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 148 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 149 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 150 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 151 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 152 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 153 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 154 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 155 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 156 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 157 158 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 159 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 160 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 161 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 162 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 163 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 164 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 165 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 166 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 167 168 /* ST Microelectronics -- newer production may have feature updates */ 169 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 170 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 171 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 172 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 173 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 174 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 175 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 176 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 177 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 178 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 179 180 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 181 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 182 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 183 184 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 185 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 186 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 187 188 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 189 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 190 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 191 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 192 193 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 194 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 195 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 196 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 197 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 198 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 199 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 200 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 201 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 202 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 203 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 204 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 205 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 206 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, 207 208 /* Numonyx -- n25q128 */ 209 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 210 }; 211 212 typedef enum { 213 NOP = 0, 214 WRSR = 0x1, 215 WRDI = 0x4, 216 RDSR = 0x5, 217 WREN = 0x6, 218 JEDEC_READ = 0x9f, 219 BULK_ERASE = 0xc7, 220 221 READ = 0x3, 222 FAST_READ = 0xb, 223 DOR = 0x3b, 224 QOR = 0x6b, 225 DIOR = 0xbb, 226 QIOR = 0xeb, 227 228 PP = 0x2, 229 DPP = 0xa2, 230 QPP = 0x32, 231 232 ERASE_4K = 0x20, 233 ERASE_32K = 0x52, 234 ERASE_SECTOR = 0xd8, 235 } FlashCMD; 236 237 typedef enum { 238 STATE_IDLE, 239 STATE_PAGE_PROGRAM, 240 STATE_READ, 241 STATE_COLLECTING_DATA, 242 STATE_READING_DATA, 243 } CMDState; 244 245 typedef struct Flash { 246 SSISlave parent_obj; 247 248 uint32_t r; 249 250 BlockBackend *blk; 251 252 uint8_t *storage; 253 uint32_t size; 254 int page_size; 255 256 uint8_t state; 257 uint8_t data[16]; 258 uint32_t len; 259 uint32_t pos; 260 uint8_t needed_bytes; 261 uint8_t cmd_in_progress; 262 uint64_t cur_addr; 263 bool write_enable; 264 265 int64_t dirty_page; 266 267 const FlashPartInfo *pi; 268 269 } Flash; 270 271 typedef struct M25P80Class { 272 SSISlaveClass parent_class; 273 FlashPartInfo *pi; 274 } M25P80Class; 275 276 #define TYPE_M25P80 "m25p80-generic" 277 #define M25P80(obj) \ 278 OBJECT_CHECK(Flash, (obj), TYPE_M25P80) 279 #define M25P80_CLASS(klass) \ 280 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80) 281 #define M25P80_GET_CLASS(obj) \ 282 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80) 283 284 static void blk_sync_complete(void *opaque, int ret) 285 { 286 /* do nothing. Masters do not directly interact with the backing store, 287 * only the working copy so no mutexing required. 288 */ 289 } 290 291 static void flash_sync_page(Flash *s, int page) 292 { 293 int blk_sector, nb_sectors; 294 QEMUIOVector iov; 295 296 if (!s->blk || blk_is_read_only(s->blk)) { 297 return; 298 } 299 300 blk_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE; 301 nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE); 302 qemu_iovec_init(&iov, 1); 303 qemu_iovec_add(&iov, s->storage + blk_sector * BDRV_SECTOR_SIZE, 304 nb_sectors * BDRV_SECTOR_SIZE); 305 blk_aio_writev(s->blk, blk_sector, &iov, nb_sectors, blk_sync_complete, 306 NULL); 307 } 308 309 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 310 { 311 int64_t start, end, nb_sectors; 312 QEMUIOVector iov; 313 314 if (!s->blk || blk_is_read_only(s->blk)) { 315 return; 316 } 317 318 assert(!(len % BDRV_SECTOR_SIZE)); 319 start = off / BDRV_SECTOR_SIZE; 320 end = (off + len) / BDRV_SECTOR_SIZE; 321 nb_sectors = end - start; 322 qemu_iovec_init(&iov, 1); 323 qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE), 324 nb_sectors * BDRV_SECTOR_SIZE); 325 blk_aio_writev(s->blk, start, &iov, nb_sectors, blk_sync_complete, NULL); 326 } 327 328 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 329 { 330 uint32_t len; 331 uint8_t capa_to_assert = 0; 332 333 switch (cmd) { 334 case ERASE_4K: 335 len = 4 << 10; 336 capa_to_assert = ER_4K; 337 break; 338 case ERASE_32K: 339 len = 32 << 10; 340 capa_to_assert = ER_32K; 341 break; 342 case ERASE_SECTOR: 343 len = s->pi->sector_size; 344 break; 345 case BULK_ERASE: 346 len = s->size; 347 break; 348 default: 349 abort(); 350 } 351 352 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len); 353 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 354 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 355 " device\n", len); 356 } 357 358 if (!s->write_enable) { 359 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 360 return; 361 } 362 memset(s->storage + offset, 0xff, len); 363 flash_sync_area(s, offset, len); 364 } 365 366 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 367 { 368 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 369 flash_sync_page(s, s->dirty_page); 370 s->dirty_page = newpage; 371 } 372 } 373 374 static inline 375 void flash_write8(Flash *s, uint64_t addr, uint8_t data) 376 { 377 int64_t page = addr / s->pi->page_size; 378 uint8_t prev = s->storage[s->cur_addr]; 379 380 if (!s->write_enable) { 381 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 382 } 383 384 if ((prev ^ data) & data) { 385 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8 386 " -> %" PRIx8 "\n", addr, prev, data); 387 } 388 389 if (s->pi->flags & WR_1) { 390 s->storage[s->cur_addr] = data; 391 } else { 392 s->storage[s->cur_addr] &= data; 393 } 394 395 flash_sync_dirty(s, page); 396 s->dirty_page = page; 397 } 398 399 static void complete_collecting_data(Flash *s) 400 { 401 s->cur_addr = s->data[0] << 16; 402 s->cur_addr |= s->data[1] << 8; 403 s->cur_addr |= s->data[2]; 404 405 s->state = STATE_IDLE; 406 407 switch (s->cmd_in_progress) { 408 case DPP: 409 case QPP: 410 case PP: 411 s->state = STATE_PAGE_PROGRAM; 412 break; 413 case READ: 414 case FAST_READ: 415 case DOR: 416 case QOR: 417 case DIOR: 418 case QIOR: 419 s->state = STATE_READ; 420 break; 421 case ERASE_4K: 422 case ERASE_32K: 423 case ERASE_SECTOR: 424 flash_erase(s, s->cur_addr, s->cmd_in_progress); 425 break; 426 case WRSR: 427 if (s->write_enable) { 428 s->write_enable = false; 429 } 430 break; 431 default: 432 break; 433 } 434 } 435 436 static void decode_new_cmd(Flash *s, uint32_t value) 437 { 438 s->cmd_in_progress = value; 439 DB_PRINT_L(0, "decoded new command:%x\n", value); 440 441 switch (value) { 442 443 case ERASE_4K: 444 case ERASE_32K: 445 case ERASE_SECTOR: 446 case READ: 447 case DPP: 448 case QPP: 449 case PP: 450 s->needed_bytes = 3; 451 s->pos = 0; 452 s->len = 0; 453 s->state = STATE_COLLECTING_DATA; 454 break; 455 456 case FAST_READ: 457 case DOR: 458 case QOR: 459 s->needed_bytes = 4; 460 s->pos = 0; 461 s->len = 0; 462 s->state = STATE_COLLECTING_DATA; 463 break; 464 465 case DIOR: 466 switch ((s->pi->jedec >> 16) & 0xFF) { 467 case JEDEC_WINBOND: 468 case JEDEC_SPANSION: 469 s->needed_bytes = 4; 470 break; 471 case JEDEC_NUMONYX: 472 default: 473 s->needed_bytes = 5; 474 } 475 s->pos = 0; 476 s->len = 0; 477 s->state = STATE_COLLECTING_DATA; 478 break; 479 480 case QIOR: 481 switch ((s->pi->jedec >> 16) & 0xFF) { 482 case JEDEC_WINBOND: 483 case JEDEC_SPANSION: 484 s->needed_bytes = 6; 485 break; 486 case JEDEC_NUMONYX: 487 default: 488 s->needed_bytes = 8; 489 } 490 s->pos = 0; 491 s->len = 0; 492 s->state = STATE_COLLECTING_DATA; 493 break; 494 495 case WRSR: 496 if (s->write_enable) { 497 s->needed_bytes = 1; 498 s->pos = 0; 499 s->len = 0; 500 s->state = STATE_COLLECTING_DATA; 501 } 502 break; 503 504 case WRDI: 505 s->write_enable = false; 506 break; 507 case WREN: 508 s->write_enable = true; 509 break; 510 511 case RDSR: 512 s->data[0] = (!!s->write_enable) << 1; 513 s->pos = 0; 514 s->len = 1; 515 s->state = STATE_READING_DATA; 516 break; 517 518 case JEDEC_READ: 519 DB_PRINT_L(0, "populated jedec code\n"); 520 s->data[0] = (s->pi->jedec >> 16) & 0xff; 521 s->data[1] = (s->pi->jedec >> 8) & 0xff; 522 s->data[2] = s->pi->jedec & 0xff; 523 if (s->pi->ext_jedec) { 524 s->data[3] = (s->pi->ext_jedec >> 8) & 0xff; 525 s->data[4] = s->pi->ext_jedec & 0xff; 526 s->len = 5; 527 } else { 528 s->len = 3; 529 } 530 s->pos = 0; 531 s->state = STATE_READING_DATA; 532 break; 533 534 case BULK_ERASE: 535 if (s->write_enable) { 536 DB_PRINT_L(0, "chip erase\n"); 537 flash_erase(s, 0, BULK_ERASE); 538 } else { 539 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 540 "protect!\n"); 541 } 542 break; 543 case NOP: 544 break; 545 default: 546 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 547 break; 548 } 549 } 550 551 static int m25p80_cs(SSISlave *ss, bool select) 552 { 553 Flash *s = M25P80(ss); 554 555 if (select) { 556 s->len = 0; 557 s->pos = 0; 558 s->state = STATE_IDLE; 559 flash_sync_dirty(s, -1); 560 } 561 562 DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); 563 564 return 0; 565 } 566 567 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) 568 { 569 Flash *s = M25P80(ss); 570 uint32_t r = 0; 571 572 switch (s->state) { 573 574 case STATE_PAGE_PROGRAM: 575 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n", 576 s->cur_addr, (uint8_t)tx); 577 flash_write8(s, s->cur_addr, (uint8_t)tx); 578 s->cur_addr++; 579 break; 580 581 case STATE_READ: 582 r = s->storage[s->cur_addr]; 583 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr, 584 (uint8_t)r); 585 s->cur_addr = (s->cur_addr + 1) % s->size; 586 break; 587 588 case STATE_COLLECTING_DATA: 589 s->data[s->len] = (uint8_t)tx; 590 s->len++; 591 592 if (s->len == s->needed_bytes) { 593 complete_collecting_data(s); 594 } 595 break; 596 597 case STATE_READING_DATA: 598 r = s->data[s->pos]; 599 s->pos++; 600 if (s->pos == s->len) { 601 s->pos = 0; 602 s->state = STATE_IDLE; 603 } 604 break; 605 606 default: 607 case STATE_IDLE: 608 decode_new_cmd(s, (uint8_t)tx); 609 break; 610 } 611 612 return r; 613 } 614 615 static int m25p80_init(SSISlave *ss) 616 { 617 DriveInfo *dinfo; 618 Flash *s = M25P80(ss); 619 M25P80Class *mc = M25P80_GET_CLASS(s); 620 621 s->pi = mc->pi; 622 623 s->size = s->pi->sector_size * s->pi->n_sectors; 624 s->dirty_page = -1; 625 626 /* FIXME use a qdev drive property instead of drive_get_next() */ 627 dinfo = drive_get_next(IF_MTD); 628 629 if (dinfo) { 630 DB_PRINT_L(0, "Binding to IF_MTD drive\n"); 631 s->blk = blk_by_legacy_dinfo(dinfo); 632 blk_attach_dev_nofail(s->blk, s); 633 634 s->storage = blk_blockalign(s->blk, s->size); 635 636 /* FIXME: Move to late init */ 637 if (blk_read(s->blk, 0, s->storage, 638 DIV_ROUND_UP(s->size, BDRV_SECTOR_SIZE))) { 639 fprintf(stderr, "Failed to initialize SPI flash!\n"); 640 return 1; 641 } 642 } else { 643 DB_PRINT_L(0, "No BDRV - binding to RAM\n"); 644 s->storage = blk_blockalign(NULL, s->size); 645 memset(s->storage, 0xFF, s->size); 646 } 647 648 return 0; 649 } 650 651 static void m25p80_pre_save(void *opaque) 652 { 653 flash_sync_dirty((Flash *)opaque, -1); 654 } 655 656 static const VMStateDescription vmstate_m25p80 = { 657 .name = "xilinx_spi", 658 .version_id = 1, 659 .minimum_version_id = 1, 660 .pre_save = m25p80_pre_save, 661 .fields = (VMStateField[]) { 662 VMSTATE_UINT8(state, Flash), 663 VMSTATE_UINT8_ARRAY(data, Flash, 16), 664 VMSTATE_UINT32(len, Flash), 665 VMSTATE_UINT32(pos, Flash), 666 VMSTATE_UINT8(needed_bytes, Flash), 667 VMSTATE_UINT8(cmd_in_progress, Flash), 668 VMSTATE_UINT64(cur_addr, Flash), 669 VMSTATE_BOOL(write_enable, Flash), 670 VMSTATE_END_OF_LIST() 671 } 672 }; 673 674 static void m25p80_class_init(ObjectClass *klass, void *data) 675 { 676 DeviceClass *dc = DEVICE_CLASS(klass); 677 SSISlaveClass *k = SSI_SLAVE_CLASS(klass); 678 M25P80Class *mc = M25P80_CLASS(klass); 679 680 k->init = m25p80_init; 681 k->transfer = m25p80_transfer8; 682 k->set_cs = m25p80_cs; 683 k->cs_polarity = SSI_CS_LOW; 684 dc->vmsd = &vmstate_m25p80; 685 mc->pi = data; 686 } 687 688 static const TypeInfo m25p80_info = { 689 .name = TYPE_M25P80, 690 .parent = TYPE_SSI_SLAVE, 691 .instance_size = sizeof(Flash), 692 .class_size = sizeof(M25P80Class), 693 .abstract = true, 694 }; 695 696 static void m25p80_register_types(void) 697 { 698 int i; 699 700 type_register_static(&m25p80_info); 701 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 702 TypeInfo ti = { 703 .name = known_devices[i].part_name, 704 .parent = TYPE_M25P80, 705 .class_init = m25p80_class_init, 706 .class_data = (void *)&known_devices[i], 707 }; 708 type_register(&ti); 709 } 710 } 711 712 type_init(m25p80_register_types) 713