1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/qdev-properties-system.h" 29 #include "hw/ssi/ssi.h" 30 #include "migration/vmstate.h" 31 #include "qemu/bitops.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 #include "qemu/error-report.h" 35 #include "qapi/error.h" 36 #include "trace.h" 37 #include "qom/object.h" 38 #include "m25p80_sfdp.h" 39 40 /* 16 MiB max in 3 byte address mode */ 41 #define MAX_3BYTES_SIZE 0x1000000 42 #define SPI_NOR_MAX_ID_LEN 6 43 44 /* Fields for FlashPartInfo->flags */ 45 enum spi_flash_option_flags { 46 ER_4K = BIT(0), 47 ER_32K = BIT(1), 48 EEPROM = BIT(2), 49 HAS_SR_TB = BIT(3), 50 HAS_SR_BP3_BIT6 = BIT(4), 51 }; 52 53 typedef struct FlashPartInfo { 54 const char *part_name; 55 /* 56 * This array stores the ID bytes. 57 * The first three bytes are the JEDIC ID. 58 * JEDEC ID zero means "no ID" (mostly older chips). 59 */ 60 uint8_t id[SPI_NOR_MAX_ID_LEN]; 61 uint8_t id_len; 62 /* there is confusion between manufacturers as to what a sector is. In this 63 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 64 * command (opcode 0xd8). 65 */ 66 uint32_t sector_size; 67 uint32_t n_sectors; 68 uint32_t page_size; 69 uint16_t flags; 70 /* 71 * Big sized spi nor are often stacked devices, thus sometime 72 * replace chip erase with die erase. 73 * This field inform how many die is in the chip. 74 */ 75 uint8_t die_cnt; 76 uint8_t (*sfdp_read)(uint32_t sfdp_addr); 77 } FlashPartInfo; 78 79 /* adapted from linux */ 80 /* Used when the "_ext_id" is two bytes at most */ 81 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 82 .part_name = _part_name,\ 83 .id = {\ 84 ((_jedec_id) >> 16) & 0xff,\ 85 ((_jedec_id) >> 8) & 0xff,\ 86 (_jedec_id) & 0xff,\ 87 ((_ext_id) >> 8) & 0xff,\ 88 (_ext_id) & 0xff,\ 89 },\ 90 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 91 .sector_size = (_sector_size),\ 92 .n_sectors = (_n_sectors),\ 93 .page_size = 256,\ 94 .flags = (_flags),\ 95 .die_cnt = 0 96 97 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 98 .part_name = _part_name,\ 99 .id = {\ 100 ((_jedec_id) >> 16) & 0xff,\ 101 ((_jedec_id) >> 8) & 0xff,\ 102 (_jedec_id) & 0xff,\ 103 ((_ext_id) >> 16) & 0xff,\ 104 ((_ext_id) >> 8) & 0xff,\ 105 (_ext_id) & 0xff,\ 106 },\ 107 .id_len = 6,\ 108 .sector_size = (_sector_size),\ 109 .n_sectors = (_n_sectors),\ 110 .page_size = 256,\ 111 .flags = (_flags),\ 112 .die_cnt = 0 113 114 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ 115 _flags, _die_cnt)\ 116 .part_name = _part_name,\ 117 .id = {\ 118 ((_jedec_id) >> 16) & 0xff,\ 119 ((_jedec_id) >> 8) & 0xff,\ 120 (_jedec_id) & 0xff,\ 121 ((_ext_id) >> 8) & 0xff,\ 122 (_ext_id) & 0xff,\ 123 },\ 124 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 125 .sector_size = (_sector_size),\ 126 .n_sectors = (_n_sectors),\ 127 .page_size = 256,\ 128 .flags = (_flags),\ 129 .die_cnt = _die_cnt 130 131 #define JEDEC_NUMONYX 0x20 132 #define JEDEC_WINBOND 0xEF 133 #define JEDEC_SPANSION 0x01 134 135 /* Numonyx (Micron) Configuration register macros */ 136 #define VCFG_DUMMY 0x1 137 #define VCFG_WRAP_SEQUENTIAL 0x2 138 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 139 #define NVCFG_XIP_MODE_MASK (7 << 9) 140 #define VCFG_XIP_MODE_DISABLED (1 << 3) 141 #define CFG_DUMMY_CLK_LEN 4 142 #define NVCFG_DUMMY_CLK_POS 12 143 #define VCFG_DUMMY_CLK_POS 4 144 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 145 #define EVCFG_VPP_ACCELERATOR (1 << 3) 146 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 147 #define NVCFG_DUAL_IO_MASK (1 << 2) 148 #define EVCFG_DUAL_IO_DISABLED (1 << 6) 149 #define NVCFG_QUAD_IO_MASK (1 << 3) 150 #define EVCFG_QUAD_IO_DISABLED (1 << 7) 151 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 152 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 153 154 /* Numonyx (Micron) Flag Status Register macros */ 155 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 156 #define FSR_FLASH_READY (1 << 7) 157 158 /* Spansion configuration registers macros. */ 159 #define SPANSION_QUAD_CFG_POS 0 160 #define SPANSION_QUAD_CFG_LEN 1 161 #define SPANSION_DUMMY_CLK_POS 0 162 #define SPANSION_DUMMY_CLK_LEN 4 163 #define SPANSION_ADDR_LEN_POS 7 164 #define SPANSION_ADDR_LEN_LEN 1 165 166 /* 167 * Spansion read mode command length in bytes, 168 * the mode is currently not supported. 169 */ 170 171 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 172 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 173 174 static const FlashPartInfo known_devices[] = { 175 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 176 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 177 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 178 179 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 180 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 181 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 182 183 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 184 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 185 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 186 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 187 188 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 189 190 /* Atmel EEPROMS - it is assumed, that don't care bit in command 191 * is set to 0. Block protection is not supported. 192 */ 193 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 194 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 195 196 /* EON -- en25xxx */ 197 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 198 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 199 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 200 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 201 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 202 203 /* GigaDevice */ 204 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 205 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 206 207 /* Intel/Numonyx -- xxxs33b */ 208 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 209 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 210 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 211 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 212 213 /* ISSI */ 214 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, 215 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, 216 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, 217 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, 218 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, 219 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, 220 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) }, 221 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) }, 222 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) }, 223 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) }, 224 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K), 225 .sfdp_read = m25p80_sfdp_is25wp256 }, 226 227 /* Macronix */ 228 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 229 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 230 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 231 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 232 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 233 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 234 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 235 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 236 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 237 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e }, 238 { INFO6("mx25l25635f", 0xc22019, 0xc22019, 64 << 10, 512, 239 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f }, 240 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 241 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 242 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 243 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 244 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K), 245 .sfdp_read = m25p80_sfdp_mx66l1g45g }, 246 247 /* Micron */ 248 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 249 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 250 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 251 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 252 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 253 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 254 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 255 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K), 256 .sfdp_read = m25p80_sfdp_n25q256a }, 257 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, 258 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 259 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 260 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, 261 ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB), 262 .sfdp_read = m25p80_sfdp_n25q256a }, 263 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 264 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, 265 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, 266 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024, 267 ER_4K | ER_32K, 2) }, 268 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 269 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 270 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 271 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 272 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 273 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 274 275 /* Spansion -- single (large) sector size only, at least 276 * for the chips listed here (without boot sectors). 277 */ 278 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 279 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 280 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 281 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 282 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 283 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 284 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 285 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 286 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 287 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 288 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 289 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 290 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 291 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 292 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 293 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 294 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 295 296 /* Spansion -- boot sectors support */ 297 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 298 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 299 300 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 301 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 302 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 303 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 304 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 305 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 306 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 307 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 308 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 309 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 310 311 /* ST Microelectronics -- newer production may have feature updates */ 312 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 313 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 314 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 315 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 316 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 317 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 318 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 319 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 320 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 321 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 322 323 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 324 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 325 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 326 327 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 328 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 329 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 330 331 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 332 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 333 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 334 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 335 336 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 337 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 338 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 339 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 340 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 341 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 342 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 343 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 344 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 345 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 346 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 347 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 348 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 349 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K), 350 .sfdp_read = m25p80_sfdp_w25q256 }, 351 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K), 352 .sfdp_read = m25p80_sfdp_w25q512jv }, 353 { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K), 354 .sfdp_read = m25p80_sfdp_w25q01jvq }, 355 }; 356 357 typedef enum { 358 NOP = 0, 359 WRSR = 0x1, 360 WRDI = 0x4, 361 RDSR = 0x5, 362 WREN = 0x6, 363 BRRD = 0x16, 364 BRWR = 0x17, 365 JEDEC_READ = 0x9f, 366 BULK_ERASE_60 = 0x60, 367 BULK_ERASE = 0xc7, 368 READ_FSR = 0x70, 369 RDCR = 0x15, 370 RDSFDP = 0x5a, 371 372 READ = 0x03, 373 READ4 = 0x13, 374 FAST_READ = 0x0b, 375 FAST_READ4 = 0x0c, 376 DOR = 0x3b, 377 DOR4 = 0x3c, 378 QOR = 0x6b, 379 QOR4 = 0x6c, 380 DIOR = 0xbb, 381 DIOR4 = 0xbc, 382 QIOR = 0xeb, 383 QIOR4 = 0xec, 384 385 PP = 0x02, 386 PP4 = 0x12, 387 PP4_4 = 0x3e, 388 DPP = 0xa2, 389 QPP = 0x32, 390 QPP_4 = 0x34, 391 RDID_90 = 0x90, 392 RDID_AB = 0xab, 393 AAI_WP = 0xad, 394 395 ERASE_4K = 0x20, 396 ERASE4_4K = 0x21, 397 ERASE_32K = 0x52, 398 ERASE4_32K = 0x5c, 399 ERASE_SECTOR = 0xd8, 400 ERASE4_SECTOR = 0xdc, 401 402 EN_4BYTE_ADDR = 0xB7, 403 EX_4BYTE_ADDR = 0xE9, 404 405 EXTEND_ADDR_READ = 0xC8, 406 EXTEND_ADDR_WRITE = 0xC5, 407 408 RESET_ENABLE = 0x66, 409 RESET_MEMORY = 0x99, 410 411 /* 412 * Micron: 0x35 - enable QPI 413 * Spansion: 0x35 - read control register 414 */ 415 RDCR_EQIO = 0x35, 416 RSTQIO = 0xf5, 417 418 RNVCR = 0xB5, 419 WNVCR = 0xB1, 420 421 RVCR = 0x85, 422 WVCR = 0x81, 423 424 REVCR = 0x65, 425 WEVCR = 0x61, 426 427 DIE_ERASE = 0xC4, 428 } FlashCMD; 429 430 typedef enum { 431 STATE_IDLE, 432 STATE_PAGE_PROGRAM, 433 STATE_READ, 434 STATE_COLLECTING_DATA, 435 STATE_COLLECTING_VAR_LEN_DATA, 436 STATE_READING_DATA, 437 STATE_READING_SFDP, 438 } CMDState; 439 440 typedef enum { 441 MAN_SPANSION, 442 MAN_MACRONIX, 443 MAN_NUMONYX, 444 MAN_WINBOND, 445 MAN_SST, 446 MAN_ISSI, 447 MAN_GENERIC, 448 } Manufacturer; 449 450 typedef enum { 451 MODE_STD = 0, 452 MODE_DIO = 1, 453 MODE_QIO = 2 454 } SPIMode; 455 456 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 457 458 struct Flash { 459 SSIPeripheral parent_obj; 460 461 BlockBackend *blk; 462 463 uint8_t *storage; 464 uint32_t size; 465 int page_size; 466 467 uint8_t state; 468 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 469 uint32_t len; 470 uint32_t pos; 471 bool data_read_loop; 472 uint8_t needed_bytes; 473 uint8_t cmd_in_progress; 474 uint32_t cur_addr; 475 uint32_t nonvolatile_cfg; 476 /* Configuration register for Macronix */ 477 uint32_t volatile_cfg; 478 uint32_t enh_volatile_cfg; 479 /* Spansion cfg registers. */ 480 uint8_t spansion_cr1nv; 481 uint8_t spansion_cr2nv; 482 uint8_t spansion_cr3nv; 483 uint8_t spansion_cr4nv; 484 uint8_t spansion_cr1v; 485 uint8_t spansion_cr2v; 486 uint8_t spansion_cr3v; 487 uint8_t spansion_cr4v; 488 bool wp_level; 489 bool write_enable; 490 bool four_bytes_address_mode; 491 bool reset_enable; 492 bool quad_enable; 493 bool aai_enable; 494 bool block_protect0; 495 bool block_protect1; 496 bool block_protect2; 497 bool block_protect3; 498 bool top_bottom_bit; 499 bool status_register_write_disabled; 500 uint8_t ear; 501 502 int64_t dirty_page; 503 504 const FlashPartInfo *pi; 505 506 }; 507 508 struct M25P80Class { 509 SSIPeripheralClass parent_class; 510 FlashPartInfo *pi; 511 }; 512 513 #define TYPE_M25P80 "m25p80-generic" 514 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) 515 516 static inline Manufacturer get_man(Flash *s) 517 { 518 switch (s->pi->id[0]) { 519 case 0x20: 520 return MAN_NUMONYX; 521 case 0xEF: 522 return MAN_WINBOND; 523 case 0x01: 524 return MAN_SPANSION; 525 case 0xC2: 526 return MAN_MACRONIX; 527 case 0xBF: 528 return MAN_SST; 529 case 0x9D: 530 return MAN_ISSI; 531 default: 532 return MAN_GENERIC; 533 } 534 } 535 536 static void blk_sync_complete(void *opaque, int ret) 537 { 538 QEMUIOVector *iov = opaque; 539 540 qemu_iovec_destroy(iov); 541 g_free(iov); 542 543 /* do nothing. Masters do not directly interact with the backing store, 544 * only the working copy so no mutexing required. 545 */ 546 } 547 548 static void flash_sync_page(Flash *s, int page) 549 { 550 QEMUIOVector *iov; 551 552 if (!s->blk || !blk_is_writable(s->blk)) { 553 return; 554 } 555 556 iov = g_new(QEMUIOVector, 1); 557 qemu_iovec_init(iov, 1); 558 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 559 s->pi->page_size); 560 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 561 blk_sync_complete, iov); 562 } 563 564 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 565 { 566 QEMUIOVector *iov; 567 568 if (!s->blk || !blk_is_writable(s->blk)) { 569 return; 570 } 571 572 assert(!(len % BDRV_SECTOR_SIZE)); 573 iov = g_new(QEMUIOVector, 1); 574 qemu_iovec_init(iov, 1); 575 qemu_iovec_add(iov, s->storage + off, len); 576 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 577 } 578 579 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 580 { 581 uint32_t len; 582 uint8_t capa_to_assert = 0; 583 584 switch (cmd) { 585 case ERASE_4K: 586 case ERASE4_4K: 587 len = 4 * KiB; 588 capa_to_assert = ER_4K; 589 break; 590 case ERASE_32K: 591 case ERASE4_32K: 592 len = 32 * KiB; 593 capa_to_assert = ER_32K; 594 break; 595 case ERASE_SECTOR: 596 case ERASE4_SECTOR: 597 len = s->pi->sector_size; 598 break; 599 case BULK_ERASE: 600 len = s->size; 601 break; 602 case DIE_ERASE: 603 if (s->pi->die_cnt) { 604 len = s->size / s->pi->die_cnt; 605 offset = offset & (~(len - 1)); 606 } else { 607 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" 608 " by device\n"); 609 return; 610 } 611 break; 612 default: 613 abort(); 614 } 615 616 trace_m25p80_flash_erase(s, offset, len); 617 618 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 619 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 620 " device\n", len); 621 } 622 623 if (!s->write_enable) { 624 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 625 return; 626 } 627 memset(s->storage + offset, 0xff, len); 628 flash_sync_area(s, offset, len); 629 } 630 631 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 632 { 633 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 634 flash_sync_page(s, s->dirty_page); 635 s->dirty_page = newpage; 636 } 637 } 638 639 static inline 640 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 641 { 642 uint32_t page = addr / s->pi->page_size; 643 uint8_t prev = s->storage[s->cur_addr]; 644 uint32_t block_protect_value = (s->block_protect3 << 3) | 645 (s->block_protect2 << 2) | 646 (s->block_protect1 << 1) | 647 (s->block_protect0 << 0); 648 649 if (!s->write_enable) { 650 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 651 return; 652 } 653 654 if (block_protect_value > 0) { 655 uint32_t num_protected_sectors = 1 << (block_protect_value - 1); 656 uint32_t sector = addr / s->pi->sector_size; 657 658 /* top_bottom_bit == 0 means TOP */ 659 if (!s->top_bottom_bit) { 660 if (s->pi->n_sectors <= sector + num_protected_sectors) { 661 qemu_log_mask(LOG_GUEST_ERROR, 662 "M25P80: write with write protect!\n"); 663 return; 664 } 665 } else { 666 if (sector < num_protected_sectors) { 667 qemu_log_mask(LOG_GUEST_ERROR, 668 "M25P80: write with write protect!\n"); 669 return; 670 } 671 } 672 } 673 674 if ((prev ^ data) & data) { 675 trace_m25p80_programming_zero_to_one(s, addr, prev, data); 676 } 677 678 if (s->pi->flags & EEPROM) { 679 s->storage[s->cur_addr] = data; 680 } else { 681 s->storage[s->cur_addr] &= data; 682 } 683 684 flash_sync_dirty(s, page); 685 s->dirty_page = page; 686 } 687 688 static inline int get_addr_length(Flash *s) 689 { 690 /* check if eeprom is in use */ 691 if (s->pi->flags == EEPROM) { 692 return 2; 693 } 694 695 switch (s->cmd_in_progress) { 696 case RDSFDP: 697 return 3; 698 case PP4: 699 case PP4_4: 700 case QPP_4: 701 case READ4: 702 case QIOR4: 703 case ERASE4_4K: 704 case ERASE4_32K: 705 case ERASE4_SECTOR: 706 case FAST_READ4: 707 case DOR4: 708 case QOR4: 709 case DIOR4: 710 return 4; 711 default: 712 return s->four_bytes_address_mode ? 4 : 3; 713 } 714 } 715 716 static void complete_collecting_data(Flash *s) 717 { 718 int i, n; 719 720 n = get_addr_length(s); 721 s->cur_addr = (n == 3 ? s->ear : 0); 722 for (i = 0; i < n; ++i) { 723 s->cur_addr <<= 8; 724 s->cur_addr |= s->data[i]; 725 } 726 727 s->cur_addr &= s->size - 1; 728 729 s->state = STATE_IDLE; 730 731 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, 732 s->cur_addr); 733 734 switch (s->cmd_in_progress) { 735 case DPP: 736 case QPP: 737 case QPP_4: 738 case PP: 739 case PP4: 740 case PP4_4: 741 s->state = STATE_PAGE_PROGRAM; 742 break; 743 case AAI_WP: 744 /* AAI programming starts from the even address */ 745 s->cur_addr &= ~BIT(0); 746 s->state = STATE_PAGE_PROGRAM; 747 break; 748 case READ: 749 case READ4: 750 case FAST_READ: 751 case FAST_READ4: 752 case DOR: 753 case DOR4: 754 case QOR: 755 case QOR4: 756 case DIOR: 757 case DIOR4: 758 case QIOR: 759 case QIOR4: 760 s->state = STATE_READ; 761 break; 762 case ERASE_4K: 763 case ERASE4_4K: 764 case ERASE_32K: 765 case ERASE4_32K: 766 case ERASE_SECTOR: 767 case ERASE4_SECTOR: 768 case DIE_ERASE: 769 flash_erase(s, s->cur_addr, s->cmd_in_progress); 770 break; 771 case WRSR: 772 s->status_register_write_disabled = extract32(s->data[0], 7, 1); 773 s->block_protect0 = extract32(s->data[0], 2, 1); 774 s->block_protect1 = extract32(s->data[0], 3, 1); 775 s->block_protect2 = extract32(s->data[0], 4, 1); 776 if (s->pi->flags & HAS_SR_TB) { 777 s->top_bottom_bit = extract32(s->data[0], 5, 1); 778 } 779 if (s->pi->flags & HAS_SR_BP3_BIT6) { 780 s->block_protect3 = extract32(s->data[0], 6, 1); 781 } 782 783 switch (get_man(s)) { 784 case MAN_SPANSION: 785 s->quad_enable = !!(s->data[1] & 0x02); 786 break; 787 case MAN_ISSI: 788 s->quad_enable = extract32(s->data[0], 6, 1); 789 break; 790 case MAN_MACRONIX: 791 s->quad_enable = extract32(s->data[0], 6, 1); 792 if (s->len > 1) { 793 s->volatile_cfg = s->data[1]; 794 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 795 } 796 break; 797 default: 798 break; 799 } 800 if (s->write_enable) { 801 s->write_enable = false; 802 } 803 break; 804 case BRWR: 805 case EXTEND_ADDR_WRITE: 806 s->ear = s->data[0]; 807 break; 808 case WNVCR: 809 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 810 break; 811 case WVCR: 812 s->volatile_cfg = s->data[0]; 813 break; 814 case WEVCR: 815 s->enh_volatile_cfg = s->data[0]; 816 break; 817 case RDID_90: 818 case RDID_AB: 819 if (get_man(s) == MAN_SST) { 820 if (s->cur_addr <= 1) { 821 if (s->cur_addr) { 822 s->data[0] = s->pi->id[2]; 823 s->data[1] = s->pi->id[0]; 824 } else { 825 s->data[0] = s->pi->id[0]; 826 s->data[1] = s->pi->id[2]; 827 } 828 s->pos = 0; 829 s->len = 2; 830 s->data_read_loop = true; 831 s->state = STATE_READING_DATA; 832 } else { 833 qemu_log_mask(LOG_GUEST_ERROR, 834 "M25P80: Invalid read id address\n"); 835 } 836 } else { 837 qemu_log_mask(LOG_GUEST_ERROR, 838 "M25P80: Read id (command 0x90/0xAB) is not supported" 839 " by device\n"); 840 } 841 break; 842 843 case RDSFDP: 844 s->state = STATE_READING_SFDP; 845 break; 846 847 default: 848 break; 849 } 850 } 851 852 static void reset_memory(Flash *s) 853 { 854 s->cmd_in_progress = NOP; 855 s->cur_addr = 0; 856 s->ear = 0; 857 s->four_bytes_address_mode = false; 858 s->len = 0; 859 s->needed_bytes = 0; 860 s->pos = 0; 861 s->state = STATE_IDLE; 862 s->write_enable = false; 863 s->reset_enable = false; 864 s->quad_enable = false; 865 s->aai_enable = false; 866 867 switch (get_man(s)) { 868 case MAN_NUMONYX: 869 s->volatile_cfg = 0; 870 s->volatile_cfg |= VCFG_DUMMY; 871 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 872 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 873 == NVCFG_XIP_MODE_DISABLED) { 874 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; 875 } 876 s->volatile_cfg |= deposit32(s->volatile_cfg, 877 VCFG_DUMMY_CLK_POS, 878 CFG_DUMMY_CLK_LEN, 879 extract32(s->nonvolatile_cfg, 880 NVCFG_DUMMY_CLK_POS, 881 CFG_DUMMY_CLK_LEN) 882 ); 883 884 s->enh_volatile_cfg = 0; 885 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; 886 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 887 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 888 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 889 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; 890 } 891 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 892 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; 893 } 894 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 895 s->four_bytes_address_mode = true; 896 } 897 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 898 s->ear = s->size / MAX_3BYTES_SIZE - 1; 899 } 900 break; 901 case MAN_MACRONIX: 902 s->volatile_cfg = 0x7; 903 break; 904 case MAN_SPANSION: 905 s->spansion_cr1v = s->spansion_cr1nv; 906 s->spansion_cr2v = s->spansion_cr2nv; 907 s->spansion_cr3v = s->spansion_cr3nv; 908 s->spansion_cr4v = s->spansion_cr4nv; 909 s->quad_enable = extract32(s->spansion_cr1v, 910 SPANSION_QUAD_CFG_POS, 911 SPANSION_QUAD_CFG_LEN 912 ); 913 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 914 SPANSION_ADDR_LEN_POS, 915 SPANSION_ADDR_LEN_LEN 916 ); 917 break; 918 default: 919 break; 920 } 921 922 trace_m25p80_reset_done(s); 923 } 924 925 static uint8_t numonyx_mode(Flash *s) 926 { 927 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { 928 return MODE_QIO; 929 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { 930 return MODE_DIO; 931 } else { 932 return MODE_STD; 933 } 934 } 935 936 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s) 937 { 938 uint8_t num_dummies; 939 uint8_t mode; 940 assert(get_man(s) == MAN_NUMONYX); 941 942 mode = numonyx_mode(s); 943 num_dummies = extract32(s->volatile_cfg, 4, 4); 944 945 if (num_dummies == 0x0 || num_dummies == 0xf) { 946 switch (s->cmd_in_progress) { 947 case QIOR: 948 case QIOR4: 949 num_dummies = 10; 950 break; 951 default: 952 num_dummies = (mode == MODE_QIO) ? 10 : 8; 953 break; 954 } 955 } 956 957 return num_dummies; 958 } 959 960 static void decode_fast_read_cmd(Flash *s) 961 { 962 s->needed_bytes = get_addr_length(s); 963 switch (get_man(s)) { 964 /* Dummy cycles - modeled with bytes writes instead of bits */ 965 case MAN_SST: 966 s->needed_bytes += 1; 967 break; 968 case MAN_WINBOND: 969 s->needed_bytes += 8; 970 break; 971 case MAN_NUMONYX: 972 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 973 break; 974 case MAN_MACRONIX: 975 if (extract32(s->volatile_cfg, 6, 2) == 1) { 976 s->needed_bytes += 6; 977 } else { 978 s->needed_bytes += 8; 979 } 980 break; 981 case MAN_SPANSION: 982 s->needed_bytes += extract32(s->spansion_cr2v, 983 SPANSION_DUMMY_CLK_POS, 984 SPANSION_DUMMY_CLK_LEN 985 ); 986 break; 987 case MAN_ISSI: 988 /* 989 * The Fast Read instruction code is followed by address bytes and 990 * dummy cycles, transmitted via the SI line. 991 * 992 * The number of dummy cycles is configurable but this is currently 993 * unmodeled, hence the default value 8 is used. 994 * 995 * QPI (Quad Peripheral Interface) mode has different default value 996 * of dummy cycles, but this is unsupported at the time being. 997 */ 998 s->needed_bytes += 1; 999 break; 1000 default: 1001 break; 1002 } 1003 s->pos = 0; 1004 s->len = 0; 1005 s->state = STATE_COLLECTING_DATA; 1006 } 1007 1008 static void decode_dio_read_cmd(Flash *s) 1009 { 1010 s->needed_bytes = get_addr_length(s); 1011 /* Dummy cycles modeled with bytes writes instead of bits */ 1012 switch (get_man(s)) { 1013 case MAN_WINBOND: 1014 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1015 break; 1016 case MAN_SPANSION: 1017 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1018 s->needed_bytes += extract32(s->spansion_cr2v, 1019 SPANSION_DUMMY_CLK_POS, 1020 SPANSION_DUMMY_CLK_LEN 1021 ); 1022 break; 1023 case MAN_NUMONYX: 1024 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1025 break; 1026 case MAN_MACRONIX: 1027 switch (extract32(s->volatile_cfg, 6, 2)) { 1028 case 1: 1029 s->needed_bytes += 6; 1030 break; 1031 case 2: 1032 s->needed_bytes += 8; 1033 break; 1034 default: 1035 s->needed_bytes += 4; 1036 break; 1037 } 1038 break; 1039 case MAN_ISSI: 1040 /* 1041 * The Fast Read Dual I/O instruction code is followed by address bytes 1042 * and dummy cycles, transmitted via the IO1 and IO0 line. 1043 * 1044 * The number of dummy cycles is configurable but this is currently 1045 * unmodeled, hence the default value 4 is used. 1046 */ 1047 s->needed_bytes += 1; 1048 break; 1049 default: 1050 break; 1051 } 1052 s->pos = 0; 1053 s->len = 0; 1054 s->state = STATE_COLLECTING_DATA; 1055 } 1056 1057 static void decode_qio_read_cmd(Flash *s) 1058 { 1059 s->needed_bytes = get_addr_length(s); 1060 /* Dummy cycles modeled with bytes writes instead of bits */ 1061 switch (get_man(s)) { 1062 case MAN_WINBOND: 1063 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1064 s->needed_bytes += 4; 1065 break; 1066 case MAN_SPANSION: 1067 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1068 s->needed_bytes += extract32(s->spansion_cr2v, 1069 SPANSION_DUMMY_CLK_POS, 1070 SPANSION_DUMMY_CLK_LEN 1071 ); 1072 break; 1073 case MAN_NUMONYX: 1074 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1075 break; 1076 case MAN_MACRONIX: 1077 switch (extract32(s->volatile_cfg, 6, 2)) { 1078 case 1: 1079 s->needed_bytes += 4; 1080 break; 1081 case 2: 1082 s->needed_bytes += 8; 1083 break; 1084 default: 1085 s->needed_bytes += 6; 1086 break; 1087 } 1088 break; 1089 case MAN_ISSI: 1090 /* 1091 * The Fast Read Quad I/O instruction code is followed by address bytes 1092 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line. 1093 * 1094 * The number of dummy cycles is configurable but this is currently 1095 * unmodeled, hence the default value 6 is used. 1096 * 1097 * QPI (Quad Peripheral Interface) mode has different default value 1098 * of dummy cycles, but this is unsupported at the time being. 1099 */ 1100 s->needed_bytes += 3; 1101 break; 1102 default: 1103 break; 1104 } 1105 s->pos = 0; 1106 s->len = 0; 1107 s->state = STATE_COLLECTING_DATA; 1108 } 1109 1110 static bool is_valid_aai_cmd(uint32_t cmd) 1111 { 1112 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR; 1113 } 1114 1115 static void decode_new_cmd(Flash *s, uint32_t value) 1116 { 1117 int i; 1118 1119 s->cmd_in_progress = value; 1120 trace_m25p80_command_decoded(s, value); 1121 1122 if (value != RESET_MEMORY) { 1123 s->reset_enable = false; 1124 } 1125 1126 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) { 1127 qemu_log_mask(LOG_GUEST_ERROR, 1128 "M25P80: Invalid cmd within AAI programming sequence"); 1129 } 1130 1131 switch (value) { 1132 1133 case ERASE_4K: 1134 case ERASE4_4K: 1135 case ERASE_32K: 1136 case ERASE4_32K: 1137 case ERASE_SECTOR: 1138 case ERASE4_SECTOR: 1139 case PP: 1140 case PP4: 1141 case DIE_ERASE: 1142 case RDID_90: 1143 case RDID_AB: 1144 s->needed_bytes = get_addr_length(s); 1145 s->pos = 0; 1146 s->len = 0; 1147 s->state = STATE_COLLECTING_DATA; 1148 break; 1149 case READ: 1150 case READ4: 1151 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1152 s->needed_bytes = get_addr_length(s); 1153 s->pos = 0; 1154 s->len = 0; 1155 s->state = STATE_COLLECTING_DATA; 1156 } else { 1157 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1158 "DIO or QIO mode\n", s->cmd_in_progress); 1159 } 1160 break; 1161 case DPP: 1162 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1163 s->needed_bytes = get_addr_length(s); 1164 s->pos = 0; 1165 s->len = 0; 1166 s->state = STATE_COLLECTING_DATA; 1167 } else { 1168 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1169 "QIO mode\n", s->cmd_in_progress); 1170 } 1171 break; 1172 case QPP: 1173 case QPP_4: 1174 case PP4_4: 1175 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1176 s->needed_bytes = get_addr_length(s); 1177 s->pos = 0; 1178 s->len = 0; 1179 s->state = STATE_COLLECTING_DATA; 1180 } else { 1181 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1182 "DIO mode\n", s->cmd_in_progress); 1183 } 1184 break; 1185 1186 case FAST_READ: 1187 case FAST_READ4: 1188 decode_fast_read_cmd(s); 1189 break; 1190 case DOR: 1191 case DOR4: 1192 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1193 decode_fast_read_cmd(s); 1194 } else { 1195 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1196 "QIO mode\n", s->cmd_in_progress); 1197 } 1198 break; 1199 case QOR: 1200 case QOR4: 1201 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1202 decode_fast_read_cmd(s); 1203 } else { 1204 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1205 "DIO mode\n", s->cmd_in_progress); 1206 } 1207 break; 1208 1209 case DIOR: 1210 case DIOR4: 1211 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1212 decode_dio_read_cmd(s); 1213 } else { 1214 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1215 "QIO mode\n", s->cmd_in_progress); 1216 } 1217 break; 1218 1219 case QIOR: 1220 case QIOR4: 1221 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1222 decode_qio_read_cmd(s); 1223 } else { 1224 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1225 "DIO mode\n", s->cmd_in_progress); 1226 } 1227 break; 1228 1229 case WRSR: 1230 /* 1231 * If WP# is low and status_register_write_disabled is high, 1232 * status register writes are disabled. 1233 * This is also called "hardware protected mode" (HPM). All other 1234 * combinations of the two states are called "software protected mode" 1235 * (SPM), and status register writes are permitted. 1236 */ 1237 if ((s->wp_level == 0 && s->status_register_write_disabled) 1238 || !s->write_enable) { 1239 qemu_log_mask(LOG_GUEST_ERROR, 1240 "M25P80: Status register write is disabled!\n"); 1241 break; 1242 } 1243 1244 switch (get_man(s)) { 1245 case MAN_SPANSION: 1246 s->needed_bytes = 2; 1247 s->state = STATE_COLLECTING_DATA; 1248 break; 1249 case MAN_MACRONIX: 1250 s->needed_bytes = 2; 1251 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1252 break; 1253 default: 1254 s->needed_bytes = 1; 1255 s->state = STATE_COLLECTING_DATA; 1256 } 1257 s->pos = 0; 1258 break; 1259 1260 case WRDI: 1261 s->write_enable = false; 1262 if (get_man(s) == MAN_SST) { 1263 s->aai_enable = false; 1264 } 1265 break; 1266 case WREN: 1267 s->write_enable = true; 1268 break; 1269 1270 case RDSR: 1271 s->data[0] = (!!s->write_enable) << 1; 1272 s->data[0] |= (!!s->status_register_write_disabled) << 7; 1273 s->data[0] |= (!!s->block_protect0) << 2; 1274 s->data[0] |= (!!s->block_protect1) << 3; 1275 s->data[0] |= (!!s->block_protect2) << 4; 1276 if (s->pi->flags & HAS_SR_TB) { 1277 s->data[0] |= (!!s->top_bottom_bit) << 5; 1278 } 1279 if (s->pi->flags & HAS_SR_BP3_BIT6) { 1280 s->data[0] |= (!!s->block_protect3) << 6; 1281 } 1282 1283 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) { 1284 s->data[0] |= (!!s->quad_enable) << 6; 1285 } 1286 if (get_man(s) == MAN_SST) { 1287 s->data[0] |= (!!s->aai_enable) << 6; 1288 } 1289 1290 s->pos = 0; 1291 s->len = 1; 1292 s->data_read_loop = true; 1293 s->state = STATE_READING_DATA; 1294 break; 1295 1296 case READ_FSR: 1297 s->data[0] = FSR_FLASH_READY; 1298 if (s->four_bytes_address_mode) { 1299 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 1300 } 1301 s->pos = 0; 1302 s->len = 1; 1303 s->data_read_loop = true; 1304 s->state = STATE_READING_DATA; 1305 break; 1306 1307 case JEDEC_READ: 1308 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1309 trace_m25p80_populated_jedec(s); 1310 for (i = 0; i < s->pi->id_len; i++) { 1311 s->data[i] = s->pi->id[i]; 1312 } 1313 for (; i < SPI_NOR_MAX_ID_LEN; i++) { 1314 s->data[i] = 0; 1315 } 1316 1317 s->len = SPI_NOR_MAX_ID_LEN; 1318 s->pos = 0; 1319 s->state = STATE_READING_DATA; 1320 } else { 1321 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read " 1322 "in DIO or QIO mode\n"); 1323 } 1324 break; 1325 1326 case RDCR: 1327 s->data[0] = s->volatile_cfg & 0xFF; 1328 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 1329 s->pos = 0; 1330 s->len = 1; 1331 s->state = STATE_READING_DATA; 1332 break; 1333 1334 case BULK_ERASE_60: 1335 case BULK_ERASE: 1336 if (s->write_enable) { 1337 trace_m25p80_chip_erase(s); 1338 flash_erase(s, 0, BULK_ERASE); 1339 } else { 1340 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 1341 "protect!\n"); 1342 } 1343 break; 1344 case NOP: 1345 break; 1346 case EN_4BYTE_ADDR: 1347 s->four_bytes_address_mode = true; 1348 break; 1349 case EX_4BYTE_ADDR: 1350 s->four_bytes_address_mode = false; 1351 break; 1352 case BRRD: 1353 case EXTEND_ADDR_READ: 1354 s->data[0] = s->ear; 1355 s->pos = 0; 1356 s->len = 1; 1357 s->state = STATE_READING_DATA; 1358 break; 1359 case BRWR: 1360 case EXTEND_ADDR_WRITE: 1361 if (s->write_enable) { 1362 s->needed_bytes = 1; 1363 s->pos = 0; 1364 s->len = 0; 1365 s->state = STATE_COLLECTING_DATA; 1366 } 1367 break; 1368 case RNVCR: 1369 s->data[0] = s->nonvolatile_cfg & 0xFF; 1370 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1371 s->pos = 0; 1372 s->len = 2; 1373 s->state = STATE_READING_DATA; 1374 break; 1375 case WNVCR: 1376 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1377 s->needed_bytes = 2; 1378 s->pos = 0; 1379 s->len = 0; 1380 s->state = STATE_COLLECTING_DATA; 1381 } 1382 break; 1383 case RVCR: 1384 s->data[0] = s->volatile_cfg & 0xFF; 1385 s->pos = 0; 1386 s->len = 1; 1387 s->state = STATE_READING_DATA; 1388 break; 1389 case WVCR: 1390 if (s->write_enable) { 1391 s->needed_bytes = 1; 1392 s->pos = 0; 1393 s->len = 0; 1394 s->state = STATE_COLLECTING_DATA; 1395 } 1396 break; 1397 case REVCR: 1398 s->data[0] = s->enh_volatile_cfg & 0xFF; 1399 s->pos = 0; 1400 s->len = 1; 1401 s->state = STATE_READING_DATA; 1402 break; 1403 case WEVCR: 1404 if (s->write_enable) { 1405 s->needed_bytes = 1; 1406 s->pos = 0; 1407 s->len = 0; 1408 s->state = STATE_COLLECTING_DATA; 1409 } 1410 break; 1411 case RESET_ENABLE: 1412 s->reset_enable = true; 1413 break; 1414 case RESET_MEMORY: 1415 if (s->reset_enable) { 1416 reset_memory(s); 1417 } 1418 break; 1419 case RDCR_EQIO: 1420 switch (get_man(s)) { 1421 case MAN_SPANSION: 1422 s->data[0] = (!!s->quad_enable) << 1; 1423 s->pos = 0; 1424 s->len = 1; 1425 s->state = STATE_READING_DATA; 1426 break; 1427 case MAN_MACRONIX: 1428 s->quad_enable = true; 1429 break; 1430 default: 1431 break; 1432 } 1433 break; 1434 case RSTQIO: 1435 s->quad_enable = false; 1436 break; 1437 case AAI_WP: 1438 if (get_man(s) == MAN_SST) { 1439 if (s->write_enable) { 1440 if (s->aai_enable) { 1441 s->state = STATE_PAGE_PROGRAM; 1442 } else { 1443 s->aai_enable = true; 1444 s->needed_bytes = get_addr_length(s); 1445 s->state = STATE_COLLECTING_DATA; 1446 } 1447 } else { 1448 qemu_log_mask(LOG_GUEST_ERROR, 1449 "M25P80: AAI_WP with write protect\n"); 1450 } 1451 } else { 1452 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1453 } 1454 break; 1455 case RDSFDP: 1456 if (s->pi->sfdp_read) { 1457 s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */ 1458 s->pos = 0; 1459 s->len = 0; 1460 s->state = STATE_COLLECTING_DATA; 1461 break; 1462 } 1463 /* Fallthrough */ 1464 1465 default: 1466 s->pos = 0; 1467 s->len = 1; 1468 s->state = STATE_READING_DATA; 1469 s->data_read_loop = true; 1470 s->data[0] = 0; 1471 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1472 break; 1473 } 1474 } 1475 1476 static int m25p80_cs(SSIPeripheral *ss, bool select) 1477 { 1478 Flash *s = M25P80(ss); 1479 1480 if (select) { 1481 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1482 complete_collecting_data(s); 1483 } 1484 s->len = 0; 1485 s->pos = 0; 1486 s->state = STATE_IDLE; 1487 flash_sync_dirty(s, -1); 1488 s->data_read_loop = false; 1489 } 1490 1491 trace_m25p80_select(s, select ? "de" : ""); 1492 1493 return 0; 1494 } 1495 1496 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) 1497 { 1498 Flash *s = M25P80(ss); 1499 uint32_t r = 0; 1500 1501 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, 1502 s->cur_addr, (uint8_t)tx); 1503 1504 switch (s->state) { 1505 1506 case STATE_PAGE_PROGRAM: 1507 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); 1508 flash_write8(s, s->cur_addr, (uint8_t)tx); 1509 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1510 1511 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) { 1512 /* 1513 * There is no wrap mode during AAI programming once the highest 1514 * unprotected memory address is reached. The Write-Enable-Latch 1515 * bit is automatically reset, and AAI programming mode aborts. 1516 */ 1517 s->write_enable = false; 1518 s->aai_enable = false; 1519 } 1520 1521 break; 1522 1523 case STATE_READ: 1524 r = s->storage[s->cur_addr]; 1525 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); 1526 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1527 break; 1528 1529 case STATE_COLLECTING_DATA: 1530 case STATE_COLLECTING_VAR_LEN_DATA: 1531 1532 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1533 qemu_log_mask(LOG_GUEST_ERROR, 1534 "M25P80: Write overrun internal data buffer. " 1535 "SPI controller (QEMU emulator or guest driver) " 1536 "is misbehaving\n"); 1537 s->len = s->pos = 0; 1538 s->state = STATE_IDLE; 1539 break; 1540 } 1541 1542 s->data[s->len] = (uint8_t)tx; 1543 s->len++; 1544 1545 if (s->len == s->needed_bytes) { 1546 complete_collecting_data(s); 1547 } 1548 break; 1549 1550 case STATE_READING_DATA: 1551 1552 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1553 qemu_log_mask(LOG_GUEST_ERROR, 1554 "M25P80: Read overrun internal data buffer. " 1555 "SPI controller (QEMU emulator or guest driver) " 1556 "is misbehaving\n"); 1557 s->len = s->pos = 0; 1558 s->state = STATE_IDLE; 1559 break; 1560 } 1561 1562 r = s->data[s->pos]; 1563 trace_m25p80_read_data(s, s->pos, (uint8_t)r); 1564 s->pos++; 1565 if (s->pos == s->len) { 1566 s->pos = 0; 1567 if (!s->data_read_loop) { 1568 s->state = STATE_IDLE; 1569 } 1570 } 1571 break; 1572 case STATE_READING_SFDP: 1573 assert(s->pi->sfdp_read); 1574 r = s->pi->sfdp_read(s->cur_addr); 1575 trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r); 1576 s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1); 1577 break; 1578 1579 default: 1580 case STATE_IDLE: 1581 decode_new_cmd(s, (uint8_t)tx); 1582 break; 1583 } 1584 1585 return r; 1586 } 1587 1588 static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level) 1589 { 1590 Flash *s = M25P80(opaque); 1591 /* WP# is just a single pin. */ 1592 assert(n == 0); 1593 s->wp_level = !!level; 1594 } 1595 1596 static void m25p80_realize(SSIPeripheral *ss, Error **errp) 1597 { 1598 Flash *s = M25P80(ss); 1599 M25P80Class *mc = M25P80_GET_CLASS(s); 1600 int ret; 1601 1602 s->pi = mc->pi; 1603 1604 s->size = s->pi->sector_size * s->pi->n_sectors; 1605 s->dirty_page = -1; 1606 1607 if (s->blk) { 1608 uint64_t perm = BLK_PERM_CONSISTENT_READ | 1609 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0); 1610 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); 1611 if (ret < 0) { 1612 return; 1613 } 1614 1615 trace_m25p80_binding(s); 1616 s->storage = blk_blockalign(s->blk, s->size); 1617 1618 if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) { 1619 error_setg(errp, "failed to read the initial flash content"); 1620 return; 1621 } 1622 } else { 1623 trace_m25p80_binding_no_bdrv(s); 1624 s->storage = blk_blockalign(NULL, s->size); 1625 memset(s->storage, 0xFF, s->size); 1626 } 1627 1628 qdev_init_gpio_in_named(DEVICE(s), 1629 m25p80_write_protect_pin_irq_handler, "WP#", 1); 1630 } 1631 1632 static void m25p80_reset(DeviceState *d) 1633 { 1634 Flash *s = M25P80(d); 1635 1636 s->wp_level = true; 1637 s->status_register_write_disabled = false; 1638 s->block_protect0 = false; 1639 s->block_protect1 = false; 1640 s->block_protect2 = false; 1641 s->block_protect3 = false; 1642 s->top_bottom_bit = false; 1643 1644 reset_memory(s); 1645 } 1646 1647 static int m25p80_pre_save(void *opaque) 1648 { 1649 flash_sync_dirty((Flash *)opaque, -1); 1650 1651 return 0; 1652 } 1653 1654 static Property m25p80_properties[] = { 1655 /* This is default value for Micron flash */ 1656 DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false), 1657 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1658 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1659 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1660 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1661 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1662 DEFINE_PROP_DRIVE("drive", Flash, blk), 1663 DEFINE_PROP_END_OF_LIST(), 1664 }; 1665 1666 static int m25p80_pre_load(void *opaque) 1667 { 1668 Flash *s = (Flash *)opaque; 1669 1670 s->data_read_loop = false; 1671 return 0; 1672 } 1673 1674 static bool m25p80_data_read_loop_needed(void *opaque) 1675 { 1676 Flash *s = (Flash *)opaque; 1677 1678 return s->data_read_loop; 1679 } 1680 1681 static const VMStateDescription vmstate_m25p80_data_read_loop = { 1682 .name = "m25p80/data_read_loop", 1683 .version_id = 1, 1684 .minimum_version_id = 1, 1685 .needed = m25p80_data_read_loop_needed, 1686 .fields = (VMStateField[]) { 1687 VMSTATE_BOOL(data_read_loop, Flash), 1688 VMSTATE_END_OF_LIST() 1689 } 1690 }; 1691 1692 static bool m25p80_aai_enable_needed(void *opaque) 1693 { 1694 Flash *s = (Flash *)opaque; 1695 1696 return s->aai_enable; 1697 } 1698 1699 static const VMStateDescription vmstate_m25p80_aai_enable = { 1700 .name = "m25p80/aai_enable", 1701 .version_id = 1, 1702 .minimum_version_id = 1, 1703 .needed = m25p80_aai_enable_needed, 1704 .fields = (VMStateField[]) { 1705 VMSTATE_BOOL(aai_enable, Flash), 1706 VMSTATE_END_OF_LIST() 1707 } 1708 }; 1709 1710 static bool m25p80_wp_level_srwd_needed(void *opaque) 1711 { 1712 Flash *s = (Flash *)opaque; 1713 1714 return !s->wp_level || s->status_register_write_disabled; 1715 } 1716 1717 static const VMStateDescription vmstate_m25p80_write_protect = { 1718 .name = "m25p80/write_protect", 1719 .version_id = 1, 1720 .minimum_version_id = 1, 1721 .needed = m25p80_wp_level_srwd_needed, 1722 .fields = (VMStateField[]) { 1723 VMSTATE_BOOL(wp_level, Flash), 1724 VMSTATE_BOOL(status_register_write_disabled, Flash), 1725 VMSTATE_END_OF_LIST() 1726 } 1727 }; 1728 1729 static bool m25p80_block_protect_needed(void *opaque) 1730 { 1731 Flash *s = (Flash *)opaque; 1732 1733 return s->block_protect0 || 1734 s->block_protect1 || 1735 s->block_protect2 || 1736 s->block_protect3 || 1737 s->top_bottom_bit; 1738 } 1739 1740 static const VMStateDescription vmstate_m25p80_block_protect = { 1741 .name = "m25p80/block_protect", 1742 .version_id = 1, 1743 .minimum_version_id = 1, 1744 .needed = m25p80_block_protect_needed, 1745 .fields = (VMStateField[]) { 1746 VMSTATE_BOOL(block_protect0, Flash), 1747 VMSTATE_BOOL(block_protect1, Flash), 1748 VMSTATE_BOOL(block_protect2, Flash), 1749 VMSTATE_BOOL(block_protect3, Flash), 1750 VMSTATE_BOOL(top_bottom_bit, Flash), 1751 VMSTATE_END_OF_LIST() 1752 } 1753 }; 1754 1755 static const VMStateDescription vmstate_m25p80 = { 1756 .name = "m25p80", 1757 .version_id = 0, 1758 .minimum_version_id = 0, 1759 .pre_save = m25p80_pre_save, 1760 .pre_load = m25p80_pre_load, 1761 .fields = (VMStateField[]) { 1762 VMSTATE_UINT8(state, Flash), 1763 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1764 VMSTATE_UINT32(len, Flash), 1765 VMSTATE_UINT32(pos, Flash), 1766 VMSTATE_UINT8(needed_bytes, Flash), 1767 VMSTATE_UINT8(cmd_in_progress, Flash), 1768 VMSTATE_UINT32(cur_addr, Flash), 1769 VMSTATE_BOOL(write_enable, Flash), 1770 VMSTATE_BOOL(reset_enable, Flash), 1771 VMSTATE_UINT8(ear, Flash), 1772 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1773 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1774 VMSTATE_UINT32(volatile_cfg, Flash), 1775 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1776 VMSTATE_BOOL(quad_enable, Flash), 1777 VMSTATE_UINT8(spansion_cr1nv, Flash), 1778 VMSTATE_UINT8(spansion_cr2nv, Flash), 1779 VMSTATE_UINT8(spansion_cr3nv, Flash), 1780 VMSTATE_UINT8(spansion_cr4nv, Flash), 1781 VMSTATE_END_OF_LIST() 1782 }, 1783 .subsections = (const VMStateDescription * []) { 1784 &vmstate_m25p80_data_read_loop, 1785 &vmstate_m25p80_aai_enable, 1786 &vmstate_m25p80_write_protect, 1787 &vmstate_m25p80_block_protect, 1788 NULL 1789 } 1790 }; 1791 1792 static void m25p80_class_init(ObjectClass *klass, void *data) 1793 { 1794 DeviceClass *dc = DEVICE_CLASS(klass); 1795 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); 1796 M25P80Class *mc = M25P80_CLASS(klass); 1797 1798 k->realize = m25p80_realize; 1799 k->transfer = m25p80_transfer8; 1800 k->set_cs = m25p80_cs; 1801 k->cs_polarity = SSI_CS_LOW; 1802 dc->vmsd = &vmstate_m25p80; 1803 device_class_set_props(dc, m25p80_properties); 1804 dc->reset = m25p80_reset; 1805 mc->pi = data; 1806 } 1807 1808 static const TypeInfo m25p80_info = { 1809 .name = TYPE_M25P80, 1810 .parent = TYPE_SSI_PERIPHERAL, 1811 .instance_size = sizeof(Flash), 1812 .class_size = sizeof(M25P80Class), 1813 .abstract = true, 1814 }; 1815 1816 static void m25p80_register_types(void) 1817 { 1818 int i; 1819 1820 type_register_static(&m25p80_info); 1821 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1822 TypeInfo ti = { 1823 .name = known_devices[i].part_name, 1824 .parent = TYPE_M25P80, 1825 .class_init = m25p80_class_init, 1826 .class_data = (void *)&known_devices[i], 1827 }; 1828 type_register(&ti); 1829 } 1830 } 1831 1832 type_init(m25p80_register_types) 1833