1 /* 2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command 3 * set. Known devices table current as of Jun/2012 and taken from linux. 4 * See drivers/mtd/devices/m25p80.c. 5 * 6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> 7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> 8 * Copyright (C) 2012 PetaLogix 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 or 13 * (at your option) a later version of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "sysemu/block-backend.h" 27 #include "hw/block/block.h" 28 #include "hw/block/flash.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/qdev-properties-system.h" 31 #include "hw/ssi/ssi.h" 32 #include "migration/vmstate.h" 33 #include "qemu/bitops.h" 34 #include "qemu/log.h" 35 #include "qemu/module.h" 36 #include "qemu/error-report.h" 37 #include "qapi/error.h" 38 #include "trace.h" 39 #include "qom/object.h" 40 #include "m25p80_sfdp.h" 41 42 /* 16 MiB max in 3 byte address mode */ 43 #define MAX_3BYTES_SIZE 0x1000000 44 #define SPI_NOR_MAX_ID_LEN 6 45 46 /* Fields for FlashPartInfo->flags */ 47 enum spi_flash_option_flags { 48 ER_4K = BIT(0), 49 ER_32K = BIT(1), 50 EEPROM = BIT(2), 51 HAS_SR_TB = BIT(3), 52 HAS_SR_BP3_BIT6 = BIT(4), 53 }; 54 55 typedef struct FlashPartInfo { 56 const char *part_name; 57 /* 58 * This array stores the ID bytes. 59 * The first three bytes are the JEDIC ID. 60 * JEDEC ID zero means "no ID" (mostly older chips). 61 */ 62 uint8_t id[SPI_NOR_MAX_ID_LEN]; 63 uint8_t id_len; 64 /* there is confusion between manufacturers as to what a sector is. In this 65 * device model, a "sector" is the size that is erased by the ERASE_SECTOR 66 * command (opcode 0xd8). 67 */ 68 uint32_t sector_size; 69 uint32_t n_sectors; 70 uint32_t page_size; 71 uint16_t flags; 72 /* 73 * Big sized spi nor are often stacked devices, thus sometime 74 * replace chip erase with die erase. 75 * This field inform how many die is in the chip. 76 */ 77 uint8_t die_cnt; 78 uint8_t (*sfdp_read)(uint32_t sfdp_addr); 79 } FlashPartInfo; 80 81 /* adapted from linux */ 82 /* Used when the "_ext_id" is two bytes at most */ 83 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 84 .part_name = _part_name,\ 85 .id = {\ 86 ((_jedec_id) >> 16) & 0xff,\ 87 ((_jedec_id) >> 8) & 0xff,\ 88 (_jedec_id) & 0xff,\ 89 ((_ext_id) >> 8) & 0xff,\ 90 (_ext_id) & 0xff,\ 91 },\ 92 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 93 .sector_size = (_sector_size),\ 94 .n_sectors = (_n_sectors),\ 95 .page_size = 256,\ 96 .flags = (_flags),\ 97 .die_cnt = 0 98 99 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ 100 .part_name = _part_name,\ 101 .id = {\ 102 ((_jedec_id) >> 16) & 0xff,\ 103 ((_jedec_id) >> 8) & 0xff,\ 104 (_jedec_id) & 0xff,\ 105 ((_ext_id) >> 16) & 0xff,\ 106 ((_ext_id) >> 8) & 0xff,\ 107 (_ext_id) & 0xff,\ 108 },\ 109 .id_len = 6,\ 110 .sector_size = (_sector_size),\ 111 .n_sectors = (_n_sectors),\ 112 .page_size = 256,\ 113 .flags = (_flags),\ 114 .die_cnt = 0 115 116 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ 117 _flags, _die_cnt)\ 118 .part_name = _part_name,\ 119 .id = {\ 120 ((_jedec_id) >> 16) & 0xff,\ 121 ((_jedec_id) >> 8) & 0xff,\ 122 (_jedec_id) & 0xff,\ 123 ((_ext_id) >> 8) & 0xff,\ 124 (_ext_id) & 0xff,\ 125 },\ 126 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ 127 .sector_size = (_sector_size),\ 128 .n_sectors = (_n_sectors),\ 129 .page_size = 256,\ 130 .flags = (_flags),\ 131 .die_cnt = _die_cnt 132 133 #define JEDEC_NUMONYX 0x20 134 #define JEDEC_WINBOND 0xEF 135 #define JEDEC_SPANSION 0x01 136 137 /* Numonyx (Micron) Configuration register macros */ 138 #define VCFG_DUMMY 0x1 139 #define VCFG_WRAP_SEQUENTIAL 0x2 140 #define NVCFG_XIP_MODE_DISABLED (7 << 9) 141 #define NVCFG_XIP_MODE_MASK (7 << 9) 142 #define VCFG_XIP_MODE_DISABLED (1 << 3) 143 #define CFG_DUMMY_CLK_LEN 4 144 #define NVCFG_DUMMY_CLK_POS 12 145 #define VCFG_DUMMY_CLK_POS 4 146 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 147 #define EVCFG_VPP_ACCELERATOR (1 << 3) 148 #define EVCFG_RESET_HOLD_ENABLED (1 << 4) 149 #define NVCFG_DUAL_IO_MASK (1 << 2) 150 #define EVCFG_DUAL_IO_DISABLED (1 << 6) 151 #define NVCFG_QUAD_IO_MASK (1 << 3) 152 #define EVCFG_QUAD_IO_DISABLED (1 << 7) 153 #define NVCFG_4BYTE_ADDR_MASK (1 << 0) 154 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) 155 156 /* Numonyx (Micron) Flag Status Register macros */ 157 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 158 #define FSR_FLASH_READY (1 << 7) 159 160 /* Spansion configuration registers macros. */ 161 #define SPANSION_QUAD_CFG_POS 0 162 #define SPANSION_QUAD_CFG_LEN 1 163 #define SPANSION_DUMMY_CLK_POS 0 164 #define SPANSION_DUMMY_CLK_LEN 4 165 #define SPANSION_ADDR_LEN_POS 7 166 #define SPANSION_ADDR_LEN_LEN 1 167 168 /* 169 * Spansion read mode command length in bytes, 170 * the mode is currently not supported. 171 */ 172 173 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 174 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 175 176 static const FlashPartInfo known_devices[] = { 177 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 178 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, 179 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, 180 181 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, 182 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, 183 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, 184 185 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, 186 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, 187 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, 188 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, 189 190 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, 191 192 /* Atmel EEPROMS - it is assumed, that don't care bit in command 193 * is set to 0. Block protection is not supported. 194 */ 195 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, 196 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, 197 198 /* EON -- en25xxx */ 199 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, 200 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, 201 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, 202 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, 203 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, 204 205 /* GigaDevice */ 206 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, 207 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, 208 209 /* Intel/Numonyx -- xxxs33b */ 210 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, 211 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, 212 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, 213 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, 214 215 /* ISSI */ 216 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, 217 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, 218 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, 219 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, 220 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, 221 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, 222 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) }, 223 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) }, 224 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) }, 225 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) }, 226 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K), 227 .sfdp_read = m25p80_sfdp_is25wp256 }, 228 229 /* Macronix */ 230 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, 231 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, 232 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, 233 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, 234 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, 235 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, 236 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, 237 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, 238 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 239 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e }, 240 { INFO6("mx25l25635f", 0xc22019, 0xc22019, 64 << 10, 512, 241 ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f }, 242 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, 243 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 244 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, 245 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, 246 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K), 247 .sfdp_read = m25p80_sfdp_mx66l1g45g }, 248 249 /* Micron */ 250 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, 251 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, 252 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, 253 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, 254 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, 255 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, 256 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, 257 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K), 258 .sfdp_read = m25p80_sfdp_n25q256a }, 259 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, 260 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 261 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, 262 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, 263 ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB), 264 .sfdp_read = m25p80_sfdp_n25q256a }, 265 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, 266 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, 267 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, 268 { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024, 269 ER_4K | ER_32K, 2), 270 .sfdp_read = m25p80_sfdp_mt35xu01g }, 271 { INFO_STACKED("mt35xu02gbba", 0x2c5b1c, 0x104100, 128 << 10, 2048, 272 ER_4K | ER_32K, 4), 273 .sfdp_read = m25p80_sfdp_mt35xu02g }, 274 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 275 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, 276 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 277 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, 278 { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 279 { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, 280 281 /* Spansion -- single (large) sector size only, at least 282 * for the chips listed here (without boot sectors). 283 */ 284 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, 285 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, 286 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, 287 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, 288 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, 289 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, 290 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, 291 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, 292 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, 293 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, 294 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, 295 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, 296 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, 297 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, 298 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, 299 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, 300 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, 301 302 /* Spansion -- boot sectors support */ 303 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, 304 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, 305 306 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ 307 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, 308 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, 309 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, 310 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, 311 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, 312 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, 313 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, 314 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, 315 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, 316 317 /* ST Microelectronics -- newer production may have feature updates */ 318 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, 319 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, 320 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, 321 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, 322 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, 323 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, 324 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, 325 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, 326 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, 327 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, 328 329 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, 330 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, 331 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, 332 333 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, 334 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, 335 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, 336 337 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, 338 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, 339 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, 340 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, 341 342 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ 343 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, 344 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, 345 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, 346 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, 347 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, 348 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, 349 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, 350 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, 351 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, 352 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, 353 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, 354 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, 355 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K), 356 .sfdp_read = m25p80_sfdp_w25q256 }, 357 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K), 358 .sfdp_read = m25p80_sfdp_w25q512jv }, 359 { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K), 360 .sfdp_read = m25p80_sfdp_w25q01jvq }, 361 362 /* Microchip */ 363 { INFO("25csm04", 0x29cc00, 0x100, 64 << 10, 8, 0) }, 364 }; 365 366 typedef enum { 367 NOP = 0, 368 WRSR = 0x1, 369 WRDI = 0x4, 370 RDSR = 0x5, 371 WREN = 0x6, 372 BRRD = 0x16, 373 BRWR = 0x17, 374 JEDEC_READ = 0x9f, 375 BULK_ERASE_60 = 0x60, 376 BULK_ERASE = 0xc7, 377 READ_FSR = 0x70, 378 RDCR = 0x15, 379 RDSFDP = 0x5a, 380 381 READ = 0x03, 382 READ4 = 0x13, 383 FAST_READ = 0x0b, 384 FAST_READ4 = 0x0c, 385 DOR = 0x3b, 386 DOR4 = 0x3c, 387 QOR = 0x6b, 388 QOR4 = 0x6c, 389 DIOR = 0xbb, 390 DIOR4 = 0xbc, 391 QIOR = 0xeb, 392 QIOR4 = 0xec, 393 394 PP = 0x02, 395 PP4 = 0x12, 396 PP4_4 = 0x3e, 397 DPP = 0xa2, 398 QPP = 0x32, 399 QPP_4 = 0x34, 400 RDID_90 = 0x90, 401 RDID_AB = 0xab, 402 AAI_WP = 0xad, 403 404 ERASE_4K = 0x20, 405 ERASE4_4K = 0x21, 406 ERASE_32K = 0x52, 407 ERASE4_32K = 0x5c, 408 ERASE_SECTOR = 0xd8, 409 ERASE4_SECTOR = 0xdc, 410 411 EN_4BYTE_ADDR = 0xB7, 412 EX_4BYTE_ADDR = 0xE9, 413 414 EXTEND_ADDR_READ = 0xC8, 415 EXTEND_ADDR_WRITE = 0xC5, 416 417 RESET_ENABLE = 0x66, 418 RESET_MEMORY = 0x99, 419 420 /* 421 * Micron: 0x35 - enable QPI 422 * Spansion: 0x35 - read control register 423 * Winbond: 0x35 - quad enable 424 */ 425 RDCR_EQIO = 0x35, 426 RSTQIO = 0xf5, 427 428 RNVCR = 0xB5, 429 WNVCR = 0xB1, 430 431 RVCR = 0x85, 432 WVCR = 0x81, 433 434 REVCR = 0x65, 435 WEVCR = 0x61, 436 437 DIE_ERASE = 0xC4, 438 } FlashCMD; 439 440 typedef enum { 441 STATE_IDLE, 442 STATE_PAGE_PROGRAM, 443 STATE_READ, 444 STATE_COLLECTING_DATA, 445 STATE_COLLECTING_VAR_LEN_DATA, 446 STATE_READING_DATA, 447 STATE_READING_SFDP, 448 } CMDState; 449 450 typedef enum { 451 MAN_SPANSION, 452 MAN_MACRONIX, 453 MAN_NUMONYX, 454 MAN_WINBOND, 455 MAN_SST, 456 MAN_ISSI, 457 MAN_GENERIC, 458 } Manufacturer; 459 460 typedef enum { 461 MODE_STD = 0, 462 MODE_DIO = 1, 463 MODE_QIO = 2 464 } SPIMode; 465 466 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 467 468 struct Flash { 469 SSIPeripheral parent_obj; 470 471 BlockBackend *blk; 472 473 uint8_t *storage; 474 uint32_t size; 475 int page_size; 476 477 uint8_t state; 478 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; 479 uint32_t len; 480 uint32_t pos; 481 bool data_read_loop; 482 uint8_t needed_bytes; 483 uint8_t cmd_in_progress; 484 uint32_t cur_addr; 485 uint32_t nonvolatile_cfg; 486 /* Configuration register for Macronix */ 487 uint32_t volatile_cfg; 488 uint32_t enh_volatile_cfg; 489 /* Spansion cfg registers. */ 490 uint8_t spansion_cr1nv; 491 uint8_t spansion_cr2nv; 492 uint8_t spansion_cr3nv; 493 uint8_t spansion_cr4nv; 494 uint8_t spansion_cr1v; 495 uint8_t spansion_cr2v; 496 uint8_t spansion_cr3v; 497 uint8_t spansion_cr4v; 498 bool wp_level; 499 bool write_enable; 500 bool four_bytes_address_mode; 501 bool reset_enable; 502 bool quad_enable; 503 bool aai_enable; 504 bool block_protect0; 505 bool block_protect1; 506 bool block_protect2; 507 bool block_protect3; 508 bool top_bottom_bit; 509 bool status_register_write_disabled; 510 uint8_t ear; 511 512 int64_t dirty_page; 513 514 const FlashPartInfo *pi; 515 516 }; 517 518 struct M25P80Class { 519 SSIPeripheralClass parent_class; 520 FlashPartInfo *pi; 521 }; 522 523 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) 524 525 static inline Manufacturer get_man(Flash *s) 526 { 527 switch (s->pi->id[0]) { 528 case 0x20: 529 return MAN_NUMONYX; 530 case 0xEF: 531 return MAN_WINBOND; 532 case 0x01: 533 return MAN_SPANSION; 534 case 0xC2: 535 return MAN_MACRONIX; 536 case 0xBF: 537 return MAN_SST; 538 case 0x9D: 539 return MAN_ISSI; 540 default: 541 return MAN_GENERIC; 542 } 543 } 544 545 static void blk_sync_complete(void *opaque, int ret) 546 { 547 QEMUIOVector *iov = opaque; 548 549 qemu_iovec_destroy(iov); 550 g_free(iov); 551 552 /* do nothing. Masters do not directly interact with the backing store, 553 * only the working copy so no mutexing required. 554 */ 555 } 556 557 static void flash_sync_page(Flash *s, int page) 558 { 559 QEMUIOVector *iov; 560 561 if (!s->blk || !blk_is_writable(s->blk)) { 562 return; 563 } 564 565 iov = g_new(QEMUIOVector, 1); 566 qemu_iovec_init(iov, 1); 567 qemu_iovec_add(iov, s->storage + page * s->pi->page_size, 568 s->pi->page_size); 569 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, 570 blk_sync_complete, iov); 571 } 572 573 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) 574 { 575 QEMUIOVector *iov; 576 577 if (!s->blk || !blk_is_writable(s->blk)) { 578 return; 579 } 580 581 assert(!(len % BDRV_SECTOR_SIZE)); 582 iov = g_new(QEMUIOVector, 1); 583 qemu_iovec_init(iov, 1); 584 qemu_iovec_add(iov, s->storage + off, len); 585 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); 586 } 587 588 static void flash_erase(Flash *s, int offset, FlashCMD cmd) 589 { 590 uint32_t len; 591 uint8_t capa_to_assert = 0; 592 593 switch (cmd) { 594 case ERASE_4K: 595 case ERASE4_4K: 596 len = 4 * KiB; 597 capa_to_assert = ER_4K; 598 break; 599 case ERASE_32K: 600 case ERASE4_32K: 601 len = 32 * KiB; 602 capa_to_assert = ER_32K; 603 break; 604 case ERASE_SECTOR: 605 case ERASE4_SECTOR: 606 len = s->pi->sector_size; 607 break; 608 case BULK_ERASE: 609 len = s->size; 610 break; 611 case DIE_ERASE: 612 if (s->pi->die_cnt) { 613 len = s->size / s->pi->die_cnt; 614 offset = offset & (~(len - 1)); 615 } else { 616 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" 617 " by device\n"); 618 return; 619 } 620 break; 621 default: 622 abort(); 623 } 624 625 trace_m25p80_flash_erase(s, offset, len); 626 627 if ((s->pi->flags & capa_to_assert) != capa_to_assert) { 628 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" 629 " device\n", len); 630 } 631 632 if (!s->write_enable) { 633 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); 634 return; 635 } 636 memset(s->storage + offset, 0xff, len); 637 flash_sync_area(s, offset, len); 638 } 639 640 static inline void flash_sync_dirty(Flash *s, int64_t newpage) 641 { 642 if (s->dirty_page >= 0 && s->dirty_page != newpage) { 643 flash_sync_page(s, s->dirty_page); 644 s->dirty_page = newpage; 645 } 646 } 647 648 static inline 649 void flash_write8(Flash *s, uint32_t addr, uint8_t data) 650 { 651 uint32_t page = addr / s->pi->page_size; 652 uint8_t prev = s->storage[s->cur_addr]; 653 uint32_t block_protect_value = (s->block_protect3 << 3) | 654 (s->block_protect2 << 2) | 655 (s->block_protect1 << 1) | 656 (s->block_protect0 << 0); 657 658 if (!s->write_enable) { 659 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); 660 return; 661 } 662 663 if (block_protect_value > 0) { 664 uint32_t num_protected_sectors = 1 << (block_protect_value - 1); 665 uint32_t sector = addr / s->pi->sector_size; 666 667 /* top_bottom_bit == 0 means TOP */ 668 if (!s->top_bottom_bit) { 669 if (s->pi->n_sectors <= sector + num_protected_sectors) { 670 qemu_log_mask(LOG_GUEST_ERROR, 671 "M25P80: write with write protect!\n"); 672 return; 673 } 674 } else { 675 if (sector < num_protected_sectors) { 676 qemu_log_mask(LOG_GUEST_ERROR, 677 "M25P80: write with write protect!\n"); 678 return; 679 } 680 } 681 } 682 683 if ((prev ^ data) & data) { 684 trace_m25p80_programming_zero_to_one(s, addr, prev, data); 685 } 686 687 if (s->pi->flags & EEPROM) { 688 s->storage[s->cur_addr] = data; 689 } else { 690 s->storage[s->cur_addr] &= data; 691 } 692 693 flash_sync_dirty(s, page); 694 s->dirty_page = page; 695 } 696 697 static inline int get_addr_length(Flash *s) 698 { 699 /* check if eeprom is in use */ 700 if (s->pi->flags == EEPROM) { 701 return 2; 702 } 703 704 switch (s->cmd_in_progress) { 705 case RDSFDP: 706 return 3; 707 case PP4: 708 case PP4_4: 709 case QPP_4: 710 case READ4: 711 case QIOR4: 712 case ERASE4_4K: 713 case ERASE4_32K: 714 case ERASE4_SECTOR: 715 case FAST_READ4: 716 case DOR4: 717 case QOR4: 718 case DIOR4: 719 return 4; 720 default: 721 return s->four_bytes_address_mode ? 4 : 3; 722 } 723 } 724 725 static void complete_collecting_data(Flash *s) 726 { 727 int i, n; 728 729 n = get_addr_length(s); 730 s->cur_addr = (n == 3 ? s->ear : 0); 731 for (i = 0; i < n; ++i) { 732 s->cur_addr <<= 8; 733 s->cur_addr |= s->data[i]; 734 } 735 736 s->cur_addr &= s->size - 1; 737 738 s->state = STATE_IDLE; 739 740 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear, 741 s->cur_addr); 742 743 switch (s->cmd_in_progress) { 744 case DPP: 745 case QPP: 746 case QPP_4: 747 case PP: 748 case PP4: 749 case PP4_4: 750 s->state = STATE_PAGE_PROGRAM; 751 break; 752 case AAI_WP: 753 /* AAI programming starts from the even address */ 754 s->cur_addr &= ~BIT(0); 755 s->state = STATE_PAGE_PROGRAM; 756 break; 757 case READ: 758 case READ4: 759 case FAST_READ: 760 case FAST_READ4: 761 case DOR: 762 case DOR4: 763 case QOR: 764 case QOR4: 765 case DIOR: 766 case DIOR4: 767 case QIOR: 768 case QIOR4: 769 s->state = STATE_READ; 770 break; 771 case ERASE_4K: 772 case ERASE4_4K: 773 case ERASE_32K: 774 case ERASE4_32K: 775 case ERASE_SECTOR: 776 case ERASE4_SECTOR: 777 case DIE_ERASE: 778 flash_erase(s, s->cur_addr, s->cmd_in_progress); 779 break; 780 case WRSR: 781 s->status_register_write_disabled = extract32(s->data[0], 7, 1); 782 s->block_protect0 = extract32(s->data[0], 2, 1); 783 s->block_protect1 = extract32(s->data[0], 3, 1); 784 s->block_protect2 = extract32(s->data[0], 4, 1); 785 if (s->pi->flags & HAS_SR_TB) { 786 s->top_bottom_bit = extract32(s->data[0], 5, 1); 787 } 788 if (s->pi->flags & HAS_SR_BP3_BIT6) { 789 s->block_protect3 = extract32(s->data[0], 6, 1); 790 } 791 792 switch (get_man(s)) { 793 case MAN_SPANSION: 794 s->quad_enable = !!(s->data[1] & 0x02); 795 break; 796 case MAN_ISSI: 797 s->quad_enable = extract32(s->data[0], 6, 1); 798 break; 799 case MAN_MACRONIX: 800 s->quad_enable = extract32(s->data[0], 6, 1); 801 if (s->len > 1) { 802 s->volatile_cfg = s->data[1]; 803 s->four_bytes_address_mode = extract32(s->data[1], 5, 1); 804 } 805 break; 806 case MAN_WINBOND: 807 if (s->len > 1) { 808 s->quad_enable = !!(s->data[1] & 0x02); 809 } 810 break; 811 default: 812 break; 813 } 814 if (s->write_enable) { 815 s->write_enable = false; 816 } 817 break; 818 case BRWR: 819 case EXTEND_ADDR_WRITE: 820 s->ear = s->data[0]; 821 break; 822 case WNVCR: 823 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); 824 break; 825 case WVCR: 826 s->volatile_cfg = s->data[0]; 827 break; 828 case WEVCR: 829 s->enh_volatile_cfg = s->data[0]; 830 break; 831 case RDID_90: 832 case RDID_AB: 833 if (get_man(s) == MAN_SST) { 834 if (s->cur_addr <= 1) { 835 if (s->cur_addr) { 836 s->data[0] = s->pi->id[2]; 837 s->data[1] = s->pi->id[0]; 838 } else { 839 s->data[0] = s->pi->id[0]; 840 s->data[1] = s->pi->id[2]; 841 } 842 s->pos = 0; 843 s->len = 2; 844 s->data_read_loop = true; 845 s->state = STATE_READING_DATA; 846 } else { 847 qemu_log_mask(LOG_GUEST_ERROR, 848 "M25P80: Invalid read id address\n"); 849 } 850 } else { 851 qemu_log_mask(LOG_GUEST_ERROR, 852 "M25P80: Read id (command 0x90/0xAB) is not supported" 853 " by device\n"); 854 } 855 break; 856 857 case RDSFDP: 858 s->state = STATE_READING_SFDP; 859 break; 860 861 default: 862 break; 863 } 864 } 865 866 static void reset_memory(Flash *s) 867 { 868 s->cmd_in_progress = NOP; 869 s->cur_addr = 0; 870 s->ear = 0; 871 s->four_bytes_address_mode = false; 872 s->len = 0; 873 s->needed_bytes = 0; 874 s->pos = 0; 875 s->state = STATE_IDLE; 876 s->write_enable = false; 877 s->reset_enable = false; 878 s->quad_enable = false; 879 s->aai_enable = false; 880 881 switch (get_man(s)) { 882 case MAN_NUMONYX: 883 s->volatile_cfg = 0; 884 s->volatile_cfg |= VCFG_DUMMY; 885 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; 886 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) 887 == NVCFG_XIP_MODE_DISABLED) { 888 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED; 889 } 890 s->volatile_cfg |= deposit32(s->volatile_cfg, 891 VCFG_DUMMY_CLK_POS, 892 CFG_DUMMY_CLK_LEN, 893 extract32(s->nonvolatile_cfg, 894 NVCFG_DUMMY_CLK_POS, 895 CFG_DUMMY_CLK_LEN) 896 ); 897 898 s->enh_volatile_cfg = 0; 899 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; 900 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; 901 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; 902 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { 903 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED; 904 } 905 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { 906 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED; 907 } 908 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { 909 s->four_bytes_address_mode = true; 910 } 911 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { 912 s->ear = s->size / MAX_3BYTES_SIZE - 1; 913 } 914 break; 915 case MAN_MACRONIX: 916 s->volatile_cfg = 0x7; 917 break; 918 case MAN_SPANSION: 919 s->spansion_cr1v = s->spansion_cr1nv; 920 s->spansion_cr2v = s->spansion_cr2nv; 921 s->spansion_cr3v = s->spansion_cr3nv; 922 s->spansion_cr4v = s->spansion_cr4nv; 923 s->quad_enable = extract32(s->spansion_cr1v, 924 SPANSION_QUAD_CFG_POS, 925 SPANSION_QUAD_CFG_LEN 926 ); 927 s->four_bytes_address_mode = extract32(s->spansion_cr2v, 928 SPANSION_ADDR_LEN_POS, 929 SPANSION_ADDR_LEN_LEN 930 ); 931 break; 932 default: 933 break; 934 } 935 936 trace_m25p80_reset_done(s); 937 } 938 939 static uint8_t numonyx_mode(Flash *s) 940 { 941 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { 942 return MODE_QIO; 943 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { 944 return MODE_DIO; 945 } else { 946 return MODE_STD; 947 } 948 } 949 950 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s) 951 { 952 uint8_t num_dummies; 953 uint8_t mode; 954 assert(get_man(s) == MAN_NUMONYX); 955 956 mode = numonyx_mode(s); 957 num_dummies = extract32(s->volatile_cfg, 4, 4); 958 959 if (num_dummies == 0x0 || num_dummies == 0xf) { 960 switch (s->cmd_in_progress) { 961 case QIOR: 962 case QIOR4: 963 num_dummies = 10; 964 break; 965 default: 966 num_dummies = (mode == MODE_QIO) ? 10 : 8; 967 break; 968 } 969 } 970 971 return num_dummies; 972 } 973 974 static void decode_fast_read_cmd(Flash *s) 975 { 976 s->needed_bytes = get_addr_length(s); 977 switch (get_man(s)) { 978 /* Dummy cycles - modeled with bytes writes instead of bits */ 979 case MAN_SST: 980 s->needed_bytes += 1; 981 break; 982 case MAN_WINBOND: 983 s->needed_bytes += 8; 984 break; 985 case MAN_NUMONYX: 986 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 987 break; 988 case MAN_MACRONIX: 989 if (extract32(s->volatile_cfg, 6, 2) == 1) { 990 s->needed_bytes += 6; 991 } else { 992 s->needed_bytes += 8; 993 } 994 break; 995 case MAN_SPANSION: 996 s->needed_bytes += extract32(s->spansion_cr2v, 997 SPANSION_DUMMY_CLK_POS, 998 SPANSION_DUMMY_CLK_LEN 999 ); 1000 break; 1001 case MAN_ISSI: 1002 /* 1003 * The Fast Read instruction code is followed by address bytes and 1004 * dummy cycles, transmitted via the SI line. 1005 * 1006 * The number of dummy cycles is configurable but this is currently 1007 * unmodeled, hence the default value 8 is used. 1008 * 1009 * QPI (Quad Peripheral Interface) mode has different default value 1010 * of dummy cycles, but this is unsupported at the time being. 1011 */ 1012 s->needed_bytes += 1; 1013 break; 1014 default: 1015 break; 1016 } 1017 s->pos = 0; 1018 s->len = 0; 1019 s->state = STATE_COLLECTING_DATA; 1020 } 1021 1022 static void decode_dio_read_cmd(Flash *s) 1023 { 1024 s->needed_bytes = get_addr_length(s); 1025 /* Dummy cycles modeled with bytes writes instead of bits */ 1026 switch (get_man(s)) { 1027 case MAN_WINBOND: 1028 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1029 break; 1030 case MAN_SPANSION: 1031 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1032 s->needed_bytes += extract32(s->spansion_cr2v, 1033 SPANSION_DUMMY_CLK_POS, 1034 SPANSION_DUMMY_CLK_LEN 1035 ); 1036 break; 1037 case MAN_NUMONYX: 1038 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1039 break; 1040 case MAN_MACRONIX: 1041 switch (extract32(s->volatile_cfg, 6, 2)) { 1042 case 1: 1043 s->needed_bytes += 6; 1044 break; 1045 case 2: 1046 s->needed_bytes += 8; 1047 break; 1048 default: 1049 s->needed_bytes += 4; 1050 break; 1051 } 1052 break; 1053 case MAN_ISSI: 1054 /* 1055 * The Fast Read Dual I/O instruction code is followed by address bytes 1056 * and dummy cycles, transmitted via the IO1 and IO0 line. 1057 * 1058 * The number of dummy cycles is configurable but this is currently 1059 * unmodeled, hence the default value 4 is used. 1060 */ 1061 s->needed_bytes += 1; 1062 break; 1063 default: 1064 break; 1065 } 1066 s->pos = 0; 1067 s->len = 0; 1068 s->state = STATE_COLLECTING_DATA; 1069 } 1070 1071 static void decode_qio_read_cmd(Flash *s) 1072 { 1073 s->needed_bytes = get_addr_length(s); 1074 /* Dummy cycles modeled with bytes writes instead of bits */ 1075 switch (get_man(s)) { 1076 case MAN_WINBOND: 1077 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; 1078 s->needed_bytes += 4; 1079 break; 1080 case MAN_SPANSION: 1081 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; 1082 s->needed_bytes += extract32(s->spansion_cr2v, 1083 SPANSION_DUMMY_CLK_POS, 1084 SPANSION_DUMMY_CLK_LEN 1085 ); 1086 break; 1087 case MAN_NUMONYX: 1088 s->needed_bytes += numonyx_extract_cfg_num_dummies(s); 1089 break; 1090 case MAN_MACRONIX: 1091 switch (extract32(s->volatile_cfg, 6, 2)) { 1092 case 1: 1093 s->needed_bytes += 4; 1094 break; 1095 case 2: 1096 s->needed_bytes += 8; 1097 break; 1098 default: 1099 s->needed_bytes += 6; 1100 break; 1101 } 1102 break; 1103 case MAN_ISSI: 1104 /* 1105 * The Fast Read Quad I/O instruction code is followed by address bytes 1106 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line. 1107 * 1108 * The number of dummy cycles is configurable but this is currently 1109 * unmodeled, hence the default value 6 is used. 1110 * 1111 * QPI (Quad Peripheral Interface) mode has different default value 1112 * of dummy cycles, but this is unsupported at the time being. 1113 */ 1114 s->needed_bytes += 3; 1115 break; 1116 default: 1117 break; 1118 } 1119 s->pos = 0; 1120 s->len = 0; 1121 s->state = STATE_COLLECTING_DATA; 1122 } 1123 1124 static bool is_valid_aai_cmd(uint32_t cmd) 1125 { 1126 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR; 1127 } 1128 1129 static void decode_new_cmd(Flash *s, uint32_t value) 1130 { 1131 int i; 1132 1133 s->cmd_in_progress = value; 1134 trace_m25p80_command_decoded(s, value); 1135 1136 if (value != RESET_MEMORY) { 1137 s->reset_enable = false; 1138 } 1139 1140 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) { 1141 qemu_log_mask(LOG_GUEST_ERROR, 1142 "M25P80: Invalid cmd within AAI programming sequence"); 1143 } 1144 1145 switch (value) { 1146 1147 case ERASE_4K: 1148 case ERASE4_4K: 1149 case ERASE_32K: 1150 case ERASE4_32K: 1151 case ERASE_SECTOR: 1152 case ERASE4_SECTOR: 1153 case PP: 1154 case PP4: 1155 case DIE_ERASE: 1156 case RDID_90: 1157 case RDID_AB: 1158 s->needed_bytes = get_addr_length(s); 1159 s->pos = 0; 1160 s->len = 0; 1161 s->state = STATE_COLLECTING_DATA; 1162 break; 1163 case READ: 1164 case READ4: 1165 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1166 s->needed_bytes = get_addr_length(s); 1167 s->pos = 0; 1168 s->len = 0; 1169 s->state = STATE_COLLECTING_DATA; 1170 } else { 1171 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1172 "DIO or QIO mode\n", s->cmd_in_progress); 1173 } 1174 break; 1175 case DPP: 1176 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1177 s->needed_bytes = get_addr_length(s); 1178 s->pos = 0; 1179 s->len = 0; 1180 s->state = STATE_COLLECTING_DATA; 1181 } else { 1182 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1183 "QIO mode\n", s->cmd_in_progress); 1184 } 1185 break; 1186 case QPP: 1187 case QPP_4: 1188 case PP4_4: 1189 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1190 s->needed_bytes = get_addr_length(s); 1191 s->pos = 0; 1192 s->len = 0; 1193 s->state = STATE_COLLECTING_DATA; 1194 } else { 1195 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1196 "DIO mode\n", s->cmd_in_progress); 1197 } 1198 break; 1199 1200 case FAST_READ: 1201 case FAST_READ4: 1202 decode_fast_read_cmd(s); 1203 break; 1204 case DOR: 1205 case DOR4: 1206 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1207 decode_fast_read_cmd(s); 1208 } else { 1209 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1210 "QIO mode\n", s->cmd_in_progress); 1211 } 1212 break; 1213 case QOR: 1214 case QOR4: 1215 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1216 decode_fast_read_cmd(s); 1217 } else { 1218 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1219 "DIO mode\n", s->cmd_in_progress); 1220 } 1221 break; 1222 1223 case DIOR: 1224 case DIOR4: 1225 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) { 1226 decode_dio_read_cmd(s); 1227 } else { 1228 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1229 "QIO mode\n", s->cmd_in_progress); 1230 } 1231 break; 1232 1233 case QIOR: 1234 case QIOR4: 1235 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) { 1236 decode_qio_read_cmd(s); 1237 } else { 1238 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in " 1239 "DIO mode\n", s->cmd_in_progress); 1240 } 1241 break; 1242 1243 case WRSR: 1244 /* 1245 * If WP# is low and status_register_write_disabled is high, 1246 * status register writes are disabled. 1247 * This is also called "hardware protected mode" (HPM). All other 1248 * combinations of the two states are called "software protected mode" 1249 * (SPM), and status register writes are permitted. 1250 */ 1251 if ((s->wp_level == 0 && s->status_register_write_disabled) 1252 || !s->write_enable) { 1253 qemu_log_mask(LOG_GUEST_ERROR, 1254 "M25P80: Status register write is disabled!\n"); 1255 break; 1256 } 1257 1258 switch (get_man(s)) { 1259 case MAN_SPANSION: 1260 s->needed_bytes = 2; 1261 s->state = STATE_COLLECTING_DATA; 1262 break; 1263 case MAN_MACRONIX: 1264 s->needed_bytes = 2; 1265 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1266 break; 1267 case MAN_WINBOND: 1268 s->needed_bytes = 2; 1269 s->state = STATE_COLLECTING_VAR_LEN_DATA; 1270 break; 1271 default: 1272 s->needed_bytes = 1; 1273 s->state = STATE_COLLECTING_DATA; 1274 } 1275 s->pos = 0; 1276 break; 1277 1278 case WRDI: 1279 s->write_enable = false; 1280 if (get_man(s) == MAN_SST) { 1281 s->aai_enable = false; 1282 } 1283 break; 1284 case WREN: 1285 s->write_enable = true; 1286 break; 1287 1288 case RDSR: 1289 s->data[0] = (!!s->write_enable) << 1; 1290 s->data[0] |= (!!s->status_register_write_disabled) << 7; 1291 s->data[0] |= (!!s->block_protect0) << 2; 1292 s->data[0] |= (!!s->block_protect1) << 3; 1293 s->data[0] |= (!!s->block_protect2) << 4; 1294 if (s->pi->flags & HAS_SR_TB) { 1295 s->data[0] |= (!!s->top_bottom_bit) << 5; 1296 } 1297 if (s->pi->flags & HAS_SR_BP3_BIT6) { 1298 s->data[0] |= (!!s->block_protect3) << 6; 1299 } 1300 1301 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) { 1302 s->data[0] |= (!!s->quad_enable) << 6; 1303 } 1304 if (get_man(s) == MAN_SST) { 1305 s->data[0] |= (!!s->aai_enable) << 6; 1306 } 1307 1308 s->pos = 0; 1309 s->len = 1; 1310 s->data_read_loop = true; 1311 s->state = STATE_READING_DATA; 1312 break; 1313 1314 case READ_FSR: 1315 s->data[0] = FSR_FLASH_READY; 1316 if (s->four_bytes_address_mode) { 1317 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; 1318 } 1319 s->pos = 0; 1320 s->len = 1; 1321 s->data_read_loop = true; 1322 s->state = STATE_READING_DATA; 1323 break; 1324 1325 case JEDEC_READ: 1326 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) { 1327 trace_m25p80_populated_jedec(s); 1328 for (i = 0; i < s->pi->id_len; i++) { 1329 s->data[i] = s->pi->id[i]; 1330 } 1331 for (; i < SPI_NOR_MAX_ID_LEN; i++) { 1332 s->data[i] = 0; 1333 } 1334 1335 s->len = SPI_NOR_MAX_ID_LEN; 1336 s->pos = 0; 1337 s->state = STATE_READING_DATA; 1338 } else { 1339 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read " 1340 "in DIO or QIO mode\n"); 1341 } 1342 break; 1343 1344 case RDCR: 1345 s->data[0] = s->volatile_cfg & 0xFF; 1346 s->data[0] |= (!!s->four_bytes_address_mode) << 5; 1347 s->pos = 0; 1348 s->len = 1; 1349 s->state = STATE_READING_DATA; 1350 break; 1351 1352 case BULK_ERASE_60: 1353 case BULK_ERASE: 1354 if (s->write_enable) { 1355 trace_m25p80_chip_erase(s); 1356 flash_erase(s, 0, BULK_ERASE); 1357 } else { 1358 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " 1359 "protect!\n"); 1360 } 1361 break; 1362 case NOP: 1363 break; 1364 case EN_4BYTE_ADDR: 1365 s->four_bytes_address_mode = true; 1366 break; 1367 case EX_4BYTE_ADDR: 1368 s->four_bytes_address_mode = false; 1369 break; 1370 case BRRD: 1371 case EXTEND_ADDR_READ: 1372 s->data[0] = s->ear; 1373 s->pos = 0; 1374 s->len = 1; 1375 s->state = STATE_READING_DATA; 1376 break; 1377 case BRWR: 1378 case EXTEND_ADDR_WRITE: 1379 if (s->write_enable) { 1380 s->needed_bytes = 1; 1381 s->pos = 0; 1382 s->len = 0; 1383 s->state = STATE_COLLECTING_DATA; 1384 } 1385 break; 1386 case RNVCR: 1387 s->data[0] = s->nonvolatile_cfg & 0xFF; 1388 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; 1389 s->pos = 0; 1390 s->len = 2; 1391 s->state = STATE_READING_DATA; 1392 break; 1393 case WNVCR: 1394 if (s->write_enable && get_man(s) == MAN_NUMONYX) { 1395 s->needed_bytes = 2; 1396 s->pos = 0; 1397 s->len = 0; 1398 s->state = STATE_COLLECTING_DATA; 1399 } 1400 break; 1401 case RVCR: 1402 s->data[0] = s->volatile_cfg & 0xFF; 1403 s->pos = 0; 1404 s->len = 1; 1405 s->state = STATE_READING_DATA; 1406 break; 1407 case WVCR: 1408 if (s->write_enable) { 1409 s->needed_bytes = 1; 1410 s->pos = 0; 1411 s->len = 0; 1412 s->state = STATE_COLLECTING_DATA; 1413 } 1414 break; 1415 case REVCR: 1416 s->data[0] = s->enh_volatile_cfg & 0xFF; 1417 s->pos = 0; 1418 s->len = 1; 1419 s->state = STATE_READING_DATA; 1420 break; 1421 case WEVCR: 1422 if (s->write_enable) { 1423 s->needed_bytes = 1; 1424 s->pos = 0; 1425 s->len = 0; 1426 s->state = STATE_COLLECTING_DATA; 1427 } 1428 break; 1429 case RESET_ENABLE: 1430 s->reset_enable = true; 1431 break; 1432 case RESET_MEMORY: 1433 if (s->reset_enable) { 1434 reset_memory(s); 1435 } 1436 break; 1437 case RDCR_EQIO: 1438 switch (get_man(s)) { 1439 case MAN_SPANSION: 1440 s->data[0] = (!!s->quad_enable) << 1; 1441 s->pos = 0; 1442 s->len = 1; 1443 s->state = STATE_READING_DATA; 1444 break; 1445 case MAN_MACRONIX: 1446 s->quad_enable = true; 1447 break; 1448 case MAN_WINBOND: 1449 s->data[0] = (!!s->quad_enable) << 1; 1450 s->pos = 0; 1451 s->len = 1; 1452 s->state = STATE_READING_DATA; 1453 break; 1454 default: 1455 break; 1456 } 1457 break; 1458 case RSTQIO: 1459 s->quad_enable = false; 1460 break; 1461 case AAI_WP: 1462 if (get_man(s) == MAN_SST) { 1463 if (s->write_enable) { 1464 if (s->aai_enable) { 1465 s->state = STATE_PAGE_PROGRAM; 1466 } else { 1467 s->aai_enable = true; 1468 s->needed_bytes = get_addr_length(s); 1469 s->state = STATE_COLLECTING_DATA; 1470 } 1471 } else { 1472 qemu_log_mask(LOG_GUEST_ERROR, 1473 "M25P80: AAI_WP with write protect\n"); 1474 } 1475 } else { 1476 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1477 } 1478 break; 1479 case RDSFDP: 1480 if (s->pi->sfdp_read) { 1481 s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */ 1482 s->pos = 0; 1483 s->len = 0; 1484 s->state = STATE_COLLECTING_DATA; 1485 break; 1486 } 1487 /* Fallthrough */ 1488 1489 default: 1490 s->pos = 0; 1491 s->len = 1; 1492 s->state = STATE_READING_DATA; 1493 s->data_read_loop = true; 1494 s->data[0] = 0; 1495 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); 1496 break; 1497 } 1498 } 1499 1500 static int m25p80_cs(SSIPeripheral *ss, bool select) 1501 { 1502 Flash *s = M25P80(ss); 1503 1504 if (select) { 1505 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { 1506 complete_collecting_data(s); 1507 } 1508 s->len = 0; 1509 s->pos = 0; 1510 s->state = STATE_IDLE; 1511 flash_sync_dirty(s, -1); 1512 s->data_read_loop = false; 1513 } 1514 1515 trace_m25p80_select(s, select ? "de" : ""); 1516 1517 return 0; 1518 } 1519 1520 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) 1521 { 1522 Flash *s = M25P80(ss); 1523 uint32_t r = 0; 1524 1525 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos, 1526 s->cur_addr, (uint8_t)tx); 1527 1528 switch (s->state) { 1529 1530 case STATE_PAGE_PROGRAM: 1531 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx); 1532 flash_write8(s, s->cur_addr, (uint8_t)tx); 1533 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1534 1535 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) { 1536 /* 1537 * There is no wrap mode during AAI programming once the highest 1538 * unprotected memory address is reached. The Write-Enable-Latch 1539 * bit is automatically reset, and AAI programming mode aborts. 1540 */ 1541 s->write_enable = false; 1542 s->aai_enable = false; 1543 } 1544 1545 break; 1546 1547 case STATE_READ: 1548 r = s->storage[s->cur_addr]; 1549 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r); 1550 s->cur_addr = (s->cur_addr + 1) & (s->size - 1); 1551 break; 1552 1553 case STATE_COLLECTING_DATA: 1554 case STATE_COLLECTING_VAR_LEN_DATA: 1555 1556 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1557 qemu_log_mask(LOG_GUEST_ERROR, 1558 "M25P80: Write overrun internal data buffer. " 1559 "SPI controller (QEMU emulator or guest driver) " 1560 "is misbehaving\n"); 1561 s->len = s->pos = 0; 1562 s->state = STATE_IDLE; 1563 break; 1564 } 1565 1566 s->data[s->len] = (uint8_t)tx; 1567 s->len++; 1568 1569 if (s->len == s->needed_bytes) { 1570 complete_collecting_data(s); 1571 } 1572 break; 1573 1574 case STATE_READING_DATA: 1575 1576 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { 1577 qemu_log_mask(LOG_GUEST_ERROR, 1578 "M25P80: Read overrun internal data buffer. " 1579 "SPI controller (QEMU emulator or guest driver) " 1580 "is misbehaving\n"); 1581 s->len = s->pos = 0; 1582 s->state = STATE_IDLE; 1583 break; 1584 } 1585 1586 r = s->data[s->pos]; 1587 trace_m25p80_read_data(s, s->pos, (uint8_t)r); 1588 s->pos++; 1589 if (s->pos == s->len) { 1590 s->pos = 0; 1591 if (!s->data_read_loop) { 1592 s->state = STATE_IDLE; 1593 } 1594 } 1595 break; 1596 case STATE_READING_SFDP: 1597 assert(s->pi->sfdp_read); 1598 r = s->pi->sfdp_read(s->cur_addr); 1599 trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r); 1600 s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1); 1601 break; 1602 1603 default: 1604 case STATE_IDLE: 1605 decode_new_cmd(s, (uint8_t)tx); 1606 break; 1607 } 1608 1609 return r; 1610 } 1611 1612 static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level) 1613 { 1614 Flash *s = M25P80(opaque); 1615 /* WP# is just a single pin. */ 1616 assert(n == 0); 1617 s->wp_level = !!level; 1618 } 1619 1620 static void m25p80_realize(SSIPeripheral *ss, Error **errp) 1621 { 1622 Flash *s = M25P80(ss); 1623 M25P80Class *mc = M25P80_GET_CLASS(s); 1624 int ret; 1625 1626 s->pi = mc->pi; 1627 1628 s->size = s->pi->sector_size * s->pi->n_sectors; 1629 s->dirty_page = -1; 1630 1631 if (s->blk) { 1632 uint64_t perm = BLK_PERM_CONSISTENT_READ | 1633 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0); 1634 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); 1635 if (ret < 0) { 1636 return; 1637 } 1638 1639 trace_m25p80_binding(s); 1640 s->storage = blk_blockalign(s->blk, s->size); 1641 1642 if (!blk_check_size_and_read_all(s->blk, DEVICE(s), 1643 s->storage, s->size, errp)) { 1644 return; 1645 } 1646 } else { 1647 trace_m25p80_binding_no_bdrv(s); 1648 s->storage = blk_blockalign(NULL, s->size); 1649 memset(s->storage, 0xFF, s->size); 1650 } 1651 1652 qdev_init_gpio_in_named(DEVICE(s), 1653 m25p80_write_protect_pin_irq_handler, "WP#", 1); 1654 } 1655 1656 static void m25p80_reset(DeviceState *d) 1657 { 1658 Flash *s = M25P80(d); 1659 1660 s->wp_level = true; 1661 s->status_register_write_disabled = false; 1662 s->block_protect0 = false; 1663 s->block_protect1 = false; 1664 s->block_protect2 = false; 1665 s->block_protect3 = false; 1666 s->top_bottom_bit = false; 1667 1668 reset_memory(s); 1669 } 1670 1671 static int m25p80_pre_save(void *opaque) 1672 { 1673 flash_sync_dirty((Flash *)opaque, -1); 1674 1675 return 0; 1676 } 1677 1678 static Property m25p80_properties[] = { 1679 /* This is default value for Micron flash */ 1680 DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false), 1681 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), 1682 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), 1683 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), 1684 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), 1685 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), 1686 DEFINE_PROP_DRIVE("drive", Flash, blk), 1687 DEFINE_PROP_END_OF_LIST(), 1688 }; 1689 1690 static int m25p80_pre_load(void *opaque) 1691 { 1692 Flash *s = (Flash *)opaque; 1693 1694 s->data_read_loop = false; 1695 return 0; 1696 } 1697 1698 static bool m25p80_data_read_loop_needed(void *opaque) 1699 { 1700 Flash *s = (Flash *)opaque; 1701 1702 return s->data_read_loop; 1703 } 1704 1705 static const VMStateDescription vmstate_m25p80_data_read_loop = { 1706 .name = "m25p80/data_read_loop", 1707 .version_id = 1, 1708 .minimum_version_id = 1, 1709 .needed = m25p80_data_read_loop_needed, 1710 .fields = (const VMStateField[]) { 1711 VMSTATE_BOOL(data_read_loop, Flash), 1712 VMSTATE_END_OF_LIST() 1713 } 1714 }; 1715 1716 static bool m25p80_aai_enable_needed(void *opaque) 1717 { 1718 Flash *s = (Flash *)opaque; 1719 1720 return s->aai_enable; 1721 } 1722 1723 static const VMStateDescription vmstate_m25p80_aai_enable = { 1724 .name = "m25p80/aai_enable", 1725 .version_id = 1, 1726 .minimum_version_id = 1, 1727 .needed = m25p80_aai_enable_needed, 1728 .fields = (const VMStateField[]) { 1729 VMSTATE_BOOL(aai_enable, Flash), 1730 VMSTATE_END_OF_LIST() 1731 } 1732 }; 1733 1734 static bool m25p80_wp_level_srwd_needed(void *opaque) 1735 { 1736 Flash *s = (Flash *)opaque; 1737 1738 return !s->wp_level || s->status_register_write_disabled; 1739 } 1740 1741 static const VMStateDescription vmstate_m25p80_write_protect = { 1742 .name = "m25p80/write_protect", 1743 .version_id = 1, 1744 .minimum_version_id = 1, 1745 .needed = m25p80_wp_level_srwd_needed, 1746 .fields = (const VMStateField[]) { 1747 VMSTATE_BOOL(wp_level, Flash), 1748 VMSTATE_BOOL(status_register_write_disabled, Flash), 1749 VMSTATE_END_OF_LIST() 1750 } 1751 }; 1752 1753 static bool m25p80_block_protect_needed(void *opaque) 1754 { 1755 Flash *s = (Flash *)opaque; 1756 1757 return s->block_protect0 || 1758 s->block_protect1 || 1759 s->block_protect2 || 1760 s->block_protect3 || 1761 s->top_bottom_bit; 1762 } 1763 1764 static const VMStateDescription vmstate_m25p80_block_protect = { 1765 .name = "m25p80/block_protect", 1766 .version_id = 1, 1767 .minimum_version_id = 1, 1768 .needed = m25p80_block_protect_needed, 1769 .fields = (const VMStateField[]) { 1770 VMSTATE_BOOL(block_protect0, Flash), 1771 VMSTATE_BOOL(block_protect1, Flash), 1772 VMSTATE_BOOL(block_protect2, Flash), 1773 VMSTATE_BOOL(block_protect3, Flash), 1774 VMSTATE_BOOL(top_bottom_bit, Flash), 1775 VMSTATE_END_OF_LIST() 1776 } 1777 }; 1778 1779 static const VMStateDescription vmstate_m25p80 = { 1780 .name = "m25p80", 1781 .version_id = 0, 1782 .minimum_version_id = 0, 1783 .pre_save = m25p80_pre_save, 1784 .pre_load = m25p80_pre_load, 1785 .fields = (const VMStateField[]) { 1786 VMSTATE_UINT8(state, Flash), 1787 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), 1788 VMSTATE_UINT32(len, Flash), 1789 VMSTATE_UINT32(pos, Flash), 1790 VMSTATE_UINT8(needed_bytes, Flash), 1791 VMSTATE_UINT8(cmd_in_progress, Flash), 1792 VMSTATE_UINT32(cur_addr, Flash), 1793 VMSTATE_BOOL(write_enable, Flash), 1794 VMSTATE_BOOL(reset_enable, Flash), 1795 VMSTATE_UINT8(ear, Flash), 1796 VMSTATE_BOOL(four_bytes_address_mode, Flash), 1797 VMSTATE_UINT32(nonvolatile_cfg, Flash), 1798 VMSTATE_UINT32(volatile_cfg, Flash), 1799 VMSTATE_UINT32(enh_volatile_cfg, Flash), 1800 VMSTATE_BOOL(quad_enable, Flash), 1801 VMSTATE_UINT8(spansion_cr1nv, Flash), 1802 VMSTATE_UINT8(spansion_cr2nv, Flash), 1803 VMSTATE_UINT8(spansion_cr3nv, Flash), 1804 VMSTATE_UINT8(spansion_cr4nv, Flash), 1805 VMSTATE_END_OF_LIST() 1806 }, 1807 .subsections = (const VMStateDescription * const []) { 1808 &vmstate_m25p80_data_read_loop, 1809 &vmstate_m25p80_aai_enable, 1810 &vmstate_m25p80_write_protect, 1811 &vmstate_m25p80_block_protect, 1812 NULL 1813 } 1814 }; 1815 1816 static void m25p80_class_init(ObjectClass *klass, void *data) 1817 { 1818 DeviceClass *dc = DEVICE_CLASS(klass); 1819 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); 1820 M25P80Class *mc = M25P80_CLASS(klass); 1821 1822 k->realize = m25p80_realize; 1823 k->transfer = m25p80_transfer8; 1824 k->set_cs = m25p80_cs; 1825 k->cs_polarity = SSI_CS_LOW; 1826 dc->vmsd = &vmstate_m25p80; 1827 device_class_set_props(dc, m25p80_properties); 1828 device_class_set_legacy_reset(dc, m25p80_reset); 1829 mc->pi = data; 1830 } 1831 1832 static const TypeInfo m25p80_info = { 1833 .name = TYPE_M25P80, 1834 .parent = TYPE_SSI_PERIPHERAL, 1835 .instance_size = sizeof(Flash), 1836 .class_size = sizeof(M25P80Class), 1837 .abstract = true, 1838 }; 1839 1840 static void m25p80_register_types(void) 1841 { 1842 int i; 1843 1844 type_register_static(&m25p80_info); 1845 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { 1846 TypeInfo ti = { 1847 .name = known_devices[i].part_name, 1848 .parent = TYPE_M25P80, 1849 .class_init = m25p80_class_init, 1850 .class_data = (void *)&known_devices[i], 1851 }; 1852 type_register(&ti); 1853 } 1854 } 1855 1856 type_init(m25p80_register_types) 1857 1858 BlockBackend *m25p80_get_blk(DeviceState *dev) 1859 { 1860 return M25P80(dev)->blk; 1861 } 1862