1 /* 2 * QEMU Floppy disk emulator (Intel 82078) 3 * 4 * Copyright (c) 2003, 2007 Jocelyn Mayer 5 * Copyright (c) 2008 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * The controller is used in Sun4m systems in a slightly different 27 * way. There are changes in DOR register and DMA is not available. 28 */ 29 30 #include "hw/hw.h" 31 #include "hw/block/fdc.h" 32 #include "qemu/error-report.h" 33 #include "qemu/timer.h" 34 #include "hw/isa/isa.h" 35 #include "hw/sysbus.h" 36 #include "sysemu/blockdev.h" 37 #include "sysemu/sysemu.h" 38 #include "qemu/log.h" 39 40 /********************************************************/ 41 /* debug Floppy devices */ 42 //#define DEBUG_FLOPPY 43 44 #ifdef DEBUG_FLOPPY 45 #define FLOPPY_DPRINTF(fmt, ...) \ 46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) 47 #else 48 #define FLOPPY_DPRINTF(fmt, ...) 49 #endif 50 51 /********************************************************/ 52 /* Floppy drive emulation */ 53 54 typedef enum FDriveRate { 55 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */ 56 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */ 57 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */ 58 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */ 59 } FDriveRate; 60 61 typedef struct FDFormat { 62 FDriveType drive; 63 uint8_t last_sect; 64 uint8_t max_track; 65 uint8_t max_head; 66 FDriveRate rate; 67 } FDFormat; 68 69 static const FDFormat fd_formats[] = { 70 /* First entry is default format */ 71 /* 1.44 MB 3"1/2 floppy disks */ 72 { FDRIVE_DRV_144, 18, 80, 1, FDRIVE_RATE_500K, }, 73 { FDRIVE_DRV_144, 20, 80, 1, FDRIVE_RATE_500K, }, 74 { FDRIVE_DRV_144, 21, 80, 1, FDRIVE_RATE_500K, }, 75 { FDRIVE_DRV_144, 21, 82, 1, FDRIVE_RATE_500K, }, 76 { FDRIVE_DRV_144, 21, 83, 1, FDRIVE_RATE_500K, }, 77 { FDRIVE_DRV_144, 22, 80, 1, FDRIVE_RATE_500K, }, 78 { FDRIVE_DRV_144, 23, 80, 1, FDRIVE_RATE_500K, }, 79 { FDRIVE_DRV_144, 24, 80, 1, FDRIVE_RATE_500K, }, 80 /* 2.88 MB 3"1/2 floppy disks */ 81 { FDRIVE_DRV_288, 36, 80, 1, FDRIVE_RATE_1M, }, 82 { FDRIVE_DRV_288, 39, 80, 1, FDRIVE_RATE_1M, }, 83 { FDRIVE_DRV_288, 40, 80, 1, FDRIVE_RATE_1M, }, 84 { FDRIVE_DRV_288, 44, 80, 1, FDRIVE_RATE_1M, }, 85 { FDRIVE_DRV_288, 48, 80, 1, FDRIVE_RATE_1M, }, 86 /* 720 kB 3"1/2 floppy disks */ 87 { FDRIVE_DRV_144, 9, 80, 1, FDRIVE_RATE_250K, }, 88 { FDRIVE_DRV_144, 10, 80, 1, FDRIVE_RATE_250K, }, 89 { FDRIVE_DRV_144, 10, 82, 1, FDRIVE_RATE_250K, }, 90 { FDRIVE_DRV_144, 10, 83, 1, FDRIVE_RATE_250K, }, 91 { FDRIVE_DRV_144, 13, 80, 1, FDRIVE_RATE_250K, }, 92 { FDRIVE_DRV_144, 14, 80, 1, FDRIVE_RATE_250K, }, 93 /* 1.2 MB 5"1/4 floppy disks */ 94 { FDRIVE_DRV_120, 15, 80, 1, FDRIVE_RATE_500K, }, 95 { FDRIVE_DRV_120, 18, 80, 1, FDRIVE_RATE_500K, }, 96 { FDRIVE_DRV_120, 18, 82, 1, FDRIVE_RATE_500K, }, 97 { FDRIVE_DRV_120, 18, 83, 1, FDRIVE_RATE_500K, }, 98 { FDRIVE_DRV_120, 20, 80, 1, FDRIVE_RATE_500K, }, 99 /* 720 kB 5"1/4 floppy disks */ 100 { FDRIVE_DRV_120, 9, 80, 1, FDRIVE_RATE_250K, }, 101 { FDRIVE_DRV_120, 11, 80, 1, FDRIVE_RATE_250K, }, 102 /* 360 kB 5"1/4 floppy disks */ 103 { FDRIVE_DRV_120, 9, 40, 1, FDRIVE_RATE_300K, }, 104 { FDRIVE_DRV_120, 9, 40, 0, FDRIVE_RATE_300K, }, 105 { FDRIVE_DRV_120, 10, 41, 1, FDRIVE_RATE_300K, }, 106 { FDRIVE_DRV_120, 10, 42, 1, FDRIVE_RATE_300K, }, 107 /* 320 kB 5"1/4 floppy disks */ 108 { FDRIVE_DRV_120, 8, 40, 1, FDRIVE_RATE_250K, }, 109 { FDRIVE_DRV_120, 8, 40, 0, FDRIVE_RATE_250K, }, 110 /* 360 kB must match 5"1/4 better than 3"1/2... */ 111 { FDRIVE_DRV_144, 9, 80, 0, FDRIVE_RATE_250K, }, 112 /* end */ 113 { FDRIVE_DRV_NONE, -1, -1, 0, 0, }, 114 }; 115 116 static void pick_geometry(BlockDriverState *bs, int *nb_heads, 117 int *max_track, int *last_sect, 118 FDriveType drive_in, FDriveType *drive, 119 FDriveRate *rate) 120 { 121 const FDFormat *parse; 122 uint64_t nb_sectors, size; 123 int i, first_match, match; 124 125 bdrv_get_geometry(bs, &nb_sectors); 126 match = -1; 127 first_match = -1; 128 for (i = 0; ; i++) { 129 parse = &fd_formats[i]; 130 if (parse->drive == FDRIVE_DRV_NONE) { 131 break; 132 } 133 if (drive_in == parse->drive || 134 drive_in == FDRIVE_DRV_NONE) { 135 size = (parse->max_head + 1) * parse->max_track * 136 parse->last_sect; 137 if (nb_sectors == size) { 138 match = i; 139 break; 140 } 141 if (first_match == -1) { 142 first_match = i; 143 } 144 } 145 } 146 if (match == -1) { 147 if (first_match == -1) { 148 match = 1; 149 } else { 150 match = first_match; 151 } 152 parse = &fd_formats[match]; 153 } 154 *nb_heads = parse->max_head + 1; 155 *max_track = parse->max_track; 156 *last_sect = parse->last_sect; 157 *drive = parse->drive; 158 *rate = parse->rate; 159 } 160 161 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) 162 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) 163 164 /* Will always be a fixed parameter for us */ 165 #define FD_SECTOR_LEN 512 166 #define FD_SECTOR_SC 2 /* Sector size code */ 167 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ 168 169 typedef struct FDCtrl FDCtrl; 170 171 /* Floppy disk drive emulation */ 172 typedef enum FDiskFlags { 173 FDISK_DBL_SIDES = 0x01, 174 } FDiskFlags; 175 176 typedef struct FDrive { 177 FDCtrl *fdctrl; 178 BlockDriverState *bs; 179 /* Drive status */ 180 FDriveType drive; 181 uint8_t perpendicular; /* 2.88 MB access mode */ 182 /* Position */ 183 uint8_t head; 184 uint8_t track; 185 uint8_t sect; 186 /* Media */ 187 FDiskFlags flags; 188 uint8_t last_sect; /* Nb sector per track */ 189 uint8_t max_track; /* Nb of tracks */ 190 uint16_t bps; /* Bytes per sector */ 191 uint8_t ro; /* Is read-only */ 192 uint8_t media_changed; /* Is media changed */ 193 uint8_t media_rate; /* Data rate of medium */ 194 } FDrive; 195 196 static void fd_init(FDrive *drv) 197 { 198 /* Drive */ 199 drv->drive = FDRIVE_DRV_NONE; 200 drv->perpendicular = 0; 201 /* Disk */ 202 drv->last_sect = 0; 203 drv->max_track = 0; 204 } 205 206 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) 207 208 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, 209 uint8_t last_sect, uint8_t num_sides) 210 { 211 return (((track * num_sides) + head) * last_sect) + sect - 1; 212 } 213 214 /* Returns current position, in sectors, for given drive */ 215 static int fd_sector(FDrive *drv) 216 { 217 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, 218 NUM_SIDES(drv)); 219 } 220 221 /* Seek to a new position: 222 * returns 0 if already on right track 223 * returns 1 if track changed 224 * returns 2 if track is invalid 225 * returns 3 if sector is invalid 226 * returns 4 if seek is disabled 227 */ 228 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, 229 int enable_seek) 230 { 231 uint32_t sector; 232 int ret; 233 234 if (track > drv->max_track || 235 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { 236 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 237 head, track, sect, 1, 238 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 239 drv->max_track, drv->last_sect); 240 return 2; 241 } 242 if (sect > drv->last_sect) { 243 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 244 head, track, sect, 1, 245 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 246 drv->max_track, drv->last_sect); 247 return 3; 248 } 249 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); 250 ret = 0; 251 if (sector != fd_sector(drv)) { 252 #if 0 253 if (!enable_seek) { 254 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x" 255 " (max=%d %02x %02x)\n", 256 head, track, sect, 1, drv->max_track, 257 drv->last_sect); 258 return 4; 259 } 260 #endif 261 drv->head = head; 262 if (drv->track != track) { 263 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) { 264 drv->media_changed = 0; 265 } 266 ret = 1; 267 } 268 drv->track = track; 269 drv->sect = sect; 270 } 271 272 if (drv->bs == NULL || !bdrv_is_inserted(drv->bs)) { 273 ret = 2; 274 } 275 276 return ret; 277 } 278 279 /* Set drive back to track 0 */ 280 static void fd_recalibrate(FDrive *drv) 281 { 282 FLOPPY_DPRINTF("recalibrate\n"); 283 fd_seek(drv, 0, 0, 1, 1); 284 } 285 286 /* Revalidate a disk drive after a disk change */ 287 static void fd_revalidate(FDrive *drv) 288 { 289 int nb_heads, max_track, last_sect, ro; 290 FDriveType drive; 291 FDriveRate rate; 292 293 FLOPPY_DPRINTF("revalidate\n"); 294 if (drv->bs != NULL) { 295 ro = bdrv_is_read_only(drv->bs); 296 pick_geometry(drv->bs, &nb_heads, &max_track, 297 &last_sect, drv->drive, &drive, &rate); 298 if (!bdrv_is_inserted(drv->bs)) { 299 FLOPPY_DPRINTF("No disk in drive\n"); 300 } else { 301 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads, 302 max_track, last_sect, ro ? "ro" : "rw"); 303 } 304 if (nb_heads == 1) { 305 drv->flags &= ~FDISK_DBL_SIDES; 306 } else { 307 drv->flags |= FDISK_DBL_SIDES; 308 } 309 drv->max_track = max_track; 310 drv->last_sect = last_sect; 311 drv->ro = ro; 312 drv->drive = drive; 313 drv->media_rate = rate; 314 } else { 315 FLOPPY_DPRINTF("No drive connected\n"); 316 drv->last_sect = 0; 317 drv->max_track = 0; 318 drv->flags &= ~FDISK_DBL_SIDES; 319 } 320 } 321 322 /********************************************************/ 323 /* Intel 82078 floppy disk controller emulation */ 324 325 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); 326 static void fdctrl_reset_fifo(FDCtrl *fdctrl); 327 static int fdctrl_transfer_handler (void *opaque, int nchan, 328 int dma_pos, int dma_len); 329 static void fdctrl_raise_irq(FDCtrl *fdctrl); 330 static FDrive *get_cur_drv(FDCtrl *fdctrl); 331 332 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); 333 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); 334 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); 335 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); 336 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); 337 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); 338 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); 339 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); 340 static uint32_t fdctrl_read_data(FDCtrl *fdctrl); 341 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); 342 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); 343 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); 344 345 enum { 346 FD_DIR_WRITE = 0, 347 FD_DIR_READ = 1, 348 FD_DIR_SCANE = 2, 349 FD_DIR_SCANL = 3, 350 FD_DIR_SCANH = 4, 351 FD_DIR_VERIFY = 5, 352 }; 353 354 enum { 355 FD_STATE_MULTI = 0x01, /* multi track flag */ 356 FD_STATE_FORMAT = 0x02, /* format flag */ 357 }; 358 359 enum { 360 FD_REG_SRA = 0x00, 361 FD_REG_SRB = 0x01, 362 FD_REG_DOR = 0x02, 363 FD_REG_TDR = 0x03, 364 FD_REG_MSR = 0x04, 365 FD_REG_DSR = 0x04, 366 FD_REG_FIFO = 0x05, 367 FD_REG_DIR = 0x07, 368 FD_REG_CCR = 0x07, 369 }; 370 371 enum { 372 FD_CMD_READ_TRACK = 0x02, 373 FD_CMD_SPECIFY = 0x03, 374 FD_CMD_SENSE_DRIVE_STATUS = 0x04, 375 FD_CMD_WRITE = 0x05, 376 FD_CMD_READ = 0x06, 377 FD_CMD_RECALIBRATE = 0x07, 378 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, 379 FD_CMD_WRITE_DELETED = 0x09, 380 FD_CMD_READ_ID = 0x0a, 381 FD_CMD_READ_DELETED = 0x0c, 382 FD_CMD_FORMAT_TRACK = 0x0d, 383 FD_CMD_DUMPREG = 0x0e, 384 FD_CMD_SEEK = 0x0f, 385 FD_CMD_VERSION = 0x10, 386 FD_CMD_SCAN_EQUAL = 0x11, 387 FD_CMD_PERPENDICULAR_MODE = 0x12, 388 FD_CMD_CONFIGURE = 0x13, 389 FD_CMD_LOCK = 0x14, 390 FD_CMD_VERIFY = 0x16, 391 FD_CMD_POWERDOWN_MODE = 0x17, 392 FD_CMD_PART_ID = 0x18, 393 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, 394 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, 395 FD_CMD_SAVE = 0x2e, 396 FD_CMD_OPTION = 0x33, 397 FD_CMD_RESTORE = 0x4e, 398 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, 399 FD_CMD_RELATIVE_SEEK_OUT = 0x8f, 400 FD_CMD_FORMAT_AND_WRITE = 0xcd, 401 FD_CMD_RELATIVE_SEEK_IN = 0xcf, 402 }; 403 404 enum { 405 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ 406 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ 407 FD_CONFIG_POLL = 0x10, /* Poll enabled */ 408 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ 409 FD_CONFIG_EIS = 0x40, /* No implied seeks */ 410 }; 411 412 enum { 413 FD_SR0_DS0 = 0x01, 414 FD_SR0_DS1 = 0x02, 415 FD_SR0_HEAD = 0x04, 416 FD_SR0_EQPMT = 0x10, 417 FD_SR0_SEEK = 0x20, 418 FD_SR0_ABNTERM = 0x40, 419 FD_SR0_INVCMD = 0x80, 420 FD_SR0_RDYCHG = 0xc0, 421 }; 422 423 enum { 424 FD_SR1_MA = 0x01, /* Missing address mark */ 425 FD_SR1_NW = 0x02, /* Not writable */ 426 FD_SR1_EC = 0x80, /* End of cylinder */ 427 }; 428 429 enum { 430 FD_SR2_SNS = 0x04, /* Scan not satisfied */ 431 FD_SR2_SEH = 0x08, /* Scan equal hit */ 432 }; 433 434 enum { 435 FD_SRA_DIR = 0x01, 436 FD_SRA_nWP = 0x02, 437 FD_SRA_nINDX = 0x04, 438 FD_SRA_HDSEL = 0x08, 439 FD_SRA_nTRK0 = 0x10, 440 FD_SRA_STEP = 0x20, 441 FD_SRA_nDRV2 = 0x40, 442 FD_SRA_INTPEND = 0x80, 443 }; 444 445 enum { 446 FD_SRB_MTR0 = 0x01, 447 FD_SRB_MTR1 = 0x02, 448 FD_SRB_WGATE = 0x04, 449 FD_SRB_RDATA = 0x08, 450 FD_SRB_WDATA = 0x10, 451 FD_SRB_DR0 = 0x20, 452 }; 453 454 enum { 455 #if MAX_FD == 4 456 FD_DOR_SELMASK = 0x03, 457 #else 458 FD_DOR_SELMASK = 0x01, 459 #endif 460 FD_DOR_nRESET = 0x04, 461 FD_DOR_DMAEN = 0x08, 462 FD_DOR_MOTEN0 = 0x10, 463 FD_DOR_MOTEN1 = 0x20, 464 FD_DOR_MOTEN2 = 0x40, 465 FD_DOR_MOTEN3 = 0x80, 466 }; 467 468 enum { 469 #if MAX_FD == 4 470 FD_TDR_BOOTSEL = 0x0c, 471 #else 472 FD_TDR_BOOTSEL = 0x04, 473 #endif 474 }; 475 476 enum { 477 FD_DSR_DRATEMASK= 0x03, 478 FD_DSR_PWRDOWN = 0x40, 479 FD_DSR_SWRESET = 0x80, 480 }; 481 482 enum { 483 FD_MSR_DRV0BUSY = 0x01, 484 FD_MSR_DRV1BUSY = 0x02, 485 FD_MSR_DRV2BUSY = 0x04, 486 FD_MSR_DRV3BUSY = 0x08, 487 FD_MSR_CMDBUSY = 0x10, 488 FD_MSR_NONDMA = 0x20, 489 FD_MSR_DIO = 0x40, 490 FD_MSR_RQM = 0x80, 491 }; 492 493 enum { 494 FD_DIR_DSKCHG = 0x80, 495 }; 496 497 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) 498 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) 499 500 struct FDCtrl { 501 MemoryRegion iomem; 502 qemu_irq irq; 503 /* Controller state */ 504 QEMUTimer *result_timer; 505 int dma_chann; 506 /* Controller's identification */ 507 uint8_t version; 508 /* HW */ 509 uint8_t sra; 510 uint8_t srb; 511 uint8_t dor; 512 uint8_t dor_vmstate; /* only used as temp during vmstate */ 513 uint8_t tdr; 514 uint8_t dsr; 515 uint8_t msr; 516 uint8_t cur_drv; 517 uint8_t status0; 518 uint8_t status1; 519 uint8_t status2; 520 /* Command FIFO */ 521 uint8_t *fifo; 522 int32_t fifo_size; 523 uint32_t data_pos; 524 uint32_t data_len; 525 uint8_t data_state; 526 uint8_t data_dir; 527 uint8_t eot; /* last wanted sector */ 528 /* States kept only to be returned back */ 529 /* precompensation */ 530 uint8_t precomp_trk; 531 uint8_t config; 532 uint8_t lock; 533 /* Power down config (also with status regB access mode */ 534 uint8_t pwrd; 535 /* Floppy drives */ 536 uint8_t num_floppies; 537 /* Sun4m quirks? */ 538 int sun4m; 539 FDrive drives[MAX_FD]; 540 int reset_sensei; 541 uint32_t check_media_rate; 542 /* Timers state */ 543 uint8_t timer0; 544 uint8_t timer1; 545 }; 546 547 typedef struct FDCtrlSysBus { 548 SysBusDevice busdev; 549 struct FDCtrl state; 550 } FDCtrlSysBus; 551 552 typedef struct FDCtrlISABus { 553 ISADevice busdev; 554 uint32_t iobase; 555 uint32_t irq; 556 uint32_t dma; 557 struct FDCtrl state; 558 int32_t bootindexA; 559 int32_t bootindexB; 560 } FDCtrlISABus; 561 562 static uint32_t fdctrl_read (void *opaque, uint32_t reg) 563 { 564 FDCtrl *fdctrl = opaque; 565 uint32_t retval; 566 567 reg &= 7; 568 switch (reg) { 569 case FD_REG_SRA: 570 retval = fdctrl_read_statusA(fdctrl); 571 break; 572 case FD_REG_SRB: 573 retval = fdctrl_read_statusB(fdctrl); 574 break; 575 case FD_REG_DOR: 576 retval = fdctrl_read_dor(fdctrl); 577 break; 578 case FD_REG_TDR: 579 retval = fdctrl_read_tape(fdctrl); 580 break; 581 case FD_REG_MSR: 582 retval = fdctrl_read_main_status(fdctrl); 583 break; 584 case FD_REG_FIFO: 585 retval = fdctrl_read_data(fdctrl); 586 break; 587 case FD_REG_DIR: 588 retval = fdctrl_read_dir(fdctrl); 589 break; 590 default: 591 retval = (uint32_t)(-1); 592 break; 593 } 594 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); 595 596 return retval; 597 } 598 599 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) 600 { 601 FDCtrl *fdctrl = opaque; 602 603 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); 604 605 reg &= 7; 606 switch (reg) { 607 case FD_REG_DOR: 608 fdctrl_write_dor(fdctrl, value); 609 break; 610 case FD_REG_TDR: 611 fdctrl_write_tape(fdctrl, value); 612 break; 613 case FD_REG_DSR: 614 fdctrl_write_rate(fdctrl, value); 615 break; 616 case FD_REG_FIFO: 617 fdctrl_write_data(fdctrl, value); 618 break; 619 case FD_REG_CCR: 620 fdctrl_write_ccr(fdctrl, value); 621 break; 622 default: 623 break; 624 } 625 } 626 627 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg, 628 unsigned ize) 629 { 630 return fdctrl_read(opaque, (uint32_t)reg); 631 } 632 633 static void fdctrl_write_mem (void *opaque, hwaddr reg, 634 uint64_t value, unsigned size) 635 { 636 fdctrl_write(opaque, (uint32_t)reg, value); 637 } 638 639 static const MemoryRegionOps fdctrl_mem_ops = { 640 .read = fdctrl_read_mem, 641 .write = fdctrl_write_mem, 642 .endianness = DEVICE_NATIVE_ENDIAN, 643 }; 644 645 static const MemoryRegionOps fdctrl_mem_strict_ops = { 646 .read = fdctrl_read_mem, 647 .write = fdctrl_write_mem, 648 .endianness = DEVICE_NATIVE_ENDIAN, 649 .valid = { 650 .min_access_size = 1, 651 .max_access_size = 1, 652 }, 653 }; 654 655 static bool fdrive_media_changed_needed(void *opaque) 656 { 657 FDrive *drive = opaque; 658 659 return (drive->bs != NULL && drive->media_changed != 1); 660 } 661 662 static const VMStateDescription vmstate_fdrive_media_changed = { 663 .name = "fdrive/media_changed", 664 .version_id = 1, 665 .minimum_version_id = 1, 666 .minimum_version_id_old = 1, 667 .fields = (VMStateField[]) { 668 VMSTATE_UINT8(media_changed, FDrive), 669 VMSTATE_END_OF_LIST() 670 } 671 }; 672 673 static bool fdrive_media_rate_needed(void *opaque) 674 { 675 FDrive *drive = opaque; 676 677 return drive->fdctrl->check_media_rate; 678 } 679 680 static const VMStateDescription vmstate_fdrive_media_rate = { 681 .name = "fdrive/media_rate", 682 .version_id = 1, 683 .minimum_version_id = 1, 684 .minimum_version_id_old = 1, 685 .fields = (VMStateField[]) { 686 VMSTATE_UINT8(media_rate, FDrive), 687 VMSTATE_END_OF_LIST() 688 } 689 }; 690 691 static const VMStateDescription vmstate_fdrive = { 692 .name = "fdrive", 693 .version_id = 1, 694 .minimum_version_id = 1, 695 .minimum_version_id_old = 1, 696 .fields = (VMStateField[]) { 697 VMSTATE_UINT8(head, FDrive), 698 VMSTATE_UINT8(track, FDrive), 699 VMSTATE_UINT8(sect, FDrive), 700 VMSTATE_END_OF_LIST() 701 }, 702 .subsections = (VMStateSubsection[]) { 703 { 704 .vmsd = &vmstate_fdrive_media_changed, 705 .needed = &fdrive_media_changed_needed, 706 } , { 707 .vmsd = &vmstate_fdrive_media_rate, 708 .needed = &fdrive_media_rate_needed, 709 } , { 710 /* empty */ 711 } 712 } 713 }; 714 715 static void fdc_pre_save(void *opaque) 716 { 717 FDCtrl *s = opaque; 718 719 s->dor_vmstate = s->dor | GET_CUR_DRV(s); 720 } 721 722 static int fdc_post_load(void *opaque, int version_id) 723 { 724 FDCtrl *s = opaque; 725 726 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); 727 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; 728 return 0; 729 } 730 731 static const VMStateDescription vmstate_fdc = { 732 .name = "fdc", 733 .version_id = 2, 734 .minimum_version_id = 2, 735 .minimum_version_id_old = 2, 736 .pre_save = fdc_pre_save, 737 .post_load = fdc_post_load, 738 .fields = (VMStateField []) { 739 /* Controller State */ 740 VMSTATE_UINT8(sra, FDCtrl), 741 VMSTATE_UINT8(srb, FDCtrl), 742 VMSTATE_UINT8(dor_vmstate, FDCtrl), 743 VMSTATE_UINT8(tdr, FDCtrl), 744 VMSTATE_UINT8(dsr, FDCtrl), 745 VMSTATE_UINT8(msr, FDCtrl), 746 VMSTATE_UINT8(status0, FDCtrl), 747 VMSTATE_UINT8(status1, FDCtrl), 748 VMSTATE_UINT8(status2, FDCtrl), 749 /* Command FIFO */ 750 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, 751 uint8_t), 752 VMSTATE_UINT32(data_pos, FDCtrl), 753 VMSTATE_UINT32(data_len, FDCtrl), 754 VMSTATE_UINT8(data_state, FDCtrl), 755 VMSTATE_UINT8(data_dir, FDCtrl), 756 VMSTATE_UINT8(eot, FDCtrl), 757 /* States kept only to be returned back */ 758 VMSTATE_UINT8(timer0, FDCtrl), 759 VMSTATE_UINT8(timer1, FDCtrl), 760 VMSTATE_UINT8(precomp_trk, FDCtrl), 761 VMSTATE_UINT8(config, FDCtrl), 762 VMSTATE_UINT8(lock, FDCtrl), 763 VMSTATE_UINT8(pwrd, FDCtrl), 764 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl), 765 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, 766 vmstate_fdrive, FDrive), 767 VMSTATE_END_OF_LIST() 768 } 769 }; 770 771 static void fdctrl_external_reset_sysbus(DeviceState *d) 772 { 773 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev); 774 FDCtrl *s = &sys->state; 775 776 fdctrl_reset(s, 0); 777 } 778 779 static void fdctrl_external_reset_isa(DeviceState *d) 780 { 781 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev); 782 FDCtrl *s = &isa->state; 783 784 fdctrl_reset(s, 0); 785 } 786 787 static void fdctrl_handle_tc(void *opaque, int irq, int level) 788 { 789 //FDCtrl *s = opaque; 790 791 if (level) { 792 // XXX 793 FLOPPY_DPRINTF("TC pulsed\n"); 794 } 795 } 796 797 /* Change IRQ state */ 798 static void fdctrl_reset_irq(FDCtrl *fdctrl) 799 { 800 fdctrl->status0 = 0; 801 if (!(fdctrl->sra & FD_SRA_INTPEND)) 802 return; 803 FLOPPY_DPRINTF("Reset interrupt\n"); 804 qemu_set_irq(fdctrl->irq, 0); 805 fdctrl->sra &= ~FD_SRA_INTPEND; 806 } 807 808 static void fdctrl_raise_irq(FDCtrl *fdctrl) 809 { 810 /* Sparc mutation */ 811 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) { 812 /* XXX: not sure */ 813 fdctrl->msr &= ~FD_MSR_CMDBUSY; 814 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 815 return; 816 } 817 if (!(fdctrl->sra & FD_SRA_INTPEND)) { 818 qemu_set_irq(fdctrl->irq, 1); 819 fdctrl->sra |= FD_SRA_INTPEND; 820 } 821 822 fdctrl->reset_sensei = 0; 823 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); 824 } 825 826 /* Reset controller */ 827 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) 828 { 829 int i; 830 831 FLOPPY_DPRINTF("reset controller\n"); 832 fdctrl_reset_irq(fdctrl); 833 /* Initialise controller */ 834 fdctrl->sra = 0; 835 fdctrl->srb = 0xc0; 836 if (!fdctrl->drives[1].bs) 837 fdctrl->sra |= FD_SRA_nDRV2; 838 fdctrl->cur_drv = 0; 839 fdctrl->dor = FD_DOR_nRESET; 840 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; 841 fdctrl->msr = FD_MSR_RQM; 842 /* FIFO state */ 843 fdctrl->data_pos = 0; 844 fdctrl->data_len = 0; 845 fdctrl->data_state = 0; 846 fdctrl->data_dir = FD_DIR_WRITE; 847 for (i = 0; i < MAX_FD; i++) 848 fd_recalibrate(&fdctrl->drives[i]); 849 fdctrl_reset_fifo(fdctrl); 850 if (do_irq) { 851 fdctrl->status0 |= FD_SR0_RDYCHG; 852 fdctrl_raise_irq(fdctrl); 853 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; 854 } 855 } 856 857 static inline FDrive *drv0(FDCtrl *fdctrl) 858 { 859 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; 860 } 861 862 static inline FDrive *drv1(FDCtrl *fdctrl) 863 { 864 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) 865 return &fdctrl->drives[1]; 866 else 867 return &fdctrl->drives[0]; 868 } 869 870 #if MAX_FD == 4 871 static inline FDrive *drv2(FDCtrl *fdctrl) 872 { 873 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) 874 return &fdctrl->drives[2]; 875 else 876 return &fdctrl->drives[1]; 877 } 878 879 static inline FDrive *drv3(FDCtrl *fdctrl) 880 { 881 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) 882 return &fdctrl->drives[3]; 883 else 884 return &fdctrl->drives[2]; 885 } 886 #endif 887 888 static FDrive *get_cur_drv(FDCtrl *fdctrl) 889 { 890 switch (fdctrl->cur_drv) { 891 case 0: return drv0(fdctrl); 892 case 1: return drv1(fdctrl); 893 #if MAX_FD == 4 894 case 2: return drv2(fdctrl); 895 case 3: return drv3(fdctrl); 896 #endif 897 default: return NULL; 898 } 899 } 900 901 /* Status A register : 0x00 (read-only) */ 902 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) 903 { 904 uint32_t retval = fdctrl->sra; 905 906 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); 907 908 return retval; 909 } 910 911 /* Status B register : 0x01 (read-only) */ 912 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) 913 { 914 uint32_t retval = fdctrl->srb; 915 916 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); 917 918 return retval; 919 } 920 921 /* Digital output register : 0x02 */ 922 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) 923 { 924 uint32_t retval = fdctrl->dor; 925 926 /* Selected drive */ 927 retval |= fdctrl->cur_drv; 928 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); 929 930 return retval; 931 } 932 933 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) 934 { 935 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); 936 937 /* Motors */ 938 if (value & FD_DOR_MOTEN0) 939 fdctrl->srb |= FD_SRB_MTR0; 940 else 941 fdctrl->srb &= ~FD_SRB_MTR0; 942 if (value & FD_DOR_MOTEN1) 943 fdctrl->srb |= FD_SRB_MTR1; 944 else 945 fdctrl->srb &= ~FD_SRB_MTR1; 946 947 /* Drive */ 948 if (value & 1) 949 fdctrl->srb |= FD_SRB_DR0; 950 else 951 fdctrl->srb &= ~FD_SRB_DR0; 952 953 /* Reset */ 954 if (!(value & FD_DOR_nRESET)) { 955 if (fdctrl->dor & FD_DOR_nRESET) { 956 FLOPPY_DPRINTF("controller enter RESET state\n"); 957 } 958 } else { 959 if (!(fdctrl->dor & FD_DOR_nRESET)) { 960 FLOPPY_DPRINTF("controller out of RESET state\n"); 961 fdctrl_reset(fdctrl, 1); 962 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 963 } 964 } 965 /* Selected drive */ 966 fdctrl->cur_drv = value & FD_DOR_SELMASK; 967 968 fdctrl->dor = value; 969 } 970 971 /* Tape drive register : 0x03 */ 972 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) 973 { 974 uint32_t retval = fdctrl->tdr; 975 976 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); 977 978 return retval; 979 } 980 981 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) 982 { 983 /* Reset mode */ 984 if (!(fdctrl->dor & FD_DOR_nRESET)) { 985 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 986 return; 987 } 988 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); 989 /* Disk boot selection indicator */ 990 fdctrl->tdr = value & FD_TDR_BOOTSEL; 991 /* Tape indicators: never allow */ 992 } 993 994 /* Main status register : 0x04 (read) */ 995 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) 996 { 997 uint32_t retval = fdctrl->msr; 998 999 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1000 fdctrl->dor |= FD_DOR_nRESET; 1001 1002 /* Sparc mutation */ 1003 if (fdctrl->sun4m) { 1004 retval |= FD_MSR_DIO; 1005 fdctrl_reset_irq(fdctrl); 1006 }; 1007 1008 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); 1009 1010 return retval; 1011 } 1012 1013 /* Data select rate register : 0x04 (write) */ 1014 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) 1015 { 1016 /* Reset mode */ 1017 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1018 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1019 return; 1020 } 1021 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); 1022 /* Reset: autoclear */ 1023 if (value & FD_DSR_SWRESET) { 1024 fdctrl->dor &= ~FD_DOR_nRESET; 1025 fdctrl_reset(fdctrl, 1); 1026 fdctrl->dor |= FD_DOR_nRESET; 1027 } 1028 if (value & FD_DSR_PWRDOWN) { 1029 fdctrl_reset(fdctrl, 1); 1030 } 1031 fdctrl->dsr = value; 1032 } 1033 1034 /* Configuration control register: 0x07 (write) */ 1035 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) 1036 { 1037 /* Reset mode */ 1038 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1039 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1040 return; 1041 } 1042 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); 1043 1044 /* Only the rate selection bits used in AT mode, and we 1045 * store those in the DSR. 1046 */ 1047 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | 1048 (value & FD_DSR_DRATEMASK); 1049 } 1050 1051 static int fdctrl_media_changed(FDrive *drv) 1052 { 1053 return drv->media_changed; 1054 } 1055 1056 /* Digital input register : 0x07 (read-only) */ 1057 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) 1058 { 1059 uint32_t retval = 0; 1060 1061 if (fdctrl_media_changed(get_cur_drv(fdctrl))) { 1062 retval |= FD_DIR_DSKCHG; 1063 } 1064 if (retval != 0) { 1065 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); 1066 } 1067 1068 return retval; 1069 } 1070 1071 /* FIFO state control */ 1072 static void fdctrl_reset_fifo(FDCtrl *fdctrl) 1073 { 1074 fdctrl->data_dir = FD_DIR_WRITE; 1075 fdctrl->data_pos = 0; 1076 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); 1077 } 1078 1079 /* Set FIFO status for the host to read */ 1080 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len) 1081 { 1082 fdctrl->data_dir = FD_DIR_READ; 1083 fdctrl->data_len = fifo_len; 1084 fdctrl->data_pos = 0; 1085 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; 1086 } 1087 1088 /* Set an error: unimplemented/unknown command */ 1089 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) 1090 { 1091 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n", 1092 fdctrl->fifo[0]); 1093 fdctrl->fifo[0] = FD_SR0_INVCMD; 1094 fdctrl_set_fifo(fdctrl, 1); 1095 } 1096 1097 /* Seek to next sector 1098 * returns 0 when end of track reached (for DBL_SIDES on head 1) 1099 * otherwise returns 1 1100 */ 1101 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) 1102 { 1103 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", 1104 cur_drv->head, cur_drv->track, cur_drv->sect, 1105 fd_sector(cur_drv)); 1106 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an 1107 error in fact */ 1108 uint8_t new_head = cur_drv->head; 1109 uint8_t new_track = cur_drv->track; 1110 uint8_t new_sect = cur_drv->sect; 1111 1112 int ret = 1; 1113 1114 if (new_sect >= cur_drv->last_sect || 1115 new_sect == fdctrl->eot) { 1116 new_sect = 1; 1117 if (FD_MULTI_TRACK(fdctrl->data_state)) { 1118 if (new_head == 0 && 1119 (cur_drv->flags & FDISK_DBL_SIDES) != 0) { 1120 new_head = 1; 1121 } else { 1122 new_head = 0; 1123 new_track++; 1124 fdctrl->status0 |= FD_SR0_SEEK; 1125 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) { 1126 ret = 0; 1127 } 1128 } 1129 } else { 1130 fdctrl->status0 |= FD_SR0_SEEK; 1131 new_track++; 1132 ret = 0; 1133 } 1134 if (ret == 1) { 1135 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", 1136 new_head, new_track, new_sect, fd_sector(cur_drv)); 1137 } 1138 } else { 1139 new_sect++; 1140 } 1141 fd_seek(cur_drv, new_head, new_track, new_sect, 1); 1142 return ret; 1143 } 1144 1145 /* Callback for transfer end (stop or abort) */ 1146 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, 1147 uint8_t status1, uint8_t status2) 1148 { 1149 FDrive *cur_drv; 1150 cur_drv = get_cur_drv(fdctrl); 1151 1152 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD); 1153 fdctrl->status0 |= GET_CUR_DRV(fdctrl); 1154 if (cur_drv->head) { 1155 fdctrl->status0 |= FD_SR0_HEAD; 1156 } 1157 fdctrl->status0 |= status0; 1158 1159 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", 1160 status0, status1, status2, fdctrl->status0); 1161 fdctrl->fifo[0] = fdctrl->status0; 1162 fdctrl->fifo[1] = status1; 1163 fdctrl->fifo[2] = status2; 1164 fdctrl->fifo[3] = cur_drv->track; 1165 fdctrl->fifo[4] = cur_drv->head; 1166 fdctrl->fifo[5] = cur_drv->sect; 1167 fdctrl->fifo[6] = FD_SECTOR_SC; 1168 fdctrl->data_dir = FD_DIR_READ; 1169 if (!(fdctrl->msr & FD_MSR_NONDMA)) { 1170 DMA_release_DREQ(fdctrl->dma_chann); 1171 } 1172 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 1173 fdctrl->msr &= ~FD_MSR_NONDMA; 1174 1175 fdctrl_set_fifo(fdctrl, 7); 1176 fdctrl_raise_irq(fdctrl); 1177 } 1178 1179 /* Prepare a data transfer (either DMA or FIFO) */ 1180 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) 1181 { 1182 FDrive *cur_drv; 1183 uint8_t kh, kt, ks; 1184 1185 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1186 cur_drv = get_cur_drv(fdctrl); 1187 kt = fdctrl->fifo[2]; 1188 kh = fdctrl->fifo[3]; 1189 ks = fdctrl->fifo[4]; 1190 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", 1191 GET_CUR_DRV(fdctrl), kh, kt, ks, 1192 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1193 NUM_SIDES(cur_drv))); 1194 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1195 case 2: 1196 /* sect too big */ 1197 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1198 fdctrl->fifo[3] = kt; 1199 fdctrl->fifo[4] = kh; 1200 fdctrl->fifo[5] = ks; 1201 return; 1202 case 3: 1203 /* track too big */ 1204 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1205 fdctrl->fifo[3] = kt; 1206 fdctrl->fifo[4] = kh; 1207 fdctrl->fifo[5] = ks; 1208 return; 1209 case 4: 1210 /* No seek enabled */ 1211 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1212 fdctrl->fifo[3] = kt; 1213 fdctrl->fifo[4] = kh; 1214 fdctrl->fifo[5] = ks; 1215 return; 1216 case 1: 1217 fdctrl->status0 |= FD_SR0_SEEK; 1218 break; 1219 default: 1220 break; 1221 } 1222 1223 /* Check the data rate. If the programmed data rate does not match 1224 * the currently inserted medium, the operation has to fail. */ 1225 if (fdctrl->check_media_rate && 1226 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 1227 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n", 1228 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 1229 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 1230 fdctrl->fifo[3] = kt; 1231 fdctrl->fifo[4] = kh; 1232 fdctrl->fifo[5] = ks; 1233 return; 1234 } 1235 1236 /* Set the FIFO state */ 1237 fdctrl->data_dir = direction; 1238 fdctrl->data_pos = 0; 1239 assert(fdctrl->msr & FD_MSR_CMDBUSY); 1240 if (fdctrl->fifo[0] & 0x80) 1241 fdctrl->data_state |= FD_STATE_MULTI; 1242 else 1243 fdctrl->data_state &= ~FD_STATE_MULTI; 1244 if (fdctrl->fifo[5] == 0) { 1245 fdctrl->data_len = fdctrl->fifo[8]; 1246 } else { 1247 int tmp; 1248 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); 1249 tmp = (fdctrl->fifo[6] - ks + 1); 1250 if (fdctrl->fifo[0] & 0x80) 1251 tmp += fdctrl->fifo[6]; 1252 fdctrl->data_len *= tmp; 1253 } 1254 fdctrl->eot = fdctrl->fifo[6]; 1255 if (fdctrl->dor & FD_DOR_DMAEN) { 1256 int dma_mode; 1257 /* DMA transfer are enabled. Check if DMA channel is well programmed */ 1258 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); 1259 dma_mode = (dma_mode >> 2) & 3; 1260 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", 1261 dma_mode, direction, 1262 (128 << fdctrl->fifo[5]) * 1263 (cur_drv->last_sect - ks + 1), fdctrl->data_len); 1264 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL || 1265 direction == FD_DIR_SCANH) && dma_mode == 0) || 1266 (direction == FD_DIR_WRITE && dma_mode == 2) || 1267 (direction == FD_DIR_READ && dma_mode == 1) || 1268 (direction == FD_DIR_VERIFY)) { 1269 /* No access is allowed until DMA transfer has completed */ 1270 fdctrl->msr &= ~FD_MSR_RQM; 1271 if (direction != FD_DIR_VERIFY) { 1272 /* Now, we just have to wait for the DMA controller to 1273 * recall us... 1274 */ 1275 DMA_hold_DREQ(fdctrl->dma_chann); 1276 DMA_schedule(fdctrl->dma_chann); 1277 } else { 1278 /* Start transfer */ 1279 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, 1280 fdctrl->data_len); 1281 } 1282 return; 1283 } else { 1284 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode, 1285 direction); 1286 } 1287 } 1288 FLOPPY_DPRINTF("start non-DMA transfer\n"); 1289 fdctrl->msr |= FD_MSR_NONDMA; 1290 if (direction != FD_DIR_WRITE) 1291 fdctrl->msr |= FD_MSR_DIO; 1292 /* IO based transfer: calculate len */ 1293 fdctrl_raise_irq(fdctrl); 1294 } 1295 1296 /* Prepare a transfer of deleted data */ 1297 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) 1298 { 1299 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n"); 1300 1301 /* We don't handle deleted data, 1302 * so we don't return *ANYTHING* 1303 */ 1304 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1305 } 1306 1307 /* handlers for DMA transfers */ 1308 static int fdctrl_transfer_handler (void *opaque, int nchan, 1309 int dma_pos, int dma_len) 1310 { 1311 FDCtrl *fdctrl; 1312 FDrive *cur_drv; 1313 int len, start_pos, rel_pos; 1314 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; 1315 1316 fdctrl = opaque; 1317 if (fdctrl->msr & FD_MSR_RQM) { 1318 FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); 1319 return 0; 1320 } 1321 cur_drv = get_cur_drv(fdctrl); 1322 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || 1323 fdctrl->data_dir == FD_DIR_SCANH) 1324 status2 = FD_SR2_SNS; 1325 if (dma_len > fdctrl->data_len) 1326 dma_len = fdctrl->data_len; 1327 if (cur_drv->bs == NULL) { 1328 if (fdctrl->data_dir == FD_DIR_WRITE) 1329 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1330 else 1331 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1332 len = 0; 1333 goto transfer_error; 1334 } 1335 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1336 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { 1337 len = dma_len - fdctrl->data_pos; 1338 if (len + rel_pos > FD_SECTOR_LEN) 1339 len = FD_SECTOR_LEN - rel_pos; 1340 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " 1341 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, 1342 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, 1343 cur_drv->track, cur_drv->sect, fd_sector(cur_drv), 1344 fd_sector(cur_drv) * FD_SECTOR_LEN); 1345 if (fdctrl->data_dir != FD_DIR_WRITE || 1346 len < FD_SECTOR_LEN || rel_pos != 0) { 1347 /* READ & SCAN commands and realign to a sector for WRITE */ 1348 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), 1349 fdctrl->fifo, 1) < 0) { 1350 FLOPPY_DPRINTF("Floppy: error getting sector %d\n", 1351 fd_sector(cur_drv)); 1352 /* Sure, image size is too small... */ 1353 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1354 } 1355 } 1356 switch (fdctrl->data_dir) { 1357 case FD_DIR_READ: 1358 /* READ commands */ 1359 DMA_write_memory (nchan, fdctrl->fifo + rel_pos, 1360 fdctrl->data_pos, len); 1361 break; 1362 case FD_DIR_WRITE: 1363 /* WRITE commands */ 1364 if (cur_drv->ro) { 1365 /* Handle readonly medium early, no need to do DMA, touch the 1366 * LED or attempt any writes. A real floppy doesn't attempt 1367 * to write to readonly media either. */ 1368 fdctrl_stop_transfer(fdctrl, 1369 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, 1370 0x00); 1371 goto transfer_error; 1372 } 1373 1374 DMA_read_memory (nchan, fdctrl->fifo + rel_pos, 1375 fdctrl->data_pos, len); 1376 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), 1377 fdctrl->fifo, 1) < 0) { 1378 FLOPPY_DPRINTF("error writing sector %d\n", 1379 fd_sector(cur_drv)); 1380 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1381 goto transfer_error; 1382 } 1383 break; 1384 case FD_DIR_VERIFY: 1385 /* VERIFY commands */ 1386 break; 1387 default: 1388 /* SCAN commands */ 1389 { 1390 uint8_t tmpbuf[FD_SECTOR_LEN]; 1391 int ret; 1392 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); 1393 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); 1394 if (ret == 0) { 1395 status2 = FD_SR2_SEH; 1396 goto end_transfer; 1397 } 1398 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || 1399 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { 1400 status2 = 0x00; 1401 goto end_transfer; 1402 } 1403 } 1404 break; 1405 } 1406 fdctrl->data_pos += len; 1407 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1408 if (rel_pos == 0) { 1409 /* Seek to next sector */ 1410 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) 1411 break; 1412 } 1413 } 1414 end_transfer: 1415 len = fdctrl->data_pos - start_pos; 1416 FLOPPY_DPRINTF("end transfer %d %d %d\n", 1417 fdctrl->data_pos, len, fdctrl->data_len); 1418 if (fdctrl->data_dir == FD_DIR_SCANE || 1419 fdctrl->data_dir == FD_DIR_SCANL || 1420 fdctrl->data_dir == FD_DIR_SCANH) 1421 status2 = FD_SR2_SEH; 1422 fdctrl->data_len -= len; 1423 fdctrl_stop_transfer(fdctrl, status0, status1, status2); 1424 transfer_error: 1425 1426 return len; 1427 } 1428 1429 /* Data register : 0x05 */ 1430 static uint32_t fdctrl_read_data(FDCtrl *fdctrl) 1431 { 1432 FDrive *cur_drv; 1433 uint32_t retval = 0; 1434 int pos; 1435 1436 cur_drv = get_cur_drv(fdctrl); 1437 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1438 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { 1439 FLOPPY_DPRINTF("error: controller not ready for reading\n"); 1440 return 0; 1441 } 1442 pos = fdctrl->data_pos; 1443 if (fdctrl->msr & FD_MSR_NONDMA) { 1444 pos %= FD_SECTOR_LEN; 1445 if (pos == 0) { 1446 if (fdctrl->data_pos != 0) 1447 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1448 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1449 fd_sector(cur_drv)); 1450 return 0; 1451 } 1452 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1453 FLOPPY_DPRINTF("error getting sector %d\n", 1454 fd_sector(cur_drv)); 1455 /* Sure, image size is too small... */ 1456 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1457 } 1458 } 1459 } 1460 retval = fdctrl->fifo[pos]; 1461 if (++fdctrl->data_pos == fdctrl->data_len) { 1462 fdctrl->data_pos = 0; 1463 /* Switch from transfer mode to status mode 1464 * then from status mode to command mode 1465 */ 1466 if (fdctrl->msr & FD_MSR_NONDMA) { 1467 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1468 } else { 1469 fdctrl_reset_fifo(fdctrl); 1470 fdctrl_reset_irq(fdctrl); 1471 } 1472 } 1473 FLOPPY_DPRINTF("data register: 0x%02x\n", retval); 1474 1475 return retval; 1476 } 1477 1478 static void fdctrl_format_sector(FDCtrl *fdctrl) 1479 { 1480 FDrive *cur_drv; 1481 uint8_t kh, kt, ks; 1482 1483 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1484 cur_drv = get_cur_drv(fdctrl); 1485 kt = fdctrl->fifo[6]; 1486 kh = fdctrl->fifo[7]; 1487 ks = fdctrl->fifo[8]; 1488 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", 1489 GET_CUR_DRV(fdctrl), kh, kt, ks, 1490 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1491 NUM_SIDES(cur_drv))); 1492 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1493 case 2: 1494 /* sect too big */ 1495 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1496 fdctrl->fifo[3] = kt; 1497 fdctrl->fifo[4] = kh; 1498 fdctrl->fifo[5] = ks; 1499 return; 1500 case 3: 1501 /* track too big */ 1502 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1503 fdctrl->fifo[3] = kt; 1504 fdctrl->fifo[4] = kh; 1505 fdctrl->fifo[5] = ks; 1506 return; 1507 case 4: 1508 /* No seek enabled */ 1509 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1510 fdctrl->fifo[3] = kt; 1511 fdctrl->fifo[4] = kh; 1512 fdctrl->fifo[5] = ks; 1513 return; 1514 case 1: 1515 fdctrl->status0 |= FD_SR0_SEEK; 1516 break; 1517 default: 1518 break; 1519 } 1520 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1521 if (cur_drv->bs == NULL || 1522 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1523 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv)); 1524 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1525 } else { 1526 if (cur_drv->sect == cur_drv->last_sect) { 1527 fdctrl->data_state &= ~FD_STATE_FORMAT; 1528 /* Last sector done */ 1529 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1530 } else { 1531 /* More to do */ 1532 fdctrl->data_pos = 0; 1533 fdctrl->data_len = 4; 1534 } 1535 } 1536 } 1537 1538 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) 1539 { 1540 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; 1541 fdctrl->fifo[0] = fdctrl->lock << 4; 1542 fdctrl_set_fifo(fdctrl, 1); 1543 } 1544 1545 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) 1546 { 1547 FDrive *cur_drv = get_cur_drv(fdctrl); 1548 1549 /* Drives position */ 1550 fdctrl->fifo[0] = drv0(fdctrl)->track; 1551 fdctrl->fifo[1] = drv1(fdctrl)->track; 1552 #if MAX_FD == 4 1553 fdctrl->fifo[2] = drv2(fdctrl)->track; 1554 fdctrl->fifo[3] = drv3(fdctrl)->track; 1555 #else 1556 fdctrl->fifo[2] = 0; 1557 fdctrl->fifo[3] = 0; 1558 #endif 1559 /* timers */ 1560 fdctrl->fifo[4] = fdctrl->timer0; 1561 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); 1562 fdctrl->fifo[6] = cur_drv->last_sect; 1563 fdctrl->fifo[7] = (fdctrl->lock << 7) | 1564 (cur_drv->perpendicular << 2); 1565 fdctrl->fifo[8] = fdctrl->config; 1566 fdctrl->fifo[9] = fdctrl->precomp_trk; 1567 fdctrl_set_fifo(fdctrl, 10); 1568 } 1569 1570 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) 1571 { 1572 /* Controller's version */ 1573 fdctrl->fifo[0] = fdctrl->version; 1574 fdctrl_set_fifo(fdctrl, 1); 1575 } 1576 1577 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) 1578 { 1579 fdctrl->fifo[0] = 0x41; /* Stepping 1 */ 1580 fdctrl_set_fifo(fdctrl, 1); 1581 } 1582 1583 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) 1584 { 1585 FDrive *cur_drv = get_cur_drv(fdctrl); 1586 1587 /* Drives position */ 1588 drv0(fdctrl)->track = fdctrl->fifo[3]; 1589 drv1(fdctrl)->track = fdctrl->fifo[4]; 1590 #if MAX_FD == 4 1591 drv2(fdctrl)->track = fdctrl->fifo[5]; 1592 drv3(fdctrl)->track = fdctrl->fifo[6]; 1593 #endif 1594 /* timers */ 1595 fdctrl->timer0 = fdctrl->fifo[7]; 1596 fdctrl->timer1 = fdctrl->fifo[8]; 1597 cur_drv->last_sect = fdctrl->fifo[9]; 1598 fdctrl->lock = fdctrl->fifo[10] >> 7; 1599 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; 1600 fdctrl->config = fdctrl->fifo[11]; 1601 fdctrl->precomp_trk = fdctrl->fifo[12]; 1602 fdctrl->pwrd = fdctrl->fifo[13]; 1603 fdctrl_reset_fifo(fdctrl); 1604 } 1605 1606 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) 1607 { 1608 FDrive *cur_drv = get_cur_drv(fdctrl); 1609 1610 fdctrl->fifo[0] = 0; 1611 fdctrl->fifo[1] = 0; 1612 /* Drives position */ 1613 fdctrl->fifo[2] = drv0(fdctrl)->track; 1614 fdctrl->fifo[3] = drv1(fdctrl)->track; 1615 #if MAX_FD == 4 1616 fdctrl->fifo[4] = drv2(fdctrl)->track; 1617 fdctrl->fifo[5] = drv3(fdctrl)->track; 1618 #else 1619 fdctrl->fifo[4] = 0; 1620 fdctrl->fifo[5] = 0; 1621 #endif 1622 /* timers */ 1623 fdctrl->fifo[6] = fdctrl->timer0; 1624 fdctrl->fifo[7] = fdctrl->timer1; 1625 fdctrl->fifo[8] = cur_drv->last_sect; 1626 fdctrl->fifo[9] = (fdctrl->lock << 7) | 1627 (cur_drv->perpendicular << 2); 1628 fdctrl->fifo[10] = fdctrl->config; 1629 fdctrl->fifo[11] = fdctrl->precomp_trk; 1630 fdctrl->fifo[12] = fdctrl->pwrd; 1631 fdctrl->fifo[13] = 0; 1632 fdctrl->fifo[14] = 0; 1633 fdctrl_set_fifo(fdctrl, 15); 1634 } 1635 1636 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) 1637 { 1638 FDrive *cur_drv = get_cur_drv(fdctrl); 1639 1640 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1641 qemu_mod_timer(fdctrl->result_timer, 1642 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50)); 1643 } 1644 1645 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) 1646 { 1647 FDrive *cur_drv; 1648 1649 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1650 cur_drv = get_cur_drv(fdctrl); 1651 fdctrl->data_state |= FD_STATE_FORMAT; 1652 if (fdctrl->fifo[0] & 0x80) 1653 fdctrl->data_state |= FD_STATE_MULTI; 1654 else 1655 fdctrl->data_state &= ~FD_STATE_MULTI; 1656 cur_drv->bps = 1657 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; 1658 #if 0 1659 cur_drv->last_sect = 1660 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : 1661 fdctrl->fifo[3] / 2; 1662 #else 1663 cur_drv->last_sect = fdctrl->fifo[3]; 1664 #endif 1665 /* TODO: implement format using DMA expected by the Bochs BIOS 1666 * and Linux fdformat (read 3 bytes per sector via DMA and fill 1667 * the sector with the specified fill byte 1668 */ 1669 fdctrl->data_state &= ~FD_STATE_FORMAT; 1670 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1671 } 1672 1673 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) 1674 { 1675 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; 1676 fdctrl->timer1 = fdctrl->fifo[2] >> 1; 1677 if (fdctrl->fifo[2] & 1) 1678 fdctrl->dor &= ~FD_DOR_DMAEN; 1679 else 1680 fdctrl->dor |= FD_DOR_DMAEN; 1681 /* No result back */ 1682 fdctrl_reset_fifo(fdctrl); 1683 } 1684 1685 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) 1686 { 1687 FDrive *cur_drv; 1688 1689 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1690 cur_drv = get_cur_drv(fdctrl); 1691 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1692 /* 1 Byte status back */ 1693 fdctrl->fifo[0] = (cur_drv->ro << 6) | 1694 (cur_drv->track == 0 ? 0x10 : 0x00) | 1695 (cur_drv->head << 2) | 1696 GET_CUR_DRV(fdctrl) | 1697 0x28; 1698 fdctrl_set_fifo(fdctrl, 1); 1699 } 1700 1701 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) 1702 { 1703 FDrive *cur_drv; 1704 1705 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1706 cur_drv = get_cur_drv(fdctrl); 1707 fd_recalibrate(cur_drv); 1708 fdctrl_reset_fifo(fdctrl); 1709 /* Raise Interrupt */ 1710 fdctrl->status0 |= FD_SR0_SEEK; 1711 fdctrl_raise_irq(fdctrl); 1712 } 1713 1714 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) 1715 { 1716 FDrive *cur_drv = get_cur_drv(fdctrl); 1717 1718 if (fdctrl->reset_sensei > 0) { 1719 fdctrl->fifo[0] = 1720 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; 1721 fdctrl->reset_sensei--; 1722 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) { 1723 fdctrl->fifo[0] = FD_SR0_INVCMD; 1724 fdctrl_set_fifo(fdctrl, 1); 1725 return; 1726 } else { 1727 fdctrl->fifo[0] = 1728 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0)) 1729 | GET_CUR_DRV(fdctrl); 1730 } 1731 1732 fdctrl->fifo[1] = cur_drv->track; 1733 fdctrl_set_fifo(fdctrl, 2); 1734 fdctrl_reset_irq(fdctrl); 1735 fdctrl->status0 = FD_SR0_RDYCHG; 1736 } 1737 1738 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) 1739 { 1740 FDrive *cur_drv; 1741 1742 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1743 cur_drv = get_cur_drv(fdctrl); 1744 fdctrl_reset_fifo(fdctrl); 1745 /* The seek command just sends step pulses to the drive and doesn't care if 1746 * there is a medium inserted of if it's banging the head against the drive. 1747 */ 1748 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1); 1749 /* Raise Interrupt */ 1750 fdctrl->status0 |= FD_SR0_SEEK; 1751 fdctrl_raise_irq(fdctrl); 1752 } 1753 1754 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) 1755 { 1756 FDrive *cur_drv = get_cur_drv(fdctrl); 1757 1758 if (fdctrl->fifo[1] & 0x80) 1759 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; 1760 /* No result back */ 1761 fdctrl_reset_fifo(fdctrl); 1762 } 1763 1764 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) 1765 { 1766 fdctrl->config = fdctrl->fifo[2]; 1767 fdctrl->precomp_trk = fdctrl->fifo[3]; 1768 /* No result back */ 1769 fdctrl_reset_fifo(fdctrl); 1770 } 1771 1772 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) 1773 { 1774 fdctrl->pwrd = fdctrl->fifo[1]; 1775 fdctrl->fifo[0] = fdctrl->fifo[1]; 1776 fdctrl_set_fifo(fdctrl, 1); 1777 } 1778 1779 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) 1780 { 1781 /* No result back */ 1782 fdctrl_reset_fifo(fdctrl); 1783 } 1784 1785 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) 1786 { 1787 FDrive *cur_drv = get_cur_drv(fdctrl); 1788 1789 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { 1790 /* Command parameters done */ 1791 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) { 1792 fdctrl->fifo[0] = fdctrl->fifo[1]; 1793 fdctrl->fifo[2] = 0; 1794 fdctrl->fifo[3] = 0; 1795 fdctrl_set_fifo(fdctrl, 4); 1796 } else { 1797 fdctrl_reset_fifo(fdctrl); 1798 } 1799 } else if (fdctrl->data_len > 7) { 1800 /* ERROR */ 1801 fdctrl->fifo[0] = 0x80 | 1802 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); 1803 fdctrl_set_fifo(fdctrl, 1); 1804 } 1805 } 1806 1807 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) 1808 { 1809 FDrive *cur_drv; 1810 1811 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1812 cur_drv = get_cur_drv(fdctrl); 1813 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { 1814 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1, 1815 cur_drv->sect, 1); 1816 } else { 1817 fd_seek(cur_drv, cur_drv->head, 1818 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1); 1819 } 1820 fdctrl_reset_fifo(fdctrl); 1821 /* Raise Interrupt */ 1822 fdctrl->status0 |= FD_SR0_SEEK; 1823 fdctrl_raise_irq(fdctrl); 1824 } 1825 1826 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) 1827 { 1828 FDrive *cur_drv; 1829 1830 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1831 cur_drv = get_cur_drv(fdctrl); 1832 if (fdctrl->fifo[2] > cur_drv->track) { 1833 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1); 1834 } else { 1835 fd_seek(cur_drv, cur_drv->head, 1836 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1); 1837 } 1838 fdctrl_reset_fifo(fdctrl); 1839 /* Raise Interrupt */ 1840 fdctrl->status0 |= FD_SR0_SEEK; 1841 fdctrl_raise_irq(fdctrl); 1842 } 1843 1844 static const struct { 1845 uint8_t value; 1846 uint8_t mask; 1847 const char* name; 1848 int parameters; 1849 void (*handler)(FDCtrl *fdctrl, int direction); 1850 int direction; 1851 } handlers[] = { 1852 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, 1853 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, 1854 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, 1855 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, 1856 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, 1857 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, 1858 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, 1859 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ 1860 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ 1861 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, 1862 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, 1863 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY }, 1864 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, 1865 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, 1866 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, 1867 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, 1868 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, 1869 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, 1870 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, 1871 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, 1872 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, 1873 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, 1874 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, 1875 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, 1876 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, 1877 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, 1878 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, 1879 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, 1880 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, 1881 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, 1882 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ 1883 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ 1884 }; 1885 /* Associate command to an index in the 'handlers' array */ 1886 static uint8_t command_to_handler[256]; 1887 1888 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) 1889 { 1890 FDrive *cur_drv; 1891 int pos; 1892 1893 /* Reset mode */ 1894 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1895 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1896 return; 1897 } 1898 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { 1899 FLOPPY_DPRINTF("error: controller not ready for writing\n"); 1900 return; 1901 } 1902 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1903 /* Is it write command time ? */ 1904 if (fdctrl->msr & FD_MSR_NONDMA) { 1905 /* FIFO data write */ 1906 pos = fdctrl->data_pos++; 1907 pos %= FD_SECTOR_LEN; 1908 fdctrl->fifo[pos] = value; 1909 if (pos == FD_SECTOR_LEN - 1 || 1910 fdctrl->data_pos == fdctrl->data_len) { 1911 cur_drv = get_cur_drv(fdctrl); 1912 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1913 FLOPPY_DPRINTF("error writing sector %d\n", 1914 fd_sector(cur_drv)); 1915 return; 1916 } 1917 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1918 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1919 fd_sector(cur_drv)); 1920 return; 1921 } 1922 } 1923 /* Switch from transfer mode to status mode 1924 * then from status mode to command mode 1925 */ 1926 if (fdctrl->data_pos == fdctrl->data_len) 1927 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1928 return; 1929 } 1930 if (fdctrl->data_pos == 0) { 1931 /* Command */ 1932 pos = command_to_handler[value & 0xff]; 1933 FLOPPY_DPRINTF("%s command\n", handlers[pos].name); 1934 fdctrl->data_len = handlers[pos].parameters + 1; 1935 fdctrl->msr |= FD_MSR_CMDBUSY; 1936 } 1937 1938 FLOPPY_DPRINTF("%s: %02x\n", __func__, value); 1939 fdctrl->fifo[fdctrl->data_pos++] = value; 1940 if (fdctrl->data_pos == fdctrl->data_len) { 1941 /* We now have all parameters 1942 * and will be able to treat the command 1943 */ 1944 if (fdctrl->data_state & FD_STATE_FORMAT) { 1945 fdctrl_format_sector(fdctrl); 1946 return; 1947 } 1948 1949 pos = command_to_handler[fdctrl->fifo[0] & 0xff]; 1950 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name); 1951 (*handlers[pos].handler)(fdctrl, handlers[pos].direction); 1952 } 1953 } 1954 1955 static void fdctrl_result_timer(void *opaque) 1956 { 1957 FDCtrl *fdctrl = opaque; 1958 FDrive *cur_drv = get_cur_drv(fdctrl); 1959 1960 /* Pretend we are spinning. 1961 * This is needed for Coherent, which uses READ ID to check for 1962 * sector interleaving. 1963 */ 1964 if (cur_drv->last_sect != 0) { 1965 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; 1966 } 1967 /* READ_ID can't automatically succeed! */ 1968 if (fdctrl->check_media_rate && 1969 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 1970 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n", 1971 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 1972 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 1973 } else { 1974 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1975 } 1976 } 1977 1978 static void fdctrl_change_cb(void *opaque, bool load) 1979 { 1980 FDrive *drive = opaque; 1981 1982 drive->media_changed = 1; 1983 fd_revalidate(drive); 1984 } 1985 1986 static const BlockDevOps fdctrl_block_ops = { 1987 .change_media_cb = fdctrl_change_cb, 1988 }; 1989 1990 /* Init functions */ 1991 static int fdctrl_connect_drives(FDCtrl *fdctrl) 1992 { 1993 unsigned int i; 1994 FDrive *drive; 1995 1996 for (i = 0; i < MAX_FD; i++) { 1997 drive = &fdctrl->drives[i]; 1998 drive->fdctrl = fdctrl; 1999 2000 if (drive->bs) { 2001 if (bdrv_get_on_error(drive->bs, 0) != BLOCKDEV_ON_ERROR_ENOSPC) { 2002 error_report("fdc doesn't support drive option werror"); 2003 return -1; 2004 } 2005 if (bdrv_get_on_error(drive->bs, 1) != BLOCKDEV_ON_ERROR_REPORT) { 2006 error_report("fdc doesn't support drive option rerror"); 2007 return -1; 2008 } 2009 } 2010 2011 fd_init(drive); 2012 fdctrl_change_cb(drive, 0); 2013 if (drive->bs) { 2014 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive); 2015 } 2016 } 2017 return 0; 2018 } 2019 2020 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds) 2021 { 2022 ISADevice *dev; 2023 2024 dev = isa_try_create(bus, "isa-fdc"); 2025 if (!dev) { 2026 return NULL; 2027 } 2028 2029 if (fds[0]) { 2030 qdev_prop_set_drive_nofail(&dev->qdev, "driveA", fds[0]->bdrv); 2031 } 2032 if (fds[1]) { 2033 qdev_prop_set_drive_nofail(&dev->qdev, "driveB", fds[1]->bdrv); 2034 } 2035 qdev_init_nofail(&dev->qdev); 2036 2037 return dev; 2038 } 2039 2040 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, 2041 hwaddr mmio_base, DriveInfo **fds) 2042 { 2043 FDCtrl *fdctrl; 2044 DeviceState *dev; 2045 FDCtrlSysBus *sys; 2046 2047 dev = qdev_create(NULL, "sysbus-fdc"); 2048 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev); 2049 fdctrl = &sys->state; 2050 fdctrl->dma_chann = dma_chann; /* FIXME */ 2051 if (fds[0]) { 2052 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv); 2053 } 2054 if (fds[1]) { 2055 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv); 2056 } 2057 qdev_init_nofail(dev); 2058 sysbus_connect_irq(&sys->busdev, 0, irq); 2059 sysbus_mmio_map(&sys->busdev, 0, mmio_base); 2060 } 2061 2062 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, 2063 DriveInfo **fds, qemu_irq *fdc_tc) 2064 { 2065 DeviceState *dev; 2066 FDCtrlSysBus *sys; 2067 2068 dev = qdev_create(NULL, "SUNW,fdtwo"); 2069 if (fds[0]) { 2070 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv); 2071 } 2072 qdev_init_nofail(dev); 2073 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev); 2074 sysbus_connect_irq(&sys->busdev, 0, irq); 2075 sysbus_mmio_map(&sys->busdev, 0, io_base); 2076 *fdc_tc = qdev_get_gpio_in(dev, 0); 2077 } 2078 2079 static int fdctrl_init_common(FDCtrl *fdctrl) 2080 { 2081 int i, j; 2082 static int command_tables_inited = 0; 2083 2084 /* Fill 'command_to_handler' lookup table */ 2085 if (!command_tables_inited) { 2086 command_tables_inited = 1; 2087 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { 2088 for (j = 0; j < sizeof(command_to_handler); j++) { 2089 if ((j & handlers[i].mask) == handlers[i].value) { 2090 command_to_handler[j] = i; 2091 } 2092 } 2093 } 2094 } 2095 2096 FLOPPY_DPRINTF("init controller\n"); 2097 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); 2098 fdctrl->fifo_size = 512; 2099 fdctrl->result_timer = qemu_new_timer_ns(vm_clock, 2100 fdctrl_result_timer, fdctrl); 2101 2102 fdctrl->version = 0x90; /* Intel 82078 controller */ 2103 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ 2104 fdctrl->num_floppies = MAX_FD; 2105 2106 if (fdctrl->dma_chann != -1) 2107 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl); 2108 return fdctrl_connect_drives(fdctrl); 2109 } 2110 2111 static const MemoryRegionPortio fdc_portio_list[] = { 2112 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, 2113 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, 2114 PORTIO_END_OF_LIST(), 2115 }; 2116 2117 static int isabus_fdc_init1(ISADevice *dev) 2118 { 2119 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev); 2120 FDCtrl *fdctrl = &isa->state; 2121 int ret; 2122 2123 isa_register_portio_list(dev, isa->iobase, fdc_portio_list, fdctrl, "fdc"); 2124 2125 isa_init_irq(&isa->busdev, &fdctrl->irq, isa->irq); 2126 fdctrl->dma_chann = isa->dma; 2127 2128 qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 2); 2129 ret = fdctrl_init_common(fdctrl); 2130 2131 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0"); 2132 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1"); 2133 2134 return ret; 2135 } 2136 2137 static int sysbus_fdc_init1(SysBusDevice *dev) 2138 { 2139 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev); 2140 FDCtrl *fdctrl = &sys->state; 2141 int ret; 2142 2143 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08); 2144 sysbus_init_mmio(dev, &fdctrl->iomem); 2145 sysbus_init_irq(dev, &fdctrl->irq); 2146 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1); 2147 fdctrl->dma_chann = -1; 2148 2149 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */ 2150 ret = fdctrl_init_common(fdctrl); 2151 2152 return ret; 2153 } 2154 2155 static int sun4m_fdc_init1(SysBusDevice *dev) 2156 { 2157 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state); 2158 2159 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl, 2160 "fdctrl", 0x08); 2161 sysbus_init_mmio(dev, &fdctrl->iomem); 2162 sysbus_init_irq(dev, &fdctrl->irq); 2163 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1); 2164 2165 fdctrl->sun4m = 1; 2166 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */ 2167 return fdctrl_init_common(fdctrl); 2168 } 2169 2170 FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i) 2171 { 2172 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, fdc); 2173 2174 return isa->state.drives[i].drive; 2175 } 2176 2177 static const VMStateDescription vmstate_isa_fdc ={ 2178 .name = "fdc", 2179 .version_id = 2, 2180 .minimum_version_id = 2, 2181 .fields = (VMStateField []) { 2182 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl), 2183 VMSTATE_END_OF_LIST() 2184 } 2185 }; 2186 2187 static Property isa_fdc_properties[] = { 2188 DEFINE_PROP_HEX32("iobase", FDCtrlISABus, iobase, 0x3f0), 2189 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6), 2190 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2), 2191 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs), 2192 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs), 2193 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1), 2194 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1), 2195 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate, 2196 0, true), 2197 DEFINE_PROP_END_OF_LIST(), 2198 }; 2199 2200 static void isabus_fdc_class_init1(ObjectClass *klass, void *data) 2201 { 2202 DeviceClass *dc = DEVICE_CLASS(klass); 2203 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); 2204 ic->init = isabus_fdc_init1; 2205 dc->fw_name = "fdc"; 2206 dc->no_user = 1; 2207 dc->reset = fdctrl_external_reset_isa; 2208 dc->vmsd = &vmstate_isa_fdc; 2209 dc->props = isa_fdc_properties; 2210 } 2211 2212 static const TypeInfo isa_fdc_info = { 2213 .name = "isa-fdc", 2214 .parent = TYPE_ISA_DEVICE, 2215 .instance_size = sizeof(FDCtrlISABus), 2216 .class_init = isabus_fdc_class_init1, 2217 }; 2218 2219 static const VMStateDescription vmstate_sysbus_fdc ={ 2220 .name = "fdc", 2221 .version_id = 2, 2222 .minimum_version_id = 2, 2223 .fields = (VMStateField []) { 2224 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl), 2225 VMSTATE_END_OF_LIST() 2226 } 2227 }; 2228 2229 static Property sysbus_fdc_properties[] = { 2230 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs), 2231 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs), 2232 DEFINE_PROP_END_OF_LIST(), 2233 }; 2234 2235 static void sysbus_fdc_class_init(ObjectClass *klass, void *data) 2236 { 2237 DeviceClass *dc = DEVICE_CLASS(klass); 2238 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 2239 2240 k->init = sysbus_fdc_init1; 2241 dc->reset = fdctrl_external_reset_sysbus; 2242 dc->vmsd = &vmstate_sysbus_fdc; 2243 dc->props = sysbus_fdc_properties; 2244 } 2245 2246 static const TypeInfo sysbus_fdc_info = { 2247 .name = "sysbus-fdc", 2248 .parent = TYPE_SYS_BUS_DEVICE, 2249 .instance_size = sizeof(FDCtrlSysBus), 2250 .class_init = sysbus_fdc_class_init, 2251 }; 2252 2253 static Property sun4m_fdc_properties[] = { 2254 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs), 2255 DEFINE_PROP_END_OF_LIST(), 2256 }; 2257 2258 static void sun4m_fdc_class_init(ObjectClass *klass, void *data) 2259 { 2260 DeviceClass *dc = DEVICE_CLASS(klass); 2261 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 2262 2263 k->init = sun4m_fdc_init1; 2264 dc->reset = fdctrl_external_reset_sysbus; 2265 dc->vmsd = &vmstate_sysbus_fdc; 2266 dc->props = sun4m_fdc_properties; 2267 } 2268 2269 static const TypeInfo sun4m_fdc_info = { 2270 .name = "SUNW,fdtwo", 2271 .parent = TYPE_SYS_BUS_DEVICE, 2272 .instance_size = sizeof(FDCtrlSysBus), 2273 .class_init = sun4m_fdc_class_init, 2274 }; 2275 2276 static void fdc_register_types(void) 2277 { 2278 type_register_static(&isa_fdc_info); 2279 type_register_static(&sysbus_fdc_info); 2280 type_register_static(&sun4m_fdc_info); 2281 } 2282 2283 type_init(fdc_register_types) 2284