1 /* 2 * QEMU Floppy disk emulator (Intel 82078) 3 * 4 * Copyright (c) 2003, 2007 Jocelyn Mayer 5 * Copyright (c) 2008 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * The controller is used in Sun4m systems in a slightly different 27 * way. There are changes in DOR register and DMA is not available. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/block/fdc.h" 33 #include "qemu/error-report.h" 34 #include "qemu/timer.h" 35 #include "hw/isa/isa.h" 36 #include "hw/sysbus.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/blockdev.h" 39 #include "sysemu/sysemu.h" 40 #include "qemu/log.h" 41 42 /********************************************************/ 43 /* debug Floppy devices */ 44 //#define DEBUG_FLOPPY 45 46 #ifdef DEBUG_FLOPPY 47 #define FLOPPY_DPRINTF(fmt, ...) \ 48 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) 49 #else 50 #define FLOPPY_DPRINTF(fmt, ...) 51 #endif 52 53 /********************************************************/ 54 /* Floppy drive emulation */ 55 56 typedef enum FDriveRate { 57 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */ 58 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */ 59 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */ 60 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */ 61 } FDriveRate; 62 63 typedef enum FDriveSize { 64 FDRIVE_SIZE_UNKNOWN, 65 FDRIVE_SIZE_350, 66 FDRIVE_SIZE_525, 67 } FDriveSize; 68 69 typedef struct FDFormat { 70 FloppyDriveType drive; 71 uint8_t last_sect; 72 uint8_t max_track; 73 uint8_t max_head; 74 FDriveRate rate; 75 } FDFormat; 76 77 /* In many cases, the total sector size of a format is enough to uniquely 78 * identify it. However, there are some total sector collisions between 79 * formats of different physical size, and these are noted below by 80 * highlighting the total sector size for entries with collisions. */ 81 static const FDFormat fd_formats[] = { 82 /* First entry is default format */ 83 /* 1.44 MB 3"1/2 floppy disks */ 84 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */ 85 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */ 86 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, }, 87 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, }, 88 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, }, 89 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, }, 90 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, }, 91 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, }, 92 /* 2.88 MB 3"1/2 floppy disks */ 93 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, }, 94 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, }, 95 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, }, 96 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, }, 97 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, }, 98 /* 720 kB 3"1/2 floppy disks */ 99 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */ 100 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, }, 101 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, }, 102 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, }, 103 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, }, 104 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, }, 105 /* 1.2 MB 5"1/4 floppy disks */ 106 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, }, 107 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */ 108 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, }, 109 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, }, 110 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */ 111 /* 720 kB 5"1/4 floppy disks */ 112 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */ 113 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, }, 114 /* 360 kB 5"1/4 floppy disks */ 115 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */ 116 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, }, 117 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, }, 118 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, }, 119 /* 320 kB 5"1/4 floppy disks */ 120 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, }, 121 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, }, 122 /* 360 kB must match 5"1/4 better than 3"1/2... */ 123 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */ 124 /* end */ 125 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, }, 126 }; 127 128 static FDriveSize drive_size(FloppyDriveType drive) 129 { 130 switch (drive) { 131 case FLOPPY_DRIVE_TYPE_120: 132 return FDRIVE_SIZE_525; 133 case FLOPPY_DRIVE_TYPE_144: 134 case FLOPPY_DRIVE_TYPE_288: 135 return FDRIVE_SIZE_350; 136 default: 137 return FDRIVE_SIZE_UNKNOWN; 138 } 139 } 140 141 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) 142 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) 143 144 /* Will always be a fixed parameter for us */ 145 #define FD_SECTOR_LEN 512 146 #define FD_SECTOR_SC 2 /* Sector size code */ 147 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ 148 149 typedef struct FDCtrl FDCtrl; 150 151 /* Floppy disk drive emulation */ 152 typedef enum FDiskFlags { 153 FDISK_DBL_SIDES = 0x01, 154 } FDiskFlags; 155 156 typedef struct FDrive { 157 FDCtrl *fdctrl; 158 BlockBackend *blk; 159 /* Drive status */ 160 FloppyDriveType drive; /* CMOS drive type */ 161 uint8_t perpendicular; /* 2.88 MB access mode */ 162 /* Position */ 163 uint8_t head; 164 uint8_t track; 165 uint8_t sect; 166 /* Media */ 167 FloppyDriveType disk; /* Current disk type */ 168 FDiskFlags flags; 169 uint8_t last_sect; /* Nb sector per track */ 170 uint8_t max_track; /* Nb of tracks */ 171 uint16_t bps; /* Bytes per sector */ 172 uint8_t ro; /* Is read-only */ 173 uint8_t media_changed; /* Is media changed */ 174 uint8_t media_rate; /* Data rate of medium */ 175 176 bool media_inserted; /* Is there a medium in the tray */ 177 bool media_validated; /* Have we validated the media? */ 178 } FDrive; 179 180 181 static FloppyDriveType get_fallback_drive_type(FDrive *drv); 182 183 static void fd_init(FDrive *drv) 184 { 185 /* Drive */ 186 drv->perpendicular = 0; 187 /* Disk */ 188 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 189 drv->last_sect = 0; 190 drv->max_track = 0; 191 drv->ro = true; 192 drv->media_changed = 1; 193 } 194 195 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) 196 197 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, 198 uint8_t last_sect, uint8_t num_sides) 199 { 200 return (((track * num_sides) + head) * last_sect) + sect - 1; 201 } 202 203 /* Returns current position, in sectors, for given drive */ 204 static int fd_sector(FDrive *drv) 205 { 206 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, 207 NUM_SIDES(drv)); 208 } 209 210 /* Seek to a new position: 211 * returns 0 if already on right track 212 * returns 1 if track changed 213 * returns 2 if track is invalid 214 * returns 3 if sector is invalid 215 * returns 4 if seek is disabled 216 */ 217 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, 218 int enable_seek) 219 { 220 uint32_t sector; 221 int ret; 222 223 if (track > drv->max_track || 224 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { 225 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 226 head, track, sect, 1, 227 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 228 drv->max_track, drv->last_sect); 229 return 2; 230 } 231 if (sect > drv->last_sect) { 232 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 233 head, track, sect, 1, 234 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 235 drv->max_track, drv->last_sect); 236 return 3; 237 } 238 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); 239 ret = 0; 240 if (sector != fd_sector(drv)) { 241 #if 0 242 if (!enable_seek) { 243 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x" 244 " (max=%d %02x %02x)\n", 245 head, track, sect, 1, drv->max_track, 246 drv->last_sect); 247 return 4; 248 } 249 #endif 250 drv->head = head; 251 if (drv->track != track) { 252 if (drv->media_inserted) { 253 drv->media_changed = 0; 254 } 255 ret = 1; 256 } 257 drv->track = track; 258 drv->sect = sect; 259 } 260 261 if (!drv->media_inserted) { 262 ret = 2; 263 } 264 265 return ret; 266 } 267 268 /* Set drive back to track 0 */ 269 static void fd_recalibrate(FDrive *drv) 270 { 271 FLOPPY_DPRINTF("recalibrate\n"); 272 fd_seek(drv, 0, 0, 1, 1); 273 } 274 275 /** 276 * Determine geometry based on inserted diskette. 277 * Will not operate on an empty drive. 278 * 279 * @return: 0 on success, -1 if the drive is empty. 280 */ 281 static int pick_geometry(FDrive *drv) 282 { 283 BlockBackend *blk = drv->blk; 284 const FDFormat *parse; 285 uint64_t nb_sectors, size; 286 int i; 287 int match, size_match, type_match; 288 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO; 289 290 /* We can only pick a geometry if we have a diskette. */ 291 if (!drv->media_inserted || drv->drive == FLOPPY_DRIVE_TYPE_NONE) { 292 return -1; 293 } 294 295 /* We need to determine the likely geometry of the inserted medium. 296 * In order of preference, we look for: 297 * (1) The same drive type and number of sectors, 298 * (2) The same diskette size and number of sectors, 299 * (3) The same drive type. 300 * 301 * In all cases, matches that occur higher in the drive table will take 302 * precedence over matches that occur later in the table. 303 */ 304 blk_get_geometry(blk, &nb_sectors); 305 match = size_match = type_match = -1; 306 for (i = 0; ; i++) { 307 parse = &fd_formats[i]; 308 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) { 309 break; 310 } 311 size = (parse->max_head + 1) * parse->max_track * parse->last_sect; 312 if (nb_sectors == size) { 313 if (magic || parse->drive == drv->drive) { 314 /* (1) perfect match -- nb_sectors and drive type */ 315 goto out; 316 } else if (drive_size(parse->drive) == drive_size(drv->drive)) { 317 /* (2) size match -- nb_sectors and physical medium size */ 318 match = (match == -1) ? i : match; 319 } else { 320 /* This is suspicious -- Did the user misconfigure? */ 321 size_match = (size_match == -1) ? i : size_match; 322 } 323 } else if (type_match == -1) { 324 if ((parse->drive == drv->drive) || 325 (magic && (parse->drive == get_fallback_drive_type(drv)))) { 326 /* (3) type match -- nb_sectors mismatch, but matches the type 327 * specified explicitly by the user, or matches the fallback 328 * default type when using the drive autodetect mechanism */ 329 type_match = i; 330 } 331 } 332 } 333 334 /* No exact match found */ 335 if (match == -1) { 336 if (size_match != -1) { 337 parse = &fd_formats[size_match]; 338 FLOPPY_DPRINTF("User requested floppy drive type '%s', " 339 "but inserted medium appears to be a " 340 "%d sector '%s' type\n", 341 FloppyDriveType_lookup[drv->drive], 342 nb_sectors, 343 FloppyDriveType_lookup[parse->drive]); 344 } 345 match = type_match; 346 } 347 348 /* No match of any kind found -- fd_format is misconfigured, abort. */ 349 if (match == -1) { 350 error_setg(&error_abort, "No candidate geometries present in table " 351 " for floppy drive type '%s'", 352 FloppyDriveType_lookup[drv->drive]); 353 } 354 355 parse = &(fd_formats[match]); 356 357 out: 358 if (parse->max_head == 0) { 359 drv->flags &= ~FDISK_DBL_SIDES; 360 } else { 361 drv->flags |= FDISK_DBL_SIDES; 362 } 363 drv->max_track = parse->max_track; 364 drv->last_sect = parse->last_sect; 365 drv->disk = parse->drive; 366 drv->media_rate = parse->rate; 367 return 0; 368 } 369 370 static void pick_drive_type(FDrive *drv) 371 { 372 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) { 373 return; 374 } 375 376 if (pick_geometry(drv) == 0) { 377 drv->drive = drv->disk; 378 } else { 379 drv->drive = get_fallback_drive_type(drv); 380 } 381 382 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO); 383 } 384 385 /* Revalidate a disk drive after a disk change */ 386 static void fd_revalidate(FDrive *drv) 387 { 388 int rc; 389 390 FLOPPY_DPRINTF("revalidate\n"); 391 if (drv->blk != NULL) { 392 drv->ro = blk_is_read_only(drv->blk); 393 if (!drv->media_inserted) { 394 FLOPPY_DPRINTF("No disk in drive\n"); 395 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 396 } else if (!drv->media_validated) { 397 rc = pick_geometry(drv); 398 if (rc) { 399 FLOPPY_DPRINTF("Could not validate floppy drive media"); 400 } else { 401 drv->media_validated = true; 402 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", 403 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1, 404 drv->max_track, drv->last_sect, 405 drv->ro ? "ro" : "rw"); 406 } 407 } 408 } else { 409 FLOPPY_DPRINTF("No drive connected\n"); 410 drv->last_sect = 0; 411 drv->max_track = 0; 412 drv->flags &= ~FDISK_DBL_SIDES; 413 drv->drive = FLOPPY_DRIVE_TYPE_NONE; 414 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 415 } 416 } 417 418 /********************************************************/ 419 /* Intel 82078 floppy disk controller emulation */ 420 421 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); 422 static void fdctrl_to_command_phase(FDCtrl *fdctrl); 423 static int fdctrl_transfer_handler (void *opaque, int nchan, 424 int dma_pos, int dma_len); 425 static void fdctrl_raise_irq(FDCtrl *fdctrl); 426 static FDrive *get_cur_drv(FDCtrl *fdctrl); 427 428 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); 429 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); 430 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); 431 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); 432 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); 433 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); 434 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); 435 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); 436 static uint32_t fdctrl_read_data(FDCtrl *fdctrl); 437 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); 438 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); 439 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); 440 441 enum { 442 FD_DIR_WRITE = 0, 443 FD_DIR_READ = 1, 444 FD_DIR_SCANE = 2, 445 FD_DIR_SCANL = 3, 446 FD_DIR_SCANH = 4, 447 FD_DIR_VERIFY = 5, 448 }; 449 450 enum { 451 FD_STATE_MULTI = 0x01, /* multi track flag */ 452 FD_STATE_FORMAT = 0x02, /* format flag */ 453 }; 454 455 enum { 456 FD_REG_SRA = 0x00, 457 FD_REG_SRB = 0x01, 458 FD_REG_DOR = 0x02, 459 FD_REG_TDR = 0x03, 460 FD_REG_MSR = 0x04, 461 FD_REG_DSR = 0x04, 462 FD_REG_FIFO = 0x05, 463 FD_REG_DIR = 0x07, 464 FD_REG_CCR = 0x07, 465 }; 466 467 enum { 468 FD_CMD_READ_TRACK = 0x02, 469 FD_CMD_SPECIFY = 0x03, 470 FD_CMD_SENSE_DRIVE_STATUS = 0x04, 471 FD_CMD_WRITE = 0x05, 472 FD_CMD_READ = 0x06, 473 FD_CMD_RECALIBRATE = 0x07, 474 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, 475 FD_CMD_WRITE_DELETED = 0x09, 476 FD_CMD_READ_ID = 0x0a, 477 FD_CMD_READ_DELETED = 0x0c, 478 FD_CMD_FORMAT_TRACK = 0x0d, 479 FD_CMD_DUMPREG = 0x0e, 480 FD_CMD_SEEK = 0x0f, 481 FD_CMD_VERSION = 0x10, 482 FD_CMD_SCAN_EQUAL = 0x11, 483 FD_CMD_PERPENDICULAR_MODE = 0x12, 484 FD_CMD_CONFIGURE = 0x13, 485 FD_CMD_LOCK = 0x14, 486 FD_CMD_VERIFY = 0x16, 487 FD_CMD_POWERDOWN_MODE = 0x17, 488 FD_CMD_PART_ID = 0x18, 489 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, 490 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, 491 FD_CMD_SAVE = 0x2e, 492 FD_CMD_OPTION = 0x33, 493 FD_CMD_RESTORE = 0x4e, 494 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, 495 FD_CMD_RELATIVE_SEEK_OUT = 0x8f, 496 FD_CMD_FORMAT_AND_WRITE = 0xcd, 497 FD_CMD_RELATIVE_SEEK_IN = 0xcf, 498 }; 499 500 enum { 501 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ 502 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ 503 FD_CONFIG_POLL = 0x10, /* Poll enabled */ 504 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ 505 FD_CONFIG_EIS = 0x40, /* No implied seeks */ 506 }; 507 508 enum { 509 FD_SR0_DS0 = 0x01, 510 FD_SR0_DS1 = 0x02, 511 FD_SR0_HEAD = 0x04, 512 FD_SR0_EQPMT = 0x10, 513 FD_SR0_SEEK = 0x20, 514 FD_SR0_ABNTERM = 0x40, 515 FD_SR0_INVCMD = 0x80, 516 FD_SR0_RDYCHG = 0xc0, 517 }; 518 519 enum { 520 FD_SR1_MA = 0x01, /* Missing address mark */ 521 FD_SR1_NW = 0x02, /* Not writable */ 522 FD_SR1_EC = 0x80, /* End of cylinder */ 523 }; 524 525 enum { 526 FD_SR2_SNS = 0x04, /* Scan not satisfied */ 527 FD_SR2_SEH = 0x08, /* Scan equal hit */ 528 }; 529 530 enum { 531 FD_SRA_DIR = 0x01, 532 FD_SRA_nWP = 0x02, 533 FD_SRA_nINDX = 0x04, 534 FD_SRA_HDSEL = 0x08, 535 FD_SRA_nTRK0 = 0x10, 536 FD_SRA_STEP = 0x20, 537 FD_SRA_nDRV2 = 0x40, 538 FD_SRA_INTPEND = 0x80, 539 }; 540 541 enum { 542 FD_SRB_MTR0 = 0x01, 543 FD_SRB_MTR1 = 0x02, 544 FD_SRB_WGATE = 0x04, 545 FD_SRB_RDATA = 0x08, 546 FD_SRB_WDATA = 0x10, 547 FD_SRB_DR0 = 0x20, 548 }; 549 550 enum { 551 #if MAX_FD == 4 552 FD_DOR_SELMASK = 0x03, 553 #else 554 FD_DOR_SELMASK = 0x01, 555 #endif 556 FD_DOR_nRESET = 0x04, 557 FD_DOR_DMAEN = 0x08, 558 FD_DOR_MOTEN0 = 0x10, 559 FD_DOR_MOTEN1 = 0x20, 560 FD_DOR_MOTEN2 = 0x40, 561 FD_DOR_MOTEN3 = 0x80, 562 }; 563 564 enum { 565 #if MAX_FD == 4 566 FD_TDR_BOOTSEL = 0x0c, 567 #else 568 FD_TDR_BOOTSEL = 0x04, 569 #endif 570 }; 571 572 enum { 573 FD_DSR_DRATEMASK= 0x03, 574 FD_DSR_PWRDOWN = 0x40, 575 FD_DSR_SWRESET = 0x80, 576 }; 577 578 enum { 579 FD_MSR_DRV0BUSY = 0x01, 580 FD_MSR_DRV1BUSY = 0x02, 581 FD_MSR_DRV2BUSY = 0x04, 582 FD_MSR_DRV3BUSY = 0x08, 583 FD_MSR_CMDBUSY = 0x10, 584 FD_MSR_NONDMA = 0x20, 585 FD_MSR_DIO = 0x40, 586 FD_MSR_RQM = 0x80, 587 }; 588 589 enum { 590 FD_DIR_DSKCHG = 0x80, 591 }; 592 593 /* 594 * See chapter 5.0 "Controller phases" of the spec: 595 * 596 * Command phase: 597 * The host writes a command and its parameters into the FIFO. The command 598 * phase is completed when all parameters for the command have been supplied, 599 * and execution phase is entered. 600 * 601 * Execution phase: 602 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO 603 * contains the payload now, otherwise it's unused. When all bytes of the 604 * required data have been transferred, the state is switched to either result 605 * phase (if the command produces status bytes) or directly back into the 606 * command phase for the next command. 607 * 608 * Result phase: 609 * The host reads out the FIFO, which contains one or more result bytes now. 610 */ 611 enum { 612 /* Only for migration: reconstruct phase from registers like qemu 2.3 */ 613 FD_PHASE_RECONSTRUCT = 0, 614 615 FD_PHASE_COMMAND = 1, 616 FD_PHASE_EXECUTION = 2, 617 FD_PHASE_RESULT = 3, 618 }; 619 620 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) 621 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) 622 623 struct FDCtrl { 624 MemoryRegion iomem; 625 qemu_irq irq; 626 /* Controller state */ 627 QEMUTimer *result_timer; 628 int dma_chann; 629 uint8_t phase; 630 /* Controller's identification */ 631 uint8_t version; 632 /* HW */ 633 uint8_t sra; 634 uint8_t srb; 635 uint8_t dor; 636 uint8_t dor_vmstate; /* only used as temp during vmstate */ 637 uint8_t tdr; 638 uint8_t dsr; 639 uint8_t msr; 640 uint8_t cur_drv; 641 uint8_t status0; 642 uint8_t status1; 643 uint8_t status2; 644 /* Command FIFO */ 645 uint8_t *fifo; 646 int32_t fifo_size; 647 uint32_t data_pos; 648 uint32_t data_len; 649 uint8_t data_state; 650 uint8_t data_dir; 651 uint8_t eot; /* last wanted sector */ 652 /* States kept only to be returned back */ 653 /* precompensation */ 654 uint8_t precomp_trk; 655 uint8_t config; 656 uint8_t lock; 657 /* Power down config (also with status regB access mode */ 658 uint8_t pwrd; 659 /* Floppy drives */ 660 uint8_t num_floppies; 661 FDrive drives[MAX_FD]; 662 int reset_sensei; 663 uint32_t check_media_rate; 664 FloppyDriveType fallback; /* type=auto failure fallback */ 665 /* Timers state */ 666 uint8_t timer0; 667 uint8_t timer1; 668 }; 669 670 static FloppyDriveType get_fallback_drive_type(FDrive *drv) 671 { 672 return drv->fdctrl->fallback; 673 } 674 675 #define TYPE_SYSBUS_FDC "base-sysbus-fdc" 676 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC) 677 678 typedef struct FDCtrlSysBus { 679 /*< private >*/ 680 SysBusDevice parent_obj; 681 /*< public >*/ 682 683 struct FDCtrl state; 684 } FDCtrlSysBus; 685 686 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC) 687 688 typedef struct FDCtrlISABus { 689 ISADevice parent_obj; 690 691 uint32_t iobase; 692 uint32_t irq; 693 uint32_t dma; 694 struct FDCtrl state; 695 int32_t bootindexA; 696 int32_t bootindexB; 697 } FDCtrlISABus; 698 699 static uint32_t fdctrl_read (void *opaque, uint32_t reg) 700 { 701 FDCtrl *fdctrl = opaque; 702 uint32_t retval; 703 704 reg &= 7; 705 switch (reg) { 706 case FD_REG_SRA: 707 retval = fdctrl_read_statusA(fdctrl); 708 break; 709 case FD_REG_SRB: 710 retval = fdctrl_read_statusB(fdctrl); 711 break; 712 case FD_REG_DOR: 713 retval = fdctrl_read_dor(fdctrl); 714 break; 715 case FD_REG_TDR: 716 retval = fdctrl_read_tape(fdctrl); 717 break; 718 case FD_REG_MSR: 719 retval = fdctrl_read_main_status(fdctrl); 720 break; 721 case FD_REG_FIFO: 722 retval = fdctrl_read_data(fdctrl); 723 break; 724 case FD_REG_DIR: 725 retval = fdctrl_read_dir(fdctrl); 726 break; 727 default: 728 retval = (uint32_t)(-1); 729 break; 730 } 731 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); 732 733 return retval; 734 } 735 736 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) 737 { 738 FDCtrl *fdctrl = opaque; 739 740 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); 741 742 reg &= 7; 743 switch (reg) { 744 case FD_REG_DOR: 745 fdctrl_write_dor(fdctrl, value); 746 break; 747 case FD_REG_TDR: 748 fdctrl_write_tape(fdctrl, value); 749 break; 750 case FD_REG_DSR: 751 fdctrl_write_rate(fdctrl, value); 752 break; 753 case FD_REG_FIFO: 754 fdctrl_write_data(fdctrl, value); 755 break; 756 case FD_REG_CCR: 757 fdctrl_write_ccr(fdctrl, value); 758 break; 759 default: 760 break; 761 } 762 } 763 764 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg, 765 unsigned ize) 766 { 767 return fdctrl_read(opaque, (uint32_t)reg); 768 } 769 770 static void fdctrl_write_mem (void *opaque, hwaddr reg, 771 uint64_t value, unsigned size) 772 { 773 fdctrl_write(opaque, (uint32_t)reg, value); 774 } 775 776 static const MemoryRegionOps fdctrl_mem_ops = { 777 .read = fdctrl_read_mem, 778 .write = fdctrl_write_mem, 779 .endianness = DEVICE_NATIVE_ENDIAN, 780 }; 781 782 static const MemoryRegionOps fdctrl_mem_strict_ops = { 783 .read = fdctrl_read_mem, 784 .write = fdctrl_write_mem, 785 .endianness = DEVICE_NATIVE_ENDIAN, 786 .valid = { 787 .min_access_size = 1, 788 .max_access_size = 1, 789 }, 790 }; 791 792 static bool fdrive_media_changed_needed(void *opaque) 793 { 794 FDrive *drive = opaque; 795 796 return (drive->media_inserted && drive->media_changed != 1); 797 } 798 799 static const VMStateDescription vmstate_fdrive_media_changed = { 800 .name = "fdrive/media_changed", 801 .version_id = 1, 802 .minimum_version_id = 1, 803 .needed = fdrive_media_changed_needed, 804 .fields = (VMStateField[]) { 805 VMSTATE_UINT8(media_changed, FDrive), 806 VMSTATE_END_OF_LIST() 807 } 808 }; 809 810 static bool fdrive_media_rate_needed(void *opaque) 811 { 812 FDrive *drive = opaque; 813 814 return drive->fdctrl->check_media_rate; 815 } 816 817 static const VMStateDescription vmstate_fdrive_media_rate = { 818 .name = "fdrive/media_rate", 819 .version_id = 1, 820 .minimum_version_id = 1, 821 .needed = fdrive_media_rate_needed, 822 .fields = (VMStateField[]) { 823 VMSTATE_UINT8(media_rate, FDrive), 824 VMSTATE_END_OF_LIST() 825 } 826 }; 827 828 static bool fdrive_perpendicular_needed(void *opaque) 829 { 830 FDrive *drive = opaque; 831 832 return drive->perpendicular != 0; 833 } 834 835 static const VMStateDescription vmstate_fdrive_perpendicular = { 836 .name = "fdrive/perpendicular", 837 .version_id = 1, 838 .minimum_version_id = 1, 839 .needed = fdrive_perpendicular_needed, 840 .fields = (VMStateField[]) { 841 VMSTATE_UINT8(perpendicular, FDrive), 842 VMSTATE_END_OF_LIST() 843 } 844 }; 845 846 static int fdrive_post_load(void *opaque, int version_id) 847 { 848 fd_revalidate(opaque); 849 return 0; 850 } 851 852 static const VMStateDescription vmstate_fdrive = { 853 .name = "fdrive", 854 .version_id = 1, 855 .minimum_version_id = 1, 856 .post_load = fdrive_post_load, 857 .fields = (VMStateField[]) { 858 VMSTATE_UINT8(head, FDrive), 859 VMSTATE_UINT8(track, FDrive), 860 VMSTATE_UINT8(sect, FDrive), 861 VMSTATE_END_OF_LIST() 862 }, 863 .subsections = (const VMStateDescription*[]) { 864 &vmstate_fdrive_media_changed, 865 &vmstate_fdrive_media_rate, 866 &vmstate_fdrive_perpendicular, 867 NULL 868 } 869 }; 870 871 /* 872 * Reconstructs the phase from register values according to the logic that was 873 * implemented in qemu 2.3. This is the default value that is used if the phase 874 * subsection is not present on migration. 875 * 876 * Don't change this function to reflect newer qemu versions, it is part of 877 * the migration ABI. 878 */ 879 static int reconstruct_phase(FDCtrl *fdctrl) 880 { 881 if (fdctrl->msr & FD_MSR_NONDMA) { 882 return FD_PHASE_EXECUTION; 883 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) { 884 /* qemu 2.3 disabled RQM only during DMA transfers */ 885 return FD_PHASE_EXECUTION; 886 } else if (fdctrl->msr & FD_MSR_DIO) { 887 return FD_PHASE_RESULT; 888 } else { 889 return FD_PHASE_COMMAND; 890 } 891 } 892 893 static void fdc_pre_save(void *opaque) 894 { 895 FDCtrl *s = opaque; 896 897 s->dor_vmstate = s->dor | GET_CUR_DRV(s); 898 } 899 900 static int fdc_pre_load(void *opaque) 901 { 902 FDCtrl *s = opaque; 903 s->phase = FD_PHASE_RECONSTRUCT; 904 return 0; 905 } 906 907 static int fdc_post_load(void *opaque, int version_id) 908 { 909 FDCtrl *s = opaque; 910 911 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); 912 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; 913 914 if (s->phase == FD_PHASE_RECONSTRUCT) { 915 s->phase = reconstruct_phase(s); 916 } 917 918 return 0; 919 } 920 921 static bool fdc_reset_sensei_needed(void *opaque) 922 { 923 FDCtrl *s = opaque; 924 925 return s->reset_sensei != 0; 926 } 927 928 static const VMStateDescription vmstate_fdc_reset_sensei = { 929 .name = "fdc/reset_sensei", 930 .version_id = 1, 931 .minimum_version_id = 1, 932 .needed = fdc_reset_sensei_needed, 933 .fields = (VMStateField[]) { 934 VMSTATE_INT32(reset_sensei, FDCtrl), 935 VMSTATE_END_OF_LIST() 936 } 937 }; 938 939 static bool fdc_result_timer_needed(void *opaque) 940 { 941 FDCtrl *s = opaque; 942 943 return timer_pending(s->result_timer); 944 } 945 946 static const VMStateDescription vmstate_fdc_result_timer = { 947 .name = "fdc/result_timer", 948 .version_id = 1, 949 .minimum_version_id = 1, 950 .needed = fdc_result_timer_needed, 951 .fields = (VMStateField[]) { 952 VMSTATE_TIMER_PTR(result_timer, FDCtrl), 953 VMSTATE_END_OF_LIST() 954 } 955 }; 956 957 static bool fdc_phase_needed(void *opaque) 958 { 959 FDCtrl *fdctrl = opaque; 960 961 return reconstruct_phase(fdctrl) != fdctrl->phase; 962 } 963 964 static const VMStateDescription vmstate_fdc_phase = { 965 .name = "fdc/phase", 966 .version_id = 1, 967 .minimum_version_id = 1, 968 .needed = fdc_phase_needed, 969 .fields = (VMStateField[]) { 970 VMSTATE_UINT8(phase, FDCtrl), 971 VMSTATE_END_OF_LIST() 972 } 973 }; 974 975 static const VMStateDescription vmstate_fdc = { 976 .name = "fdc", 977 .version_id = 2, 978 .minimum_version_id = 2, 979 .pre_save = fdc_pre_save, 980 .pre_load = fdc_pre_load, 981 .post_load = fdc_post_load, 982 .fields = (VMStateField[]) { 983 /* Controller State */ 984 VMSTATE_UINT8(sra, FDCtrl), 985 VMSTATE_UINT8(srb, FDCtrl), 986 VMSTATE_UINT8(dor_vmstate, FDCtrl), 987 VMSTATE_UINT8(tdr, FDCtrl), 988 VMSTATE_UINT8(dsr, FDCtrl), 989 VMSTATE_UINT8(msr, FDCtrl), 990 VMSTATE_UINT8(status0, FDCtrl), 991 VMSTATE_UINT8(status1, FDCtrl), 992 VMSTATE_UINT8(status2, FDCtrl), 993 /* Command FIFO */ 994 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, 995 uint8_t), 996 VMSTATE_UINT32(data_pos, FDCtrl), 997 VMSTATE_UINT32(data_len, FDCtrl), 998 VMSTATE_UINT8(data_state, FDCtrl), 999 VMSTATE_UINT8(data_dir, FDCtrl), 1000 VMSTATE_UINT8(eot, FDCtrl), 1001 /* States kept only to be returned back */ 1002 VMSTATE_UINT8(timer0, FDCtrl), 1003 VMSTATE_UINT8(timer1, FDCtrl), 1004 VMSTATE_UINT8(precomp_trk, FDCtrl), 1005 VMSTATE_UINT8(config, FDCtrl), 1006 VMSTATE_UINT8(lock, FDCtrl), 1007 VMSTATE_UINT8(pwrd, FDCtrl), 1008 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl), 1009 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, 1010 vmstate_fdrive, FDrive), 1011 VMSTATE_END_OF_LIST() 1012 }, 1013 .subsections = (const VMStateDescription*[]) { 1014 &vmstate_fdc_reset_sensei, 1015 &vmstate_fdc_result_timer, 1016 &vmstate_fdc_phase, 1017 NULL 1018 } 1019 }; 1020 1021 static void fdctrl_external_reset_sysbus(DeviceState *d) 1022 { 1023 FDCtrlSysBus *sys = SYSBUS_FDC(d); 1024 FDCtrl *s = &sys->state; 1025 1026 fdctrl_reset(s, 0); 1027 } 1028 1029 static void fdctrl_external_reset_isa(DeviceState *d) 1030 { 1031 FDCtrlISABus *isa = ISA_FDC(d); 1032 FDCtrl *s = &isa->state; 1033 1034 fdctrl_reset(s, 0); 1035 } 1036 1037 static void fdctrl_handle_tc(void *opaque, int irq, int level) 1038 { 1039 //FDCtrl *s = opaque; 1040 1041 if (level) { 1042 // XXX 1043 FLOPPY_DPRINTF("TC pulsed\n"); 1044 } 1045 } 1046 1047 /* Change IRQ state */ 1048 static void fdctrl_reset_irq(FDCtrl *fdctrl) 1049 { 1050 fdctrl->status0 = 0; 1051 if (!(fdctrl->sra & FD_SRA_INTPEND)) 1052 return; 1053 FLOPPY_DPRINTF("Reset interrupt\n"); 1054 qemu_set_irq(fdctrl->irq, 0); 1055 fdctrl->sra &= ~FD_SRA_INTPEND; 1056 } 1057 1058 static void fdctrl_raise_irq(FDCtrl *fdctrl) 1059 { 1060 if (!(fdctrl->sra & FD_SRA_INTPEND)) { 1061 qemu_set_irq(fdctrl->irq, 1); 1062 fdctrl->sra |= FD_SRA_INTPEND; 1063 } 1064 1065 fdctrl->reset_sensei = 0; 1066 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); 1067 } 1068 1069 /* Reset controller */ 1070 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) 1071 { 1072 int i; 1073 1074 FLOPPY_DPRINTF("reset controller\n"); 1075 fdctrl_reset_irq(fdctrl); 1076 /* Initialise controller */ 1077 fdctrl->sra = 0; 1078 fdctrl->srb = 0xc0; 1079 if (!fdctrl->drives[1].blk) { 1080 fdctrl->sra |= FD_SRA_nDRV2; 1081 } 1082 fdctrl->cur_drv = 0; 1083 fdctrl->dor = FD_DOR_nRESET; 1084 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; 1085 fdctrl->msr = FD_MSR_RQM; 1086 fdctrl->reset_sensei = 0; 1087 timer_del(fdctrl->result_timer); 1088 /* FIFO state */ 1089 fdctrl->data_pos = 0; 1090 fdctrl->data_len = 0; 1091 fdctrl->data_state = 0; 1092 fdctrl->data_dir = FD_DIR_WRITE; 1093 for (i = 0; i < MAX_FD; i++) 1094 fd_recalibrate(&fdctrl->drives[i]); 1095 fdctrl_to_command_phase(fdctrl); 1096 if (do_irq) { 1097 fdctrl->status0 |= FD_SR0_RDYCHG; 1098 fdctrl_raise_irq(fdctrl); 1099 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; 1100 } 1101 } 1102 1103 static inline FDrive *drv0(FDCtrl *fdctrl) 1104 { 1105 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; 1106 } 1107 1108 static inline FDrive *drv1(FDCtrl *fdctrl) 1109 { 1110 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) 1111 return &fdctrl->drives[1]; 1112 else 1113 return &fdctrl->drives[0]; 1114 } 1115 1116 #if MAX_FD == 4 1117 static inline FDrive *drv2(FDCtrl *fdctrl) 1118 { 1119 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) 1120 return &fdctrl->drives[2]; 1121 else 1122 return &fdctrl->drives[1]; 1123 } 1124 1125 static inline FDrive *drv3(FDCtrl *fdctrl) 1126 { 1127 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) 1128 return &fdctrl->drives[3]; 1129 else 1130 return &fdctrl->drives[2]; 1131 } 1132 #endif 1133 1134 static FDrive *get_cur_drv(FDCtrl *fdctrl) 1135 { 1136 switch (fdctrl->cur_drv) { 1137 case 0: return drv0(fdctrl); 1138 case 1: return drv1(fdctrl); 1139 #if MAX_FD == 4 1140 case 2: return drv2(fdctrl); 1141 case 3: return drv3(fdctrl); 1142 #endif 1143 default: return NULL; 1144 } 1145 } 1146 1147 /* Status A register : 0x00 (read-only) */ 1148 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) 1149 { 1150 uint32_t retval = fdctrl->sra; 1151 1152 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); 1153 1154 return retval; 1155 } 1156 1157 /* Status B register : 0x01 (read-only) */ 1158 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) 1159 { 1160 uint32_t retval = fdctrl->srb; 1161 1162 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); 1163 1164 return retval; 1165 } 1166 1167 /* Digital output register : 0x02 */ 1168 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) 1169 { 1170 uint32_t retval = fdctrl->dor; 1171 1172 /* Selected drive */ 1173 retval |= fdctrl->cur_drv; 1174 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); 1175 1176 return retval; 1177 } 1178 1179 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) 1180 { 1181 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); 1182 1183 /* Motors */ 1184 if (value & FD_DOR_MOTEN0) 1185 fdctrl->srb |= FD_SRB_MTR0; 1186 else 1187 fdctrl->srb &= ~FD_SRB_MTR0; 1188 if (value & FD_DOR_MOTEN1) 1189 fdctrl->srb |= FD_SRB_MTR1; 1190 else 1191 fdctrl->srb &= ~FD_SRB_MTR1; 1192 1193 /* Drive */ 1194 if (value & 1) 1195 fdctrl->srb |= FD_SRB_DR0; 1196 else 1197 fdctrl->srb &= ~FD_SRB_DR0; 1198 1199 /* Reset */ 1200 if (!(value & FD_DOR_nRESET)) { 1201 if (fdctrl->dor & FD_DOR_nRESET) { 1202 FLOPPY_DPRINTF("controller enter RESET state\n"); 1203 } 1204 } else { 1205 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1206 FLOPPY_DPRINTF("controller out of RESET state\n"); 1207 fdctrl_reset(fdctrl, 1); 1208 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1209 } 1210 } 1211 /* Selected drive */ 1212 fdctrl->cur_drv = value & FD_DOR_SELMASK; 1213 1214 fdctrl->dor = value; 1215 } 1216 1217 /* Tape drive register : 0x03 */ 1218 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) 1219 { 1220 uint32_t retval = fdctrl->tdr; 1221 1222 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); 1223 1224 return retval; 1225 } 1226 1227 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) 1228 { 1229 /* Reset mode */ 1230 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1231 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1232 return; 1233 } 1234 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); 1235 /* Disk boot selection indicator */ 1236 fdctrl->tdr = value & FD_TDR_BOOTSEL; 1237 /* Tape indicators: never allow */ 1238 } 1239 1240 /* Main status register : 0x04 (read) */ 1241 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) 1242 { 1243 uint32_t retval = fdctrl->msr; 1244 1245 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1246 fdctrl->dor |= FD_DOR_nRESET; 1247 1248 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); 1249 1250 return retval; 1251 } 1252 1253 /* Data select rate register : 0x04 (write) */ 1254 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) 1255 { 1256 /* Reset mode */ 1257 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1258 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1259 return; 1260 } 1261 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); 1262 /* Reset: autoclear */ 1263 if (value & FD_DSR_SWRESET) { 1264 fdctrl->dor &= ~FD_DOR_nRESET; 1265 fdctrl_reset(fdctrl, 1); 1266 fdctrl->dor |= FD_DOR_nRESET; 1267 } 1268 if (value & FD_DSR_PWRDOWN) { 1269 fdctrl_reset(fdctrl, 1); 1270 } 1271 fdctrl->dsr = value; 1272 } 1273 1274 /* Configuration control register: 0x07 (write) */ 1275 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) 1276 { 1277 /* Reset mode */ 1278 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1279 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1280 return; 1281 } 1282 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); 1283 1284 /* Only the rate selection bits used in AT mode, and we 1285 * store those in the DSR. 1286 */ 1287 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | 1288 (value & FD_DSR_DRATEMASK); 1289 } 1290 1291 static int fdctrl_media_changed(FDrive *drv) 1292 { 1293 return drv->media_changed; 1294 } 1295 1296 /* Digital input register : 0x07 (read-only) */ 1297 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) 1298 { 1299 uint32_t retval = 0; 1300 1301 if (fdctrl_media_changed(get_cur_drv(fdctrl))) { 1302 retval |= FD_DIR_DSKCHG; 1303 } 1304 if (retval != 0) { 1305 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); 1306 } 1307 1308 return retval; 1309 } 1310 1311 /* Clear the FIFO and update the state for receiving the next command */ 1312 static void fdctrl_to_command_phase(FDCtrl *fdctrl) 1313 { 1314 fdctrl->phase = FD_PHASE_COMMAND; 1315 fdctrl->data_dir = FD_DIR_WRITE; 1316 fdctrl->data_pos = 0; 1317 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */ 1318 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); 1319 fdctrl->msr |= FD_MSR_RQM; 1320 } 1321 1322 /* Update the state to allow the guest to read out the command status. 1323 * @fifo_len is the number of result bytes to be read out. */ 1324 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len) 1325 { 1326 fdctrl->phase = FD_PHASE_RESULT; 1327 fdctrl->data_dir = FD_DIR_READ; 1328 fdctrl->data_len = fifo_len; 1329 fdctrl->data_pos = 0; 1330 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; 1331 } 1332 1333 /* Set an error: unimplemented/unknown command */ 1334 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) 1335 { 1336 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n", 1337 fdctrl->fifo[0]); 1338 fdctrl->fifo[0] = FD_SR0_INVCMD; 1339 fdctrl_to_result_phase(fdctrl, 1); 1340 } 1341 1342 /* Seek to next sector 1343 * returns 0 when end of track reached (for DBL_SIDES on head 1) 1344 * otherwise returns 1 1345 */ 1346 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) 1347 { 1348 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", 1349 cur_drv->head, cur_drv->track, cur_drv->sect, 1350 fd_sector(cur_drv)); 1351 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an 1352 error in fact */ 1353 uint8_t new_head = cur_drv->head; 1354 uint8_t new_track = cur_drv->track; 1355 uint8_t new_sect = cur_drv->sect; 1356 1357 int ret = 1; 1358 1359 if (new_sect >= cur_drv->last_sect || 1360 new_sect == fdctrl->eot) { 1361 new_sect = 1; 1362 if (FD_MULTI_TRACK(fdctrl->data_state)) { 1363 if (new_head == 0 && 1364 (cur_drv->flags & FDISK_DBL_SIDES) != 0) { 1365 new_head = 1; 1366 } else { 1367 new_head = 0; 1368 new_track++; 1369 fdctrl->status0 |= FD_SR0_SEEK; 1370 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) { 1371 ret = 0; 1372 } 1373 } 1374 } else { 1375 fdctrl->status0 |= FD_SR0_SEEK; 1376 new_track++; 1377 ret = 0; 1378 } 1379 if (ret == 1) { 1380 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", 1381 new_head, new_track, new_sect, fd_sector(cur_drv)); 1382 } 1383 } else { 1384 new_sect++; 1385 } 1386 fd_seek(cur_drv, new_head, new_track, new_sect, 1); 1387 return ret; 1388 } 1389 1390 /* Callback for transfer end (stop or abort) */ 1391 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, 1392 uint8_t status1, uint8_t status2) 1393 { 1394 FDrive *cur_drv; 1395 cur_drv = get_cur_drv(fdctrl); 1396 1397 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD); 1398 fdctrl->status0 |= GET_CUR_DRV(fdctrl); 1399 if (cur_drv->head) { 1400 fdctrl->status0 |= FD_SR0_HEAD; 1401 } 1402 fdctrl->status0 |= status0; 1403 1404 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", 1405 status0, status1, status2, fdctrl->status0); 1406 fdctrl->fifo[0] = fdctrl->status0; 1407 fdctrl->fifo[1] = status1; 1408 fdctrl->fifo[2] = status2; 1409 fdctrl->fifo[3] = cur_drv->track; 1410 fdctrl->fifo[4] = cur_drv->head; 1411 fdctrl->fifo[5] = cur_drv->sect; 1412 fdctrl->fifo[6] = FD_SECTOR_SC; 1413 fdctrl->data_dir = FD_DIR_READ; 1414 if (!(fdctrl->msr & FD_MSR_NONDMA)) { 1415 DMA_release_DREQ(fdctrl->dma_chann); 1416 } 1417 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 1418 fdctrl->msr &= ~FD_MSR_NONDMA; 1419 1420 fdctrl_to_result_phase(fdctrl, 7); 1421 fdctrl_raise_irq(fdctrl); 1422 } 1423 1424 /* Prepare a data transfer (either DMA or FIFO) */ 1425 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) 1426 { 1427 FDrive *cur_drv; 1428 uint8_t kh, kt, ks; 1429 1430 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1431 cur_drv = get_cur_drv(fdctrl); 1432 kt = fdctrl->fifo[2]; 1433 kh = fdctrl->fifo[3]; 1434 ks = fdctrl->fifo[4]; 1435 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", 1436 GET_CUR_DRV(fdctrl), kh, kt, ks, 1437 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1438 NUM_SIDES(cur_drv))); 1439 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1440 case 2: 1441 /* sect too big */ 1442 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1443 fdctrl->fifo[3] = kt; 1444 fdctrl->fifo[4] = kh; 1445 fdctrl->fifo[5] = ks; 1446 return; 1447 case 3: 1448 /* track too big */ 1449 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1450 fdctrl->fifo[3] = kt; 1451 fdctrl->fifo[4] = kh; 1452 fdctrl->fifo[5] = ks; 1453 return; 1454 case 4: 1455 /* No seek enabled */ 1456 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1457 fdctrl->fifo[3] = kt; 1458 fdctrl->fifo[4] = kh; 1459 fdctrl->fifo[5] = ks; 1460 return; 1461 case 1: 1462 fdctrl->status0 |= FD_SR0_SEEK; 1463 break; 1464 default: 1465 break; 1466 } 1467 1468 /* Check the data rate. If the programmed data rate does not match 1469 * the currently inserted medium, the operation has to fail. */ 1470 if (fdctrl->check_media_rate && 1471 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 1472 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n", 1473 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 1474 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 1475 fdctrl->fifo[3] = kt; 1476 fdctrl->fifo[4] = kh; 1477 fdctrl->fifo[5] = ks; 1478 return; 1479 } 1480 1481 /* Set the FIFO state */ 1482 fdctrl->data_dir = direction; 1483 fdctrl->data_pos = 0; 1484 assert(fdctrl->msr & FD_MSR_CMDBUSY); 1485 if (fdctrl->fifo[0] & 0x80) 1486 fdctrl->data_state |= FD_STATE_MULTI; 1487 else 1488 fdctrl->data_state &= ~FD_STATE_MULTI; 1489 if (fdctrl->fifo[5] == 0) { 1490 fdctrl->data_len = fdctrl->fifo[8]; 1491 } else { 1492 int tmp; 1493 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); 1494 tmp = (fdctrl->fifo[6] - ks + 1); 1495 if (fdctrl->fifo[0] & 0x80) 1496 tmp += fdctrl->fifo[6]; 1497 fdctrl->data_len *= tmp; 1498 } 1499 fdctrl->eot = fdctrl->fifo[6]; 1500 if (fdctrl->dor & FD_DOR_DMAEN) { 1501 int dma_mode; 1502 /* DMA transfer are enabled. Check if DMA channel is well programmed */ 1503 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); 1504 dma_mode = (dma_mode >> 2) & 3; 1505 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", 1506 dma_mode, direction, 1507 (128 << fdctrl->fifo[5]) * 1508 (cur_drv->last_sect - ks + 1), fdctrl->data_len); 1509 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL || 1510 direction == FD_DIR_SCANH) && dma_mode == 0) || 1511 (direction == FD_DIR_WRITE && dma_mode == 2) || 1512 (direction == FD_DIR_READ && dma_mode == 1) || 1513 (direction == FD_DIR_VERIFY)) { 1514 /* No access is allowed until DMA transfer has completed */ 1515 fdctrl->msr &= ~FD_MSR_RQM; 1516 if (direction != FD_DIR_VERIFY) { 1517 /* Now, we just have to wait for the DMA controller to 1518 * recall us... 1519 */ 1520 DMA_hold_DREQ(fdctrl->dma_chann); 1521 DMA_schedule(); 1522 } else { 1523 /* Start transfer */ 1524 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, 1525 fdctrl->data_len); 1526 } 1527 return; 1528 } else { 1529 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode, 1530 direction); 1531 } 1532 } 1533 FLOPPY_DPRINTF("start non-DMA transfer\n"); 1534 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM; 1535 if (direction != FD_DIR_WRITE) 1536 fdctrl->msr |= FD_MSR_DIO; 1537 /* IO based transfer: calculate len */ 1538 fdctrl_raise_irq(fdctrl); 1539 } 1540 1541 /* Prepare a transfer of deleted data */ 1542 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) 1543 { 1544 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n"); 1545 1546 /* We don't handle deleted data, 1547 * so we don't return *ANYTHING* 1548 */ 1549 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1550 } 1551 1552 /* handlers for DMA transfers */ 1553 static int fdctrl_transfer_handler (void *opaque, int nchan, 1554 int dma_pos, int dma_len) 1555 { 1556 FDCtrl *fdctrl; 1557 FDrive *cur_drv; 1558 int len, start_pos, rel_pos; 1559 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; 1560 1561 fdctrl = opaque; 1562 if (fdctrl->msr & FD_MSR_RQM) { 1563 FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); 1564 return 0; 1565 } 1566 cur_drv = get_cur_drv(fdctrl); 1567 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || 1568 fdctrl->data_dir == FD_DIR_SCANH) 1569 status2 = FD_SR2_SNS; 1570 if (dma_len > fdctrl->data_len) 1571 dma_len = fdctrl->data_len; 1572 if (cur_drv->blk == NULL) { 1573 if (fdctrl->data_dir == FD_DIR_WRITE) 1574 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1575 else 1576 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1577 len = 0; 1578 goto transfer_error; 1579 } 1580 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1581 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { 1582 len = dma_len - fdctrl->data_pos; 1583 if (len + rel_pos > FD_SECTOR_LEN) 1584 len = FD_SECTOR_LEN - rel_pos; 1585 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " 1586 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, 1587 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, 1588 cur_drv->track, cur_drv->sect, fd_sector(cur_drv), 1589 fd_sector(cur_drv) * FD_SECTOR_LEN); 1590 if (fdctrl->data_dir != FD_DIR_WRITE || 1591 len < FD_SECTOR_LEN || rel_pos != 0) { 1592 /* READ & SCAN commands and realign to a sector for WRITE */ 1593 if (blk_read(cur_drv->blk, fd_sector(cur_drv), 1594 fdctrl->fifo, 1) < 0) { 1595 FLOPPY_DPRINTF("Floppy: error getting sector %d\n", 1596 fd_sector(cur_drv)); 1597 /* Sure, image size is too small... */ 1598 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1599 } 1600 } 1601 switch (fdctrl->data_dir) { 1602 case FD_DIR_READ: 1603 /* READ commands */ 1604 DMA_write_memory (nchan, fdctrl->fifo + rel_pos, 1605 fdctrl->data_pos, len); 1606 break; 1607 case FD_DIR_WRITE: 1608 /* WRITE commands */ 1609 if (cur_drv->ro) { 1610 /* Handle readonly medium early, no need to do DMA, touch the 1611 * LED or attempt any writes. A real floppy doesn't attempt 1612 * to write to readonly media either. */ 1613 fdctrl_stop_transfer(fdctrl, 1614 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, 1615 0x00); 1616 goto transfer_error; 1617 } 1618 1619 DMA_read_memory (nchan, fdctrl->fifo + rel_pos, 1620 fdctrl->data_pos, len); 1621 if (blk_write(cur_drv->blk, fd_sector(cur_drv), 1622 fdctrl->fifo, 1) < 0) { 1623 FLOPPY_DPRINTF("error writing sector %d\n", 1624 fd_sector(cur_drv)); 1625 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1626 goto transfer_error; 1627 } 1628 break; 1629 case FD_DIR_VERIFY: 1630 /* VERIFY commands */ 1631 break; 1632 default: 1633 /* SCAN commands */ 1634 { 1635 uint8_t tmpbuf[FD_SECTOR_LEN]; 1636 int ret; 1637 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); 1638 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); 1639 if (ret == 0) { 1640 status2 = FD_SR2_SEH; 1641 goto end_transfer; 1642 } 1643 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || 1644 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { 1645 status2 = 0x00; 1646 goto end_transfer; 1647 } 1648 } 1649 break; 1650 } 1651 fdctrl->data_pos += len; 1652 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1653 if (rel_pos == 0) { 1654 /* Seek to next sector */ 1655 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) 1656 break; 1657 } 1658 } 1659 end_transfer: 1660 len = fdctrl->data_pos - start_pos; 1661 FLOPPY_DPRINTF("end transfer %d %d %d\n", 1662 fdctrl->data_pos, len, fdctrl->data_len); 1663 if (fdctrl->data_dir == FD_DIR_SCANE || 1664 fdctrl->data_dir == FD_DIR_SCANL || 1665 fdctrl->data_dir == FD_DIR_SCANH) 1666 status2 = FD_SR2_SEH; 1667 fdctrl->data_len -= len; 1668 fdctrl_stop_transfer(fdctrl, status0, status1, status2); 1669 transfer_error: 1670 1671 return len; 1672 } 1673 1674 /* Data register : 0x05 */ 1675 static uint32_t fdctrl_read_data(FDCtrl *fdctrl) 1676 { 1677 FDrive *cur_drv; 1678 uint32_t retval = 0; 1679 uint32_t pos; 1680 1681 cur_drv = get_cur_drv(fdctrl); 1682 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1683 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { 1684 FLOPPY_DPRINTF("error: controller not ready for reading\n"); 1685 return 0; 1686 } 1687 1688 /* If data_len spans multiple sectors, the current position in the FIFO 1689 * wraps around while fdctrl->data_pos is the real position in the whole 1690 * request. */ 1691 pos = fdctrl->data_pos; 1692 pos %= FD_SECTOR_LEN; 1693 1694 switch (fdctrl->phase) { 1695 case FD_PHASE_EXECUTION: 1696 assert(fdctrl->msr & FD_MSR_NONDMA); 1697 if (pos == 0) { 1698 if (fdctrl->data_pos != 0) 1699 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1700 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1701 fd_sector(cur_drv)); 1702 return 0; 1703 } 1704 if (blk_read(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) 1705 < 0) { 1706 FLOPPY_DPRINTF("error getting sector %d\n", 1707 fd_sector(cur_drv)); 1708 /* Sure, image size is too small... */ 1709 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1710 } 1711 } 1712 1713 if (++fdctrl->data_pos == fdctrl->data_len) { 1714 fdctrl->msr &= ~FD_MSR_RQM; 1715 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1716 } 1717 break; 1718 1719 case FD_PHASE_RESULT: 1720 assert(!(fdctrl->msr & FD_MSR_NONDMA)); 1721 if (++fdctrl->data_pos == fdctrl->data_len) { 1722 fdctrl->msr &= ~FD_MSR_RQM; 1723 fdctrl_to_command_phase(fdctrl); 1724 fdctrl_reset_irq(fdctrl); 1725 } 1726 break; 1727 1728 case FD_PHASE_COMMAND: 1729 default: 1730 abort(); 1731 } 1732 1733 retval = fdctrl->fifo[pos]; 1734 FLOPPY_DPRINTF("data register: 0x%02x\n", retval); 1735 1736 return retval; 1737 } 1738 1739 static void fdctrl_format_sector(FDCtrl *fdctrl) 1740 { 1741 FDrive *cur_drv; 1742 uint8_t kh, kt, ks; 1743 1744 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1745 cur_drv = get_cur_drv(fdctrl); 1746 kt = fdctrl->fifo[6]; 1747 kh = fdctrl->fifo[7]; 1748 ks = fdctrl->fifo[8]; 1749 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", 1750 GET_CUR_DRV(fdctrl), kh, kt, ks, 1751 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1752 NUM_SIDES(cur_drv))); 1753 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1754 case 2: 1755 /* sect too big */ 1756 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1757 fdctrl->fifo[3] = kt; 1758 fdctrl->fifo[4] = kh; 1759 fdctrl->fifo[5] = ks; 1760 return; 1761 case 3: 1762 /* track too big */ 1763 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1764 fdctrl->fifo[3] = kt; 1765 fdctrl->fifo[4] = kh; 1766 fdctrl->fifo[5] = ks; 1767 return; 1768 case 4: 1769 /* No seek enabled */ 1770 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1771 fdctrl->fifo[3] = kt; 1772 fdctrl->fifo[4] = kh; 1773 fdctrl->fifo[5] = ks; 1774 return; 1775 case 1: 1776 fdctrl->status0 |= FD_SR0_SEEK; 1777 break; 1778 default: 1779 break; 1780 } 1781 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1782 if (cur_drv->blk == NULL || 1783 blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1784 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv)); 1785 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1786 } else { 1787 if (cur_drv->sect == cur_drv->last_sect) { 1788 fdctrl->data_state &= ~FD_STATE_FORMAT; 1789 /* Last sector done */ 1790 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1791 } else { 1792 /* More to do */ 1793 fdctrl->data_pos = 0; 1794 fdctrl->data_len = 4; 1795 } 1796 } 1797 } 1798 1799 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) 1800 { 1801 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; 1802 fdctrl->fifo[0] = fdctrl->lock << 4; 1803 fdctrl_to_result_phase(fdctrl, 1); 1804 } 1805 1806 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) 1807 { 1808 FDrive *cur_drv = get_cur_drv(fdctrl); 1809 1810 /* Drives position */ 1811 fdctrl->fifo[0] = drv0(fdctrl)->track; 1812 fdctrl->fifo[1] = drv1(fdctrl)->track; 1813 #if MAX_FD == 4 1814 fdctrl->fifo[2] = drv2(fdctrl)->track; 1815 fdctrl->fifo[3] = drv3(fdctrl)->track; 1816 #else 1817 fdctrl->fifo[2] = 0; 1818 fdctrl->fifo[3] = 0; 1819 #endif 1820 /* timers */ 1821 fdctrl->fifo[4] = fdctrl->timer0; 1822 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); 1823 fdctrl->fifo[6] = cur_drv->last_sect; 1824 fdctrl->fifo[7] = (fdctrl->lock << 7) | 1825 (cur_drv->perpendicular << 2); 1826 fdctrl->fifo[8] = fdctrl->config; 1827 fdctrl->fifo[9] = fdctrl->precomp_trk; 1828 fdctrl_to_result_phase(fdctrl, 10); 1829 } 1830 1831 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) 1832 { 1833 /* Controller's version */ 1834 fdctrl->fifo[0] = fdctrl->version; 1835 fdctrl_to_result_phase(fdctrl, 1); 1836 } 1837 1838 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) 1839 { 1840 fdctrl->fifo[0] = 0x41; /* Stepping 1 */ 1841 fdctrl_to_result_phase(fdctrl, 1); 1842 } 1843 1844 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) 1845 { 1846 FDrive *cur_drv = get_cur_drv(fdctrl); 1847 1848 /* Drives position */ 1849 drv0(fdctrl)->track = fdctrl->fifo[3]; 1850 drv1(fdctrl)->track = fdctrl->fifo[4]; 1851 #if MAX_FD == 4 1852 drv2(fdctrl)->track = fdctrl->fifo[5]; 1853 drv3(fdctrl)->track = fdctrl->fifo[6]; 1854 #endif 1855 /* timers */ 1856 fdctrl->timer0 = fdctrl->fifo[7]; 1857 fdctrl->timer1 = fdctrl->fifo[8]; 1858 cur_drv->last_sect = fdctrl->fifo[9]; 1859 fdctrl->lock = fdctrl->fifo[10] >> 7; 1860 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; 1861 fdctrl->config = fdctrl->fifo[11]; 1862 fdctrl->precomp_trk = fdctrl->fifo[12]; 1863 fdctrl->pwrd = fdctrl->fifo[13]; 1864 fdctrl_to_command_phase(fdctrl); 1865 } 1866 1867 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) 1868 { 1869 FDrive *cur_drv = get_cur_drv(fdctrl); 1870 1871 fdctrl->fifo[0] = 0; 1872 fdctrl->fifo[1] = 0; 1873 /* Drives position */ 1874 fdctrl->fifo[2] = drv0(fdctrl)->track; 1875 fdctrl->fifo[3] = drv1(fdctrl)->track; 1876 #if MAX_FD == 4 1877 fdctrl->fifo[4] = drv2(fdctrl)->track; 1878 fdctrl->fifo[5] = drv3(fdctrl)->track; 1879 #else 1880 fdctrl->fifo[4] = 0; 1881 fdctrl->fifo[5] = 0; 1882 #endif 1883 /* timers */ 1884 fdctrl->fifo[6] = fdctrl->timer0; 1885 fdctrl->fifo[7] = fdctrl->timer1; 1886 fdctrl->fifo[8] = cur_drv->last_sect; 1887 fdctrl->fifo[9] = (fdctrl->lock << 7) | 1888 (cur_drv->perpendicular << 2); 1889 fdctrl->fifo[10] = fdctrl->config; 1890 fdctrl->fifo[11] = fdctrl->precomp_trk; 1891 fdctrl->fifo[12] = fdctrl->pwrd; 1892 fdctrl->fifo[13] = 0; 1893 fdctrl->fifo[14] = 0; 1894 fdctrl_to_result_phase(fdctrl, 15); 1895 } 1896 1897 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) 1898 { 1899 FDrive *cur_drv = get_cur_drv(fdctrl); 1900 1901 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1902 timer_mod(fdctrl->result_timer, 1903 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50)); 1904 } 1905 1906 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) 1907 { 1908 FDrive *cur_drv; 1909 1910 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1911 cur_drv = get_cur_drv(fdctrl); 1912 fdctrl->data_state |= FD_STATE_FORMAT; 1913 if (fdctrl->fifo[0] & 0x80) 1914 fdctrl->data_state |= FD_STATE_MULTI; 1915 else 1916 fdctrl->data_state &= ~FD_STATE_MULTI; 1917 cur_drv->bps = 1918 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; 1919 #if 0 1920 cur_drv->last_sect = 1921 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : 1922 fdctrl->fifo[3] / 2; 1923 #else 1924 cur_drv->last_sect = fdctrl->fifo[3]; 1925 #endif 1926 /* TODO: implement format using DMA expected by the Bochs BIOS 1927 * and Linux fdformat (read 3 bytes per sector via DMA and fill 1928 * the sector with the specified fill byte 1929 */ 1930 fdctrl->data_state &= ~FD_STATE_FORMAT; 1931 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1932 } 1933 1934 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) 1935 { 1936 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; 1937 fdctrl->timer1 = fdctrl->fifo[2] >> 1; 1938 if (fdctrl->fifo[2] & 1) 1939 fdctrl->dor &= ~FD_DOR_DMAEN; 1940 else 1941 fdctrl->dor |= FD_DOR_DMAEN; 1942 /* No result back */ 1943 fdctrl_to_command_phase(fdctrl); 1944 } 1945 1946 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) 1947 { 1948 FDrive *cur_drv; 1949 1950 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1951 cur_drv = get_cur_drv(fdctrl); 1952 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1953 /* 1 Byte status back */ 1954 fdctrl->fifo[0] = (cur_drv->ro << 6) | 1955 (cur_drv->track == 0 ? 0x10 : 0x00) | 1956 (cur_drv->head << 2) | 1957 GET_CUR_DRV(fdctrl) | 1958 0x28; 1959 fdctrl_to_result_phase(fdctrl, 1); 1960 } 1961 1962 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) 1963 { 1964 FDrive *cur_drv; 1965 1966 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1967 cur_drv = get_cur_drv(fdctrl); 1968 fd_recalibrate(cur_drv); 1969 fdctrl_to_command_phase(fdctrl); 1970 /* Raise Interrupt */ 1971 fdctrl->status0 |= FD_SR0_SEEK; 1972 fdctrl_raise_irq(fdctrl); 1973 } 1974 1975 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) 1976 { 1977 FDrive *cur_drv = get_cur_drv(fdctrl); 1978 1979 if (fdctrl->reset_sensei > 0) { 1980 fdctrl->fifo[0] = 1981 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; 1982 fdctrl->reset_sensei--; 1983 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) { 1984 fdctrl->fifo[0] = FD_SR0_INVCMD; 1985 fdctrl_to_result_phase(fdctrl, 1); 1986 return; 1987 } else { 1988 fdctrl->fifo[0] = 1989 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0)) 1990 | GET_CUR_DRV(fdctrl); 1991 } 1992 1993 fdctrl->fifo[1] = cur_drv->track; 1994 fdctrl_to_result_phase(fdctrl, 2); 1995 fdctrl_reset_irq(fdctrl); 1996 fdctrl->status0 = FD_SR0_RDYCHG; 1997 } 1998 1999 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) 2000 { 2001 FDrive *cur_drv; 2002 2003 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2004 cur_drv = get_cur_drv(fdctrl); 2005 fdctrl_to_command_phase(fdctrl); 2006 /* The seek command just sends step pulses to the drive and doesn't care if 2007 * there is a medium inserted of if it's banging the head against the drive. 2008 */ 2009 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1); 2010 /* Raise Interrupt */ 2011 fdctrl->status0 |= FD_SR0_SEEK; 2012 fdctrl_raise_irq(fdctrl); 2013 } 2014 2015 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) 2016 { 2017 FDrive *cur_drv = get_cur_drv(fdctrl); 2018 2019 if (fdctrl->fifo[1] & 0x80) 2020 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; 2021 /* No result back */ 2022 fdctrl_to_command_phase(fdctrl); 2023 } 2024 2025 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) 2026 { 2027 fdctrl->config = fdctrl->fifo[2]; 2028 fdctrl->precomp_trk = fdctrl->fifo[3]; 2029 /* No result back */ 2030 fdctrl_to_command_phase(fdctrl); 2031 } 2032 2033 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) 2034 { 2035 fdctrl->pwrd = fdctrl->fifo[1]; 2036 fdctrl->fifo[0] = fdctrl->fifo[1]; 2037 fdctrl_to_result_phase(fdctrl, 1); 2038 } 2039 2040 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) 2041 { 2042 /* No result back */ 2043 fdctrl_to_command_phase(fdctrl); 2044 } 2045 2046 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) 2047 { 2048 FDrive *cur_drv = get_cur_drv(fdctrl); 2049 uint32_t pos; 2050 2051 pos = fdctrl->data_pos - 1; 2052 pos %= FD_SECTOR_LEN; 2053 if (fdctrl->fifo[pos] & 0x80) { 2054 /* Command parameters done */ 2055 if (fdctrl->fifo[pos] & 0x40) { 2056 fdctrl->fifo[0] = fdctrl->fifo[1]; 2057 fdctrl->fifo[2] = 0; 2058 fdctrl->fifo[3] = 0; 2059 fdctrl_to_result_phase(fdctrl, 4); 2060 } else { 2061 fdctrl_to_command_phase(fdctrl); 2062 } 2063 } else if (fdctrl->data_len > 7) { 2064 /* ERROR */ 2065 fdctrl->fifo[0] = 0x80 | 2066 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); 2067 fdctrl_to_result_phase(fdctrl, 1); 2068 } 2069 } 2070 2071 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) 2072 { 2073 FDrive *cur_drv; 2074 2075 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2076 cur_drv = get_cur_drv(fdctrl); 2077 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { 2078 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1, 2079 cur_drv->sect, 1); 2080 } else { 2081 fd_seek(cur_drv, cur_drv->head, 2082 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1); 2083 } 2084 fdctrl_to_command_phase(fdctrl); 2085 /* Raise Interrupt */ 2086 fdctrl->status0 |= FD_SR0_SEEK; 2087 fdctrl_raise_irq(fdctrl); 2088 } 2089 2090 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) 2091 { 2092 FDrive *cur_drv; 2093 2094 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2095 cur_drv = get_cur_drv(fdctrl); 2096 if (fdctrl->fifo[2] > cur_drv->track) { 2097 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1); 2098 } else { 2099 fd_seek(cur_drv, cur_drv->head, 2100 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1); 2101 } 2102 fdctrl_to_command_phase(fdctrl); 2103 /* Raise Interrupt */ 2104 fdctrl->status0 |= FD_SR0_SEEK; 2105 fdctrl_raise_irq(fdctrl); 2106 } 2107 2108 /* 2109 * Handlers for the execution phase of each command 2110 */ 2111 typedef struct FDCtrlCommand { 2112 uint8_t value; 2113 uint8_t mask; 2114 const char* name; 2115 int parameters; 2116 void (*handler)(FDCtrl *fdctrl, int direction); 2117 int direction; 2118 } FDCtrlCommand; 2119 2120 static const FDCtrlCommand handlers[] = { 2121 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, 2122 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, 2123 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, 2124 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, 2125 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, 2126 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, 2127 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, 2128 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ 2129 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ 2130 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, 2131 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, 2132 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY }, 2133 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, 2134 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, 2135 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, 2136 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, 2137 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, 2138 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, 2139 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, 2140 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, 2141 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, 2142 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, 2143 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, 2144 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, 2145 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, 2146 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, 2147 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, 2148 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, 2149 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, 2150 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, 2151 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ 2152 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ 2153 }; 2154 /* Associate command to an index in the 'handlers' array */ 2155 static uint8_t command_to_handler[256]; 2156 2157 static const FDCtrlCommand *get_command(uint8_t cmd) 2158 { 2159 int idx; 2160 2161 idx = command_to_handler[cmd]; 2162 FLOPPY_DPRINTF("%s command\n", handlers[idx].name); 2163 return &handlers[idx]; 2164 } 2165 2166 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) 2167 { 2168 FDrive *cur_drv; 2169 const FDCtrlCommand *cmd; 2170 uint32_t pos; 2171 2172 /* Reset mode */ 2173 if (!(fdctrl->dor & FD_DOR_nRESET)) { 2174 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 2175 return; 2176 } 2177 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { 2178 FLOPPY_DPRINTF("error: controller not ready for writing\n"); 2179 return; 2180 } 2181 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 2182 2183 FLOPPY_DPRINTF("%s: %02x\n", __func__, value); 2184 2185 /* If data_len spans multiple sectors, the current position in the FIFO 2186 * wraps around while fdctrl->data_pos is the real position in the whole 2187 * request. */ 2188 pos = fdctrl->data_pos++; 2189 pos %= FD_SECTOR_LEN; 2190 fdctrl->fifo[pos] = value; 2191 2192 if (fdctrl->data_pos == fdctrl->data_len) { 2193 fdctrl->msr &= ~FD_MSR_RQM; 2194 } 2195 2196 switch (fdctrl->phase) { 2197 case FD_PHASE_EXECUTION: 2198 /* For DMA requests, RQM should be cleared during execution phase, so 2199 * we would have errored out above. */ 2200 assert(fdctrl->msr & FD_MSR_NONDMA); 2201 2202 /* FIFO data write */ 2203 if (pos == FD_SECTOR_LEN - 1 || 2204 fdctrl->data_pos == fdctrl->data_len) { 2205 cur_drv = get_cur_drv(fdctrl); 2206 if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) 2207 < 0) { 2208 FLOPPY_DPRINTF("error writing sector %d\n", 2209 fd_sector(cur_drv)); 2210 break; 2211 } 2212 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 2213 FLOPPY_DPRINTF("error seeking to next sector %d\n", 2214 fd_sector(cur_drv)); 2215 break; 2216 } 2217 } 2218 2219 /* Switch to result phase when done with the transfer */ 2220 if (fdctrl->data_pos == fdctrl->data_len) { 2221 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2222 } 2223 break; 2224 2225 case FD_PHASE_COMMAND: 2226 assert(!(fdctrl->msr & FD_MSR_NONDMA)); 2227 assert(fdctrl->data_pos < FD_SECTOR_LEN); 2228 2229 if (pos == 0) { 2230 /* The first byte specifies the command. Now we start reading 2231 * as many parameters as this command requires. */ 2232 cmd = get_command(value); 2233 fdctrl->data_len = cmd->parameters + 1; 2234 if (cmd->parameters) { 2235 fdctrl->msr |= FD_MSR_RQM; 2236 } 2237 fdctrl->msr |= FD_MSR_CMDBUSY; 2238 } 2239 2240 if (fdctrl->data_pos == fdctrl->data_len) { 2241 /* We have all parameters now, execute the command */ 2242 fdctrl->phase = FD_PHASE_EXECUTION; 2243 2244 if (fdctrl->data_state & FD_STATE_FORMAT) { 2245 fdctrl_format_sector(fdctrl); 2246 break; 2247 } 2248 2249 cmd = get_command(fdctrl->fifo[0]); 2250 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name); 2251 cmd->handler(fdctrl, cmd->direction); 2252 } 2253 break; 2254 2255 case FD_PHASE_RESULT: 2256 default: 2257 abort(); 2258 } 2259 } 2260 2261 static void fdctrl_result_timer(void *opaque) 2262 { 2263 FDCtrl *fdctrl = opaque; 2264 FDrive *cur_drv = get_cur_drv(fdctrl); 2265 2266 /* Pretend we are spinning. 2267 * This is needed for Coherent, which uses READ ID to check for 2268 * sector interleaving. 2269 */ 2270 if (cur_drv->last_sect != 0) { 2271 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; 2272 } 2273 /* READ_ID can't automatically succeed! */ 2274 if (fdctrl->check_media_rate && 2275 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 2276 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n", 2277 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 2278 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 2279 } else { 2280 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2281 } 2282 } 2283 2284 static void fdctrl_change_cb(void *opaque, bool load) 2285 { 2286 FDrive *drive = opaque; 2287 2288 drive->media_inserted = load && drive->blk && blk_is_inserted(drive->blk); 2289 2290 drive->media_changed = 1; 2291 drive->media_validated = false; 2292 fd_revalidate(drive); 2293 } 2294 2295 static bool fdctrl_is_tray_open(void *opaque) 2296 { 2297 FDrive *drive = opaque; 2298 return !drive->media_inserted; 2299 } 2300 2301 static const BlockDevOps fdctrl_block_ops = { 2302 .change_media_cb = fdctrl_change_cb, 2303 .is_tray_open = fdctrl_is_tray_open, 2304 }; 2305 2306 /* Init functions */ 2307 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp) 2308 { 2309 unsigned int i; 2310 FDrive *drive; 2311 2312 for (i = 0; i < MAX_FD; i++) { 2313 drive = &fdctrl->drives[i]; 2314 drive->fdctrl = fdctrl; 2315 2316 if (drive->blk) { 2317 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) { 2318 error_setg(errp, "fdc doesn't support drive option werror"); 2319 return; 2320 } 2321 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) { 2322 error_setg(errp, "fdc doesn't support drive option rerror"); 2323 return; 2324 } 2325 } 2326 2327 fd_init(drive); 2328 if (drive->blk) { 2329 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive); 2330 drive->media_inserted = blk_is_inserted(drive->blk); 2331 pick_drive_type(drive); 2332 } 2333 fd_revalidate(drive); 2334 } 2335 } 2336 2337 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds) 2338 { 2339 DeviceState *dev; 2340 ISADevice *isadev; 2341 2342 isadev = isa_try_create(bus, TYPE_ISA_FDC); 2343 if (!isadev) { 2344 return NULL; 2345 } 2346 dev = DEVICE(isadev); 2347 2348 if (fds[0]) { 2349 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), 2350 &error_fatal); 2351 } 2352 if (fds[1]) { 2353 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), 2354 &error_fatal); 2355 } 2356 qdev_init_nofail(dev); 2357 2358 return isadev; 2359 } 2360 2361 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, 2362 hwaddr mmio_base, DriveInfo **fds) 2363 { 2364 FDCtrl *fdctrl; 2365 DeviceState *dev; 2366 SysBusDevice *sbd; 2367 FDCtrlSysBus *sys; 2368 2369 dev = qdev_create(NULL, "sysbus-fdc"); 2370 sys = SYSBUS_FDC(dev); 2371 fdctrl = &sys->state; 2372 fdctrl->dma_chann = dma_chann; /* FIXME */ 2373 if (fds[0]) { 2374 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), 2375 &error_fatal); 2376 } 2377 if (fds[1]) { 2378 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), 2379 &error_fatal); 2380 } 2381 qdev_init_nofail(dev); 2382 sbd = SYS_BUS_DEVICE(dev); 2383 sysbus_connect_irq(sbd, 0, irq); 2384 sysbus_mmio_map(sbd, 0, mmio_base); 2385 } 2386 2387 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, 2388 DriveInfo **fds, qemu_irq *fdc_tc) 2389 { 2390 DeviceState *dev; 2391 FDCtrlSysBus *sys; 2392 2393 dev = qdev_create(NULL, "SUNW,fdtwo"); 2394 if (fds[0]) { 2395 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]), 2396 &error_fatal); 2397 } 2398 qdev_init_nofail(dev); 2399 sys = SYSBUS_FDC(dev); 2400 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); 2401 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base); 2402 *fdc_tc = qdev_get_gpio_in(dev, 0); 2403 } 2404 2405 static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp) 2406 { 2407 int i, j; 2408 static int command_tables_inited = 0; 2409 2410 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) { 2411 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'"); 2412 } 2413 2414 /* Fill 'command_to_handler' lookup table */ 2415 if (!command_tables_inited) { 2416 command_tables_inited = 1; 2417 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { 2418 for (j = 0; j < sizeof(command_to_handler); j++) { 2419 if ((j & handlers[i].mask) == handlers[i].value) { 2420 command_to_handler[j] = i; 2421 } 2422 } 2423 } 2424 } 2425 2426 FLOPPY_DPRINTF("init controller\n"); 2427 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); 2428 fdctrl->fifo_size = 512; 2429 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2430 fdctrl_result_timer, fdctrl); 2431 2432 fdctrl->version = 0x90; /* Intel 82078 controller */ 2433 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ 2434 fdctrl->num_floppies = MAX_FD; 2435 2436 if (fdctrl->dma_chann != -1) { 2437 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl); 2438 } 2439 fdctrl_connect_drives(fdctrl, errp); 2440 } 2441 2442 static const MemoryRegionPortio fdc_portio_list[] = { 2443 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, 2444 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, 2445 PORTIO_END_OF_LIST(), 2446 }; 2447 2448 static void isabus_fdc_realize(DeviceState *dev, Error **errp) 2449 { 2450 ISADevice *isadev = ISA_DEVICE(dev); 2451 FDCtrlISABus *isa = ISA_FDC(dev); 2452 FDCtrl *fdctrl = &isa->state; 2453 Error *err = NULL; 2454 2455 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl, 2456 "fdc"); 2457 2458 isa_init_irq(isadev, &fdctrl->irq, isa->irq); 2459 fdctrl->dma_chann = isa->dma; 2460 2461 qdev_set_legacy_instance_id(dev, isa->iobase, 2); 2462 fdctrl_realize_common(fdctrl, &err); 2463 if (err != NULL) { 2464 error_propagate(errp, err); 2465 return; 2466 } 2467 } 2468 2469 static void sysbus_fdc_initfn(Object *obj) 2470 { 2471 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2472 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2473 FDCtrl *fdctrl = &sys->state; 2474 2475 fdctrl->dma_chann = -1; 2476 2477 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl, 2478 "fdc", 0x08); 2479 sysbus_init_mmio(sbd, &fdctrl->iomem); 2480 } 2481 2482 static void sun4m_fdc_initfn(Object *obj) 2483 { 2484 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2485 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2486 FDCtrl *fdctrl = &sys->state; 2487 2488 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops, 2489 fdctrl, "fdctrl", 0x08); 2490 sysbus_init_mmio(sbd, &fdctrl->iomem); 2491 } 2492 2493 static void sysbus_fdc_common_initfn(Object *obj) 2494 { 2495 DeviceState *dev = DEVICE(obj); 2496 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 2497 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2498 FDCtrl *fdctrl = &sys->state; 2499 2500 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */ 2501 2502 sysbus_init_irq(sbd, &fdctrl->irq); 2503 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1); 2504 } 2505 2506 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp) 2507 { 2508 FDCtrlSysBus *sys = SYSBUS_FDC(dev); 2509 FDCtrl *fdctrl = &sys->state; 2510 2511 fdctrl_realize_common(fdctrl, errp); 2512 } 2513 2514 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i) 2515 { 2516 FDCtrlISABus *isa = ISA_FDC(fdc); 2517 2518 return isa->state.drives[i].drive; 2519 } 2520 2521 static const VMStateDescription vmstate_isa_fdc ={ 2522 .name = "fdc", 2523 .version_id = 2, 2524 .minimum_version_id = 2, 2525 .fields = (VMStateField[]) { 2526 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl), 2527 VMSTATE_END_OF_LIST() 2528 } 2529 }; 2530 2531 static Property isa_fdc_properties[] = { 2532 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0), 2533 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6), 2534 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2), 2535 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk), 2536 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk), 2537 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate, 2538 0, true), 2539 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlISABus, state.drives[0].drive, 2540 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2541 FloppyDriveType), 2542 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlISABus, state.drives[1].drive, 2543 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2544 FloppyDriveType), 2545 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback, 2546 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type, 2547 FloppyDriveType), 2548 DEFINE_PROP_END_OF_LIST(), 2549 }; 2550 2551 static void isabus_fdc_class_init(ObjectClass *klass, void *data) 2552 { 2553 DeviceClass *dc = DEVICE_CLASS(klass); 2554 2555 dc->realize = isabus_fdc_realize; 2556 dc->fw_name = "fdc"; 2557 dc->reset = fdctrl_external_reset_isa; 2558 dc->vmsd = &vmstate_isa_fdc; 2559 dc->props = isa_fdc_properties; 2560 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2561 } 2562 2563 static void isabus_fdc_instance_init(Object *obj) 2564 { 2565 FDCtrlISABus *isa = ISA_FDC(obj); 2566 2567 device_add_bootindex_property(obj, &isa->bootindexA, 2568 "bootindexA", "/floppy@0", 2569 DEVICE(obj), NULL); 2570 device_add_bootindex_property(obj, &isa->bootindexB, 2571 "bootindexB", "/floppy@1", 2572 DEVICE(obj), NULL); 2573 } 2574 2575 static const TypeInfo isa_fdc_info = { 2576 .name = TYPE_ISA_FDC, 2577 .parent = TYPE_ISA_DEVICE, 2578 .instance_size = sizeof(FDCtrlISABus), 2579 .class_init = isabus_fdc_class_init, 2580 .instance_init = isabus_fdc_instance_init, 2581 }; 2582 2583 static const VMStateDescription vmstate_sysbus_fdc ={ 2584 .name = "fdc", 2585 .version_id = 2, 2586 .minimum_version_id = 2, 2587 .fields = (VMStateField[]) { 2588 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl), 2589 VMSTATE_END_OF_LIST() 2590 } 2591 }; 2592 2593 static Property sysbus_fdc_properties[] = { 2594 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk), 2595 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk), 2596 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlSysBus, state.drives[0].drive, 2597 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2598 FloppyDriveType), 2599 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlSysBus, state.drives[1].drive, 2600 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2601 FloppyDriveType), 2602 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback, 2603 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type, 2604 FloppyDriveType), 2605 DEFINE_PROP_END_OF_LIST(), 2606 }; 2607 2608 static void sysbus_fdc_class_init(ObjectClass *klass, void *data) 2609 { 2610 DeviceClass *dc = DEVICE_CLASS(klass); 2611 2612 dc->props = sysbus_fdc_properties; 2613 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2614 } 2615 2616 static const TypeInfo sysbus_fdc_info = { 2617 .name = "sysbus-fdc", 2618 .parent = TYPE_SYSBUS_FDC, 2619 .instance_init = sysbus_fdc_initfn, 2620 .class_init = sysbus_fdc_class_init, 2621 }; 2622 2623 static Property sun4m_fdc_properties[] = { 2624 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk), 2625 DEFINE_PROP_DEFAULT("fdtype", FDCtrlSysBus, state.drives[0].drive, 2626 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2627 FloppyDriveType), 2628 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback, 2629 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type, 2630 FloppyDriveType), 2631 DEFINE_PROP_END_OF_LIST(), 2632 }; 2633 2634 static void sun4m_fdc_class_init(ObjectClass *klass, void *data) 2635 { 2636 DeviceClass *dc = DEVICE_CLASS(klass); 2637 2638 dc->props = sun4m_fdc_properties; 2639 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2640 } 2641 2642 static const TypeInfo sun4m_fdc_info = { 2643 .name = "SUNW,fdtwo", 2644 .parent = TYPE_SYSBUS_FDC, 2645 .instance_init = sun4m_fdc_initfn, 2646 .class_init = sun4m_fdc_class_init, 2647 }; 2648 2649 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data) 2650 { 2651 DeviceClass *dc = DEVICE_CLASS(klass); 2652 2653 dc->realize = sysbus_fdc_common_realize; 2654 dc->reset = fdctrl_external_reset_sysbus; 2655 dc->vmsd = &vmstate_sysbus_fdc; 2656 } 2657 2658 static const TypeInfo sysbus_fdc_type_info = { 2659 .name = TYPE_SYSBUS_FDC, 2660 .parent = TYPE_SYS_BUS_DEVICE, 2661 .instance_size = sizeof(FDCtrlSysBus), 2662 .instance_init = sysbus_fdc_common_initfn, 2663 .abstract = true, 2664 .class_init = sysbus_fdc_common_class_init, 2665 }; 2666 2667 static void fdc_register_types(void) 2668 { 2669 type_register_static(&isa_fdc_info); 2670 type_register_static(&sysbus_fdc_type_info); 2671 type_register_static(&sysbus_fdc_info); 2672 type_register_static(&sun4m_fdc_info); 2673 } 2674 2675 type_init(fdc_register_types) 2676