1 /* 2 * QEMU Floppy disk emulator (Intel 82078) 3 * 4 * Copyright (c) 2003, 2007 Jocelyn Mayer 5 * Copyright (c) 2008 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * The controller is used in Sun4m systems in a slightly different 27 * way. There are changes in DOR register and DMA is not available. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/block/fdc.h" 33 #include "qemu/error-report.h" 34 #include "qemu/timer.h" 35 #include "hw/isa/isa.h" 36 #include "hw/sysbus.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/blockdev.h" 39 #include "sysemu/sysemu.h" 40 #include "qemu/log.h" 41 42 /********************************************************/ 43 /* debug Floppy devices */ 44 //#define DEBUG_FLOPPY 45 46 #ifdef DEBUG_FLOPPY 47 #define FLOPPY_DPRINTF(fmt, ...) \ 48 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) 49 #else 50 #define FLOPPY_DPRINTF(fmt, ...) 51 #endif 52 53 /********************************************************/ 54 /* Floppy drive emulation */ 55 56 typedef enum FDriveRate { 57 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */ 58 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */ 59 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */ 60 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */ 61 } FDriveRate; 62 63 typedef enum FDriveSize { 64 FDRIVE_SIZE_UNKNOWN, 65 FDRIVE_SIZE_350, 66 FDRIVE_SIZE_525, 67 } FDriveSize; 68 69 typedef struct FDFormat { 70 FloppyDriveType drive; 71 uint8_t last_sect; 72 uint8_t max_track; 73 uint8_t max_head; 74 FDriveRate rate; 75 } FDFormat; 76 77 /* In many cases, the total sector size of a format is enough to uniquely 78 * identify it. However, there are some total sector collisions between 79 * formats of different physical size, and these are noted below by 80 * highlighting the total sector size for entries with collisions. */ 81 static const FDFormat fd_formats[] = { 82 /* First entry is default format */ 83 /* 1.44 MB 3"1/2 floppy disks */ 84 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */ 85 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */ 86 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, }, 87 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, }, 88 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, }, 89 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, }, 90 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, }, 91 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, }, 92 /* 2.88 MB 3"1/2 floppy disks */ 93 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, }, 94 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, }, 95 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, }, 96 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, }, 97 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, }, 98 /* 720 kB 3"1/2 floppy disks */ 99 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */ 100 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, }, 101 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, }, 102 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, }, 103 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, }, 104 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, }, 105 /* 1.2 MB 5"1/4 floppy disks */ 106 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, }, 107 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */ 108 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, }, 109 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, }, 110 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */ 111 /* 720 kB 5"1/4 floppy disks */ 112 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */ 113 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, }, 114 /* 360 kB 5"1/4 floppy disks */ 115 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */ 116 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, }, 117 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, }, 118 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, }, 119 /* 320 kB 5"1/4 floppy disks */ 120 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, }, 121 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, }, 122 /* 360 kB must match 5"1/4 better than 3"1/2... */ 123 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */ 124 /* end */ 125 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, }, 126 }; 127 128 static FDriveSize drive_size(FloppyDriveType drive) 129 { 130 switch (drive) { 131 case FLOPPY_DRIVE_TYPE_120: 132 return FDRIVE_SIZE_525; 133 case FLOPPY_DRIVE_TYPE_144: 134 case FLOPPY_DRIVE_TYPE_288: 135 return FDRIVE_SIZE_350; 136 default: 137 return FDRIVE_SIZE_UNKNOWN; 138 } 139 } 140 141 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) 142 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) 143 144 /* Will always be a fixed parameter for us */ 145 #define FD_SECTOR_LEN 512 146 #define FD_SECTOR_SC 2 /* Sector size code */ 147 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ 148 149 typedef struct FDCtrl FDCtrl; 150 151 /* Floppy disk drive emulation */ 152 typedef enum FDiskFlags { 153 FDISK_DBL_SIDES = 0x01, 154 } FDiskFlags; 155 156 typedef struct FDrive { 157 FDCtrl *fdctrl; 158 BlockBackend *blk; 159 /* Drive status */ 160 FloppyDriveType drive; /* CMOS drive type */ 161 uint8_t perpendicular; /* 2.88 MB access mode */ 162 /* Position */ 163 uint8_t head; 164 uint8_t track; 165 uint8_t sect; 166 /* Media */ 167 FloppyDriveType disk; /* Current disk type */ 168 FDiskFlags flags; 169 uint8_t last_sect; /* Nb sector per track */ 170 uint8_t max_track; /* Nb of tracks */ 171 uint16_t bps; /* Bytes per sector */ 172 uint8_t ro; /* Is read-only */ 173 uint8_t media_changed; /* Is media changed */ 174 uint8_t media_rate; /* Data rate of medium */ 175 176 bool media_validated; /* Have we validated the media? */ 177 } FDrive; 178 179 180 static FloppyDriveType get_fallback_drive_type(FDrive *drv); 181 182 /* Hack: FD_SEEK is expected to work on empty drives. However, QEMU 183 * currently goes through some pains to keep seeks within the bounds 184 * established by last_sect and max_track. Correcting this is difficult, 185 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel. 186 * 187 * For now: allow empty drives to have large bounds so we can seek around, 188 * with the understanding that when a diskette is inserted, the bounds will 189 * properly tighten to match the geometry of that inserted medium. 190 */ 191 static void fd_empty_seek_hack(FDrive *drv) 192 { 193 drv->last_sect = 0xFF; 194 drv->max_track = 0xFF; 195 } 196 197 static void fd_init(FDrive *drv) 198 { 199 /* Drive */ 200 drv->perpendicular = 0; 201 /* Disk */ 202 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 203 drv->last_sect = 0; 204 drv->max_track = 0; 205 drv->ro = true; 206 drv->media_changed = 1; 207 } 208 209 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) 210 211 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, 212 uint8_t last_sect, uint8_t num_sides) 213 { 214 return (((track * num_sides) + head) * last_sect) + sect - 1; 215 } 216 217 /* Returns current position, in sectors, for given drive */ 218 static int fd_sector(FDrive *drv) 219 { 220 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, 221 NUM_SIDES(drv)); 222 } 223 224 /* Seek to a new position: 225 * returns 0 if already on right track 226 * returns 1 if track changed 227 * returns 2 if track is invalid 228 * returns 3 if sector is invalid 229 * returns 4 if seek is disabled 230 */ 231 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, 232 int enable_seek) 233 { 234 uint32_t sector; 235 int ret; 236 237 if (track > drv->max_track || 238 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { 239 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 240 head, track, sect, 1, 241 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 242 drv->max_track, drv->last_sect); 243 return 2; 244 } 245 if (sect > drv->last_sect) { 246 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 247 head, track, sect, 1, 248 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 249 drv->max_track, drv->last_sect); 250 return 3; 251 } 252 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); 253 ret = 0; 254 if (sector != fd_sector(drv)) { 255 #if 0 256 if (!enable_seek) { 257 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x" 258 " (max=%d %02x %02x)\n", 259 head, track, sect, 1, drv->max_track, 260 drv->last_sect); 261 return 4; 262 } 263 #endif 264 drv->head = head; 265 if (drv->track != track) { 266 if (drv->blk != NULL && blk_is_inserted(drv->blk)) { 267 drv->media_changed = 0; 268 } 269 ret = 1; 270 } 271 drv->track = track; 272 drv->sect = sect; 273 } 274 275 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) { 276 ret = 2; 277 } 278 279 return ret; 280 } 281 282 /* Set drive back to track 0 */ 283 static void fd_recalibrate(FDrive *drv) 284 { 285 FLOPPY_DPRINTF("recalibrate\n"); 286 fd_seek(drv, 0, 0, 1, 1); 287 } 288 289 /** 290 * Determine geometry based on inserted diskette. 291 * Will not operate on an empty drive. 292 * 293 * @return: 0 on success, -1 if the drive is empty. 294 */ 295 static int pick_geometry(FDrive *drv) 296 { 297 BlockBackend *blk = drv->blk; 298 const FDFormat *parse; 299 uint64_t nb_sectors, size; 300 int i; 301 int match, size_match, type_match; 302 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO; 303 304 /* We can only pick a geometry if we have a diskette. */ 305 if (!drv->blk || !blk_is_inserted(drv->blk) || 306 drv->drive == FLOPPY_DRIVE_TYPE_NONE) 307 { 308 return -1; 309 } 310 311 /* We need to determine the likely geometry of the inserted medium. 312 * In order of preference, we look for: 313 * (1) The same drive type and number of sectors, 314 * (2) The same diskette size and number of sectors, 315 * (3) The same drive type. 316 * 317 * In all cases, matches that occur higher in the drive table will take 318 * precedence over matches that occur later in the table. 319 */ 320 blk_get_geometry(blk, &nb_sectors); 321 match = size_match = type_match = -1; 322 for (i = 0; ; i++) { 323 parse = &fd_formats[i]; 324 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) { 325 break; 326 } 327 size = (parse->max_head + 1) * parse->max_track * parse->last_sect; 328 if (nb_sectors == size) { 329 if (magic || parse->drive == drv->drive) { 330 /* (1) perfect match -- nb_sectors and drive type */ 331 goto out; 332 } else if (drive_size(parse->drive) == drive_size(drv->drive)) { 333 /* (2) size match -- nb_sectors and physical medium size */ 334 match = (match == -1) ? i : match; 335 } else { 336 /* This is suspicious -- Did the user misconfigure? */ 337 size_match = (size_match == -1) ? i : size_match; 338 } 339 } else if (type_match == -1) { 340 if ((parse->drive == drv->drive) || 341 (magic && (parse->drive == get_fallback_drive_type(drv)))) { 342 /* (3) type match -- nb_sectors mismatch, but matches the type 343 * specified explicitly by the user, or matches the fallback 344 * default type when using the drive autodetect mechanism */ 345 type_match = i; 346 } 347 } 348 } 349 350 /* No exact match found */ 351 if (match == -1) { 352 if (size_match != -1) { 353 parse = &fd_formats[size_match]; 354 FLOPPY_DPRINTF("User requested floppy drive type '%s', " 355 "but inserted medium appears to be a " 356 "%d sector '%s' type\n", 357 FloppyDriveType_lookup[drv->drive], 358 nb_sectors, 359 FloppyDriveType_lookup[parse->drive]); 360 } 361 match = type_match; 362 } 363 364 /* No match of any kind found -- fd_format is misconfigured, abort. */ 365 if (match == -1) { 366 error_setg(&error_abort, "No candidate geometries present in table " 367 " for floppy drive type '%s'", 368 FloppyDriveType_lookup[drv->drive]); 369 } 370 371 parse = &(fd_formats[match]); 372 373 out: 374 if (parse->max_head == 0) { 375 drv->flags &= ~FDISK_DBL_SIDES; 376 } else { 377 drv->flags |= FDISK_DBL_SIDES; 378 } 379 drv->max_track = parse->max_track; 380 drv->last_sect = parse->last_sect; 381 drv->disk = parse->drive; 382 drv->media_rate = parse->rate; 383 return 0; 384 } 385 386 static void pick_drive_type(FDrive *drv) 387 { 388 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) { 389 return; 390 } 391 392 if (pick_geometry(drv) == 0) { 393 drv->drive = drv->disk; 394 } else { 395 drv->drive = get_fallback_drive_type(drv); 396 } 397 398 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO); 399 } 400 401 /* Revalidate a disk drive after a disk change */ 402 static void fd_revalidate(FDrive *drv) 403 { 404 int rc; 405 406 FLOPPY_DPRINTF("revalidate\n"); 407 if (drv->blk != NULL) { 408 drv->ro = blk_is_read_only(drv->blk); 409 if (!blk_is_inserted(drv->blk)) { 410 FLOPPY_DPRINTF("No disk in drive\n"); 411 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 412 fd_empty_seek_hack(drv); 413 } else if (!drv->media_validated) { 414 rc = pick_geometry(drv); 415 if (rc) { 416 FLOPPY_DPRINTF("Could not validate floppy drive media"); 417 } else { 418 drv->media_validated = true; 419 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", 420 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1, 421 drv->max_track, drv->last_sect, 422 drv->ro ? "ro" : "rw"); 423 } 424 } 425 } else { 426 FLOPPY_DPRINTF("No drive connected\n"); 427 drv->last_sect = 0; 428 drv->max_track = 0; 429 drv->flags &= ~FDISK_DBL_SIDES; 430 drv->drive = FLOPPY_DRIVE_TYPE_NONE; 431 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 432 } 433 } 434 435 /********************************************************/ 436 /* Intel 82078 floppy disk controller emulation */ 437 438 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); 439 static void fdctrl_to_command_phase(FDCtrl *fdctrl); 440 static int fdctrl_transfer_handler (void *opaque, int nchan, 441 int dma_pos, int dma_len); 442 static void fdctrl_raise_irq(FDCtrl *fdctrl); 443 static FDrive *get_cur_drv(FDCtrl *fdctrl); 444 445 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); 446 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); 447 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); 448 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); 449 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); 450 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); 451 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); 452 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); 453 static uint32_t fdctrl_read_data(FDCtrl *fdctrl); 454 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); 455 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); 456 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); 457 458 enum { 459 FD_DIR_WRITE = 0, 460 FD_DIR_READ = 1, 461 FD_DIR_SCANE = 2, 462 FD_DIR_SCANL = 3, 463 FD_DIR_SCANH = 4, 464 FD_DIR_VERIFY = 5, 465 }; 466 467 enum { 468 FD_STATE_MULTI = 0x01, /* multi track flag */ 469 FD_STATE_FORMAT = 0x02, /* format flag */ 470 }; 471 472 enum { 473 FD_REG_SRA = 0x00, 474 FD_REG_SRB = 0x01, 475 FD_REG_DOR = 0x02, 476 FD_REG_TDR = 0x03, 477 FD_REG_MSR = 0x04, 478 FD_REG_DSR = 0x04, 479 FD_REG_FIFO = 0x05, 480 FD_REG_DIR = 0x07, 481 FD_REG_CCR = 0x07, 482 }; 483 484 enum { 485 FD_CMD_READ_TRACK = 0x02, 486 FD_CMD_SPECIFY = 0x03, 487 FD_CMD_SENSE_DRIVE_STATUS = 0x04, 488 FD_CMD_WRITE = 0x05, 489 FD_CMD_READ = 0x06, 490 FD_CMD_RECALIBRATE = 0x07, 491 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, 492 FD_CMD_WRITE_DELETED = 0x09, 493 FD_CMD_READ_ID = 0x0a, 494 FD_CMD_READ_DELETED = 0x0c, 495 FD_CMD_FORMAT_TRACK = 0x0d, 496 FD_CMD_DUMPREG = 0x0e, 497 FD_CMD_SEEK = 0x0f, 498 FD_CMD_VERSION = 0x10, 499 FD_CMD_SCAN_EQUAL = 0x11, 500 FD_CMD_PERPENDICULAR_MODE = 0x12, 501 FD_CMD_CONFIGURE = 0x13, 502 FD_CMD_LOCK = 0x14, 503 FD_CMD_VERIFY = 0x16, 504 FD_CMD_POWERDOWN_MODE = 0x17, 505 FD_CMD_PART_ID = 0x18, 506 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, 507 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, 508 FD_CMD_SAVE = 0x2e, 509 FD_CMD_OPTION = 0x33, 510 FD_CMD_RESTORE = 0x4e, 511 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, 512 FD_CMD_RELATIVE_SEEK_OUT = 0x8f, 513 FD_CMD_FORMAT_AND_WRITE = 0xcd, 514 FD_CMD_RELATIVE_SEEK_IN = 0xcf, 515 }; 516 517 enum { 518 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ 519 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ 520 FD_CONFIG_POLL = 0x10, /* Poll enabled */ 521 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ 522 FD_CONFIG_EIS = 0x40, /* No implied seeks */ 523 }; 524 525 enum { 526 FD_SR0_DS0 = 0x01, 527 FD_SR0_DS1 = 0x02, 528 FD_SR0_HEAD = 0x04, 529 FD_SR0_EQPMT = 0x10, 530 FD_SR0_SEEK = 0x20, 531 FD_SR0_ABNTERM = 0x40, 532 FD_SR0_INVCMD = 0x80, 533 FD_SR0_RDYCHG = 0xc0, 534 }; 535 536 enum { 537 FD_SR1_MA = 0x01, /* Missing address mark */ 538 FD_SR1_NW = 0x02, /* Not writable */ 539 FD_SR1_EC = 0x80, /* End of cylinder */ 540 }; 541 542 enum { 543 FD_SR2_SNS = 0x04, /* Scan not satisfied */ 544 FD_SR2_SEH = 0x08, /* Scan equal hit */ 545 }; 546 547 enum { 548 FD_SRA_DIR = 0x01, 549 FD_SRA_nWP = 0x02, 550 FD_SRA_nINDX = 0x04, 551 FD_SRA_HDSEL = 0x08, 552 FD_SRA_nTRK0 = 0x10, 553 FD_SRA_STEP = 0x20, 554 FD_SRA_nDRV2 = 0x40, 555 FD_SRA_INTPEND = 0x80, 556 }; 557 558 enum { 559 FD_SRB_MTR0 = 0x01, 560 FD_SRB_MTR1 = 0x02, 561 FD_SRB_WGATE = 0x04, 562 FD_SRB_RDATA = 0x08, 563 FD_SRB_WDATA = 0x10, 564 FD_SRB_DR0 = 0x20, 565 }; 566 567 enum { 568 #if MAX_FD == 4 569 FD_DOR_SELMASK = 0x03, 570 #else 571 FD_DOR_SELMASK = 0x01, 572 #endif 573 FD_DOR_nRESET = 0x04, 574 FD_DOR_DMAEN = 0x08, 575 FD_DOR_MOTEN0 = 0x10, 576 FD_DOR_MOTEN1 = 0x20, 577 FD_DOR_MOTEN2 = 0x40, 578 FD_DOR_MOTEN3 = 0x80, 579 }; 580 581 enum { 582 #if MAX_FD == 4 583 FD_TDR_BOOTSEL = 0x0c, 584 #else 585 FD_TDR_BOOTSEL = 0x04, 586 #endif 587 }; 588 589 enum { 590 FD_DSR_DRATEMASK= 0x03, 591 FD_DSR_PWRDOWN = 0x40, 592 FD_DSR_SWRESET = 0x80, 593 }; 594 595 enum { 596 FD_MSR_DRV0BUSY = 0x01, 597 FD_MSR_DRV1BUSY = 0x02, 598 FD_MSR_DRV2BUSY = 0x04, 599 FD_MSR_DRV3BUSY = 0x08, 600 FD_MSR_CMDBUSY = 0x10, 601 FD_MSR_NONDMA = 0x20, 602 FD_MSR_DIO = 0x40, 603 FD_MSR_RQM = 0x80, 604 }; 605 606 enum { 607 FD_DIR_DSKCHG = 0x80, 608 }; 609 610 /* 611 * See chapter 5.0 "Controller phases" of the spec: 612 * 613 * Command phase: 614 * The host writes a command and its parameters into the FIFO. The command 615 * phase is completed when all parameters for the command have been supplied, 616 * and execution phase is entered. 617 * 618 * Execution phase: 619 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO 620 * contains the payload now, otherwise it's unused. When all bytes of the 621 * required data have been transferred, the state is switched to either result 622 * phase (if the command produces status bytes) or directly back into the 623 * command phase for the next command. 624 * 625 * Result phase: 626 * The host reads out the FIFO, which contains one or more result bytes now. 627 */ 628 enum { 629 /* Only for migration: reconstruct phase from registers like qemu 2.3 */ 630 FD_PHASE_RECONSTRUCT = 0, 631 632 FD_PHASE_COMMAND = 1, 633 FD_PHASE_EXECUTION = 2, 634 FD_PHASE_RESULT = 3, 635 }; 636 637 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) 638 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) 639 640 struct FDCtrl { 641 MemoryRegion iomem; 642 qemu_irq irq; 643 /* Controller state */ 644 QEMUTimer *result_timer; 645 int dma_chann; 646 uint8_t phase; 647 IsaDma *dma; 648 /* Controller's identification */ 649 uint8_t version; 650 /* HW */ 651 uint8_t sra; 652 uint8_t srb; 653 uint8_t dor; 654 uint8_t dor_vmstate; /* only used as temp during vmstate */ 655 uint8_t tdr; 656 uint8_t dsr; 657 uint8_t msr; 658 uint8_t cur_drv; 659 uint8_t status0; 660 uint8_t status1; 661 uint8_t status2; 662 /* Command FIFO */ 663 uint8_t *fifo; 664 int32_t fifo_size; 665 uint32_t data_pos; 666 uint32_t data_len; 667 uint8_t data_state; 668 uint8_t data_dir; 669 uint8_t eot; /* last wanted sector */ 670 /* States kept only to be returned back */ 671 /* precompensation */ 672 uint8_t precomp_trk; 673 uint8_t config; 674 uint8_t lock; 675 /* Power down config (also with status regB access mode */ 676 uint8_t pwrd; 677 /* Floppy drives */ 678 uint8_t num_floppies; 679 FDrive drives[MAX_FD]; 680 int reset_sensei; 681 uint32_t check_media_rate; 682 FloppyDriveType fallback; /* type=auto failure fallback */ 683 /* Timers state */ 684 uint8_t timer0; 685 uint8_t timer1; 686 }; 687 688 static FloppyDriveType get_fallback_drive_type(FDrive *drv) 689 { 690 return drv->fdctrl->fallback; 691 } 692 693 #define TYPE_SYSBUS_FDC "base-sysbus-fdc" 694 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC) 695 696 typedef struct FDCtrlSysBus { 697 /*< private >*/ 698 SysBusDevice parent_obj; 699 /*< public >*/ 700 701 struct FDCtrl state; 702 } FDCtrlSysBus; 703 704 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC) 705 706 typedef struct FDCtrlISABus { 707 ISADevice parent_obj; 708 709 uint32_t iobase; 710 uint32_t irq; 711 uint32_t dma; 712 struct FDCtrl state; 713 int32_t bootindexA; 714 int32_t bootindexB; 715 } FDCtrlISABus; 716 717 static uint32_t fdctrl_read (void *opaque, uint32_t reg) 718 { 719 FDCtrl *fdctrl = opaque; 720 uint32_t retval; 721 722 reg &= 7; 723 switch (reg) { 724 case FD_REG_SRA: 725 retval = fdctrl_read_statusA(fdctrl); 726 break; 727 case FD_REG_SRB: 728 retval = fdctrl_read_statusB(fdctrl); 729 break; 730 case FD_REG_DOR: 731 retval = fdctrl_read_dor(fdctrl); 732 break; 733 case FD_REG_TDR: 734 retval = fdctrl_read_tape(fdctrl); 735 break; 736 case FD_REG_MSR: 737 retval = fdctrl_read_main_status(fdctrl); 738 break; 739 case FD_REG_FIFO: 740 retval = fdctrl_read_data(fdctrl); 741 break; 742 case FD_REG_DIR: 743 retval = fdctrl_read_dir(fdctrl); 744 break; 745 default: 746 retval = (uint32_t)(-1); 747 break; 748 } 749 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); 750 751 return retval; 752 } 753 754 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) 755 { 756 FDCtrl *fdctrl = opaque; 757 758 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); 759 760 reg &= 7; 761 switch (reg) { 762 case FD_REG_DOR: 763 fdctrl_write_dor(fdctrl, value); 764 break; 765 case FD_REG_TDR: 766 fdctrl_write_tape(fdctrl, value); 767 break; 768 case FD_REG_DSR: 769 fdctrl_write_rate(fdctrl, value); 770 break; 771 case FD_REG_FIFO: 772 fdctrl_write_data(fdctrl, value); 773 break; 774 case FD_REG_CCR: 775 fdctrl_write_ccr(fdctrl, value); 776 break; 777 default: 778 break; 779 } 780 } 781 782 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg, 783 unsigned ize) 784 { 785 return fdctrl_read(opaque, (uint32_t)reg); 786 } 787 788 static void fdctrl_write_mem (void *opaque, hwaddr reg, 789 uint64_t value, unsigned size) 790 { 791 fdctrl_write(opaque, (uint32_t)reg, value); 792 } 793 794 static const MemoryRegionOps fdctrl_mem_ops = { 795 .read = fdctrl_read_mem, 796 .write = fdctrl_write_mem, 797 .endianness = DEVICE_NATIVE_ENDIAN, 798 }; 799 800 static const MemoryRegionOps fdctrl_mem_strict_ops = { 801 .read = fdctrl_read_mem, 802 .write = fdctrl_write_mem, 803 .endianness = DEVICE_NATIVE_ENDIAN, 804 .valid = { 805 .min_access_size = 1, 806 .max_access_size = 1, 807 }, 808 }; 809 810 static bool fdrive_media_changed_needed(void *opaque) 811 { 812 FDrive *drive = opaque; 813 814 return (drive->blk != NULL && drive->media_changed != 1); 815 } 816 817 static const VMStateDescription vmstate_fdrive_media_changed = { 818 .name = "fdrive/media_changed", 819 .version_id = 1, 820 .minimum_version_id = 1, 821 .needed = fdrive_media_changed_needed, 822 .fields = (VMStateField[]) { 823 VMSTATE_UINT8(media_changed, FDrive), 824 VMSTATE_END_OF_LIST() 825 } 826 }; 827 828 static bool fdrive_media_rate_needed(void *opaque) 829 { 830 FDrive *drive = opaque; 831 832 return drive->fdctrl->check_media_rate; 833 } 834 835 static const VMStateDescription vmstate_fdrive_media_rate = { 836 .name = "fdrive/media_rate", 837 .version_id = 1, 838 .minimum_version_id = 1, 839 .needed = fdrive_media_rate_needed, 840 .fields = (VMStateField[]) { 841 VMSTATE_UINT8(media_rate, FDrive), 842 VMSTATE_END_OF_LIST() 843 } 844 }; 845 846 static bool fdrive_perpendicular_needed(void *opaque) 847 { 848 FDrive *drive = opaque; 849 850 return drive->perpendicular != 0; 851 } 852 853 static const VMStateDescription vmstate_fdrive_perpendicular = { 854 .name = "fdrive/perpendicular", 855 .version_id = 1, 856 .minimum_version_id = 1, 857 .needed = fdrive_perpendicular_needed, 858 .fields = (VMStateField[]) { 859 VMSTATE_UINT8(perpendicular, FDrive), 860 VMSTATE_END_OF_LIST() 861 } 862 }; 863 864 static int fdrive_post_load(void *opaque, int version_id) 865 { 866 fd_revalidate(opaque); 867 return 0; 868 } 869 870 static const VMStateDescription vmstate_fdrive = { 871 .name = "fdrive", 872 .version_id = 1, 873 .minimum_version_id = 1, 874 .post_load = fdrive_post_load, 875 .fields = (VMStateField[]) { 876 VMSTATE_UINT8(head, FDrive), 877 VMSTATE_UINT8(track, FDrive), 878 VMSTATE_UINT8(sect, FDrive), 879 VMSTATE_END_OF_LIST() 880 }, 881 .subsections = (const VMStateDescription*[]) { 882 &vmstate_fdrive_media_changed, 883 &vmstate_fdrive_media_rate, 884 &vmstate_fdrive_perpendicular, 885 NULL 886 } 887 }; 888 889 /* 890 * Reconstructs the phase from register values according to the logic that was 891 * implemented in qemu 2.3. This is the default value that is used if the phase 892 * subsection is not present on migration. 893 * 894 * Don't change this function to reflect newer qemu versions, it is part of 895 * the migration ABI. 896 */ 897 static int reconstruct_phase(FDCtrl *fdctrl) 898 { 899 if (fdctrl->msr & FD_MSR_NONDMA) { 900 return FD_PHASE_EXECUTION; 901 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) { 902 /* qemu 2.3 disabled RQM only during DMA transfers */ 903 return FD_PHASE_EXECUTION; 904 } else if (fdctrl->msr & FD_MSR_DIO) { 905 return FD_PHASE_RESULT; 906 } else { 907 return FD_PHASE_COMMAND; 908 } 909 } 910 911 static void fdc_pre_save(void *opaque) 912 { 913 FDCtrl *s = opaque; 914 915 s->dor_vmstate = s->dor | GET_CUR_DRV(s); 916 } 917 918 static int fdc_pre_load(void *opaque) 919 { 920 FDCtrl *s = opaque; 921 s->phase = FD_PHASE_RECONSTRUCT; 922 return 0; 923 } 924 925 static int fdc_post_load(void *opaque, int version_id) 926 { 927 FDCtrl *s = opaque; 928 929 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); 930 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; 931 932 if (s->phase == FD_PHASE_RECONSTRUCT) { 933 s->phase = reconstruct_phase(s); 934 } 935 936 return 0; 937 } 938 939 static bool fdc_reset_sensei_needed(void *opaque) 940 { 941 FDCtrl *s = opaque; 942 943 return s->reset_sensei != 0; 944 } 945 946 static const VMStateDescription vmstate_fdc_reset_sensei = { 947 .name = "fdc/reset_sensei", 948 .version_id = 1, 949 .minimum_version_id = 1, 950 .needed = fdc_reset_sensei_needed, 951 .fields = (VMStateField[]) { 952 VMSTATE_INT32(reset_sensei, FDCtrl), 953 VMSTATE_END_OF_LIST() 954 } 955 }; 956 957 static bool fdc_result_timer_needed(void *opaque) 958 { 959 FDCtrl *s = opaque; 960 961 return timer_pending(s->result_timer); 962 } 963 964 static const VMStateDescription vmstate_fdc_result_timer = { 965 .name = "fdc/result_timer", 966 .version_id = 1, 967 .minimum_version_id = 1, 968 .needed = fdc_result_timer_needed, 969 .fields = (VMStateField[]) { 970 VMSTATE_TIMER_PTR(result_timer, FDCtrl), 971 VMSTATE_END_OF_LIST() 972 } 973 }; 974 975 static bool fdc_phase_needed(void *opaque) 976 { 977 FDCtrl *fdctrl = opaque; 978 979 return reconstruct_phase(fdctrl) != fdctrl->phase; 980 } 981 982 static const VMStateDescription vmstate_fdc_phase = { 983 .name = "fdc/phase", 984 .version_id = 1, 985 .minimum_version_id = 1, 986 .needed = fdc_phase_needed, 987 .fields = (VMStateField[]) { 988 VMSTATE_UINT8(phase, FDCtrl), 989 VMSTATE_END_OF_LIST() 990 } 991 }; 992 993 static const VMStateDescription vmstate_fdc = { 994 .name = "fdc", 995 .version_id = 2, 996 .minimum_version_id = 2, 997 .pre_save = fdc_pre_save, 998 .pre_load = fdc_pre_load, 999 .post_load = fdc_post_load, 1000 .fields = (VMStateField[]) { 1001 /* Controller State */ 1002 VMSTATE_UINT8(sra, FDCtrl), 1003 VMSTATE_UINT8(srb, FDCtrl), 1004 VMSTATE_UINT8(dor_vmstate, FDCtrl), 1005 VMSTATE_UINT8(tdr, FDCtrl), 1006 VMSTATE_UINT8(dsr, FDCtrl), 1007 VMSTATE_UINT8(msr, FDCtrl), 1008 VMSTATE_UINT8(status0, FDCtrl), 1009 VMSTATE_UINT8(status1, FDCtrl), 1010 VMSTATE_UINT8(status2, FDCtrl), 1011 /* Command FIFO */ 1012 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, 1013 uint8_t), 1014 VMSTATE_UINT32(data_pos, FDCtrl), 1015 VMSTATE_UINT32(data_len, FDCtrl), 1016 VMSTATE_UINT8(data_state, FDCtrl), 1017 VMSTATE_UINT8(data_dir, FDCtrl), 1018 VMSTATE_UINT8(eot, FDCtrl), 1019 /* States kept only to be returned back */ 1020 VMSTATE_UINT8(timer0, FDCtrl), 1021 VMSTATE_UINT8(timer1, FDCtrl), 1022 VMSTATE_UINT8(precomp_trk, FDCtrl), 1023 VMSTATE_UINT8(config, FDCtrl), 1024 VMSTATE_UINT8(lock, FDCtrl), 1025 VMSTATE_UINT8(pwrd, FDCtrl), 1026 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl), 1027 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, 1028 vmstate_fdrive, FDrive), 1029 VMSTATE_END_OF_LIST() 1030 }, 1031 .subsections = (const VMStateDescription*[]) { 1032 &vmstate_fdc_reset_sensei, 1033 &vmstate_fdc_result_timer, 1034 &vmstate_fdc_phase, 1035 NULL 1036 } 1037 }; 1038 1039 static void fdctrl_external_reset_sysbus(DeviceState *d) 1040 { 1041 FDCtrlSysBus *sys = SYSBUS_FDC(d); 1042 FDCtrl *s = &sys->state; 1043 1044 fdctrl_reset(s, 0); 1045 } 1046 1047 static void fdctrl_external_reset_isa(DeviceState *d) 1048 { 1049 FDCtrlISABus *isa = ISA_FDC(d); 1050 FDCtrl *s = &isa->state; 1051 1052 fdctrl_reset(s, 0); 1053 } 1054 1055 static void fdctrl_handle_tc(void *opaque, int irq, int level) 1056 { 1057 //FDCtrl *s = opaque; 1058 1059 if (level) { 1060 // XXX 1061 FLOPPY_DPRINTF("TC pulsed\n"); 1062 } 1063 } 1064 1065 /* Change IRQ state */ 1066 static void fdctrl_reset_irq(FDCtrl *fdctrl) 1067 { 1068 fdctrl->status0 = 0; 1069 if (!(fdctrl->sra & FD_SRA_INTPEND)) 1070 return; 1071 FLOPPY_DPRINTF("Reset interrupt\n"); 1072 qemu_set_irq(fdctrl->irq, 0); 1073 fdctrl->sra &= ~FD_SRA_INTPEND; 1074 } 1075 1076 static void fdctrl_raise_irq(FDCtrl *fdctrl) 1077 { 1078 if (!(fdctrl->sra & FD_SRA_INTPEND)) { 1079 qemu_set_irq(fdctrl->irq, 1); 1080 fdctrl->sra |= FD_SRA_INTPEND; 1081 } 1082 1083 fdctrl->reset_sensei = 0; 1084 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); 1085 } 1086 1087 /* Reset controller */ 1088 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) 1089 { 1090 int i; 1091 1092 FLOPPY_DPRINTF("reset controller\n"); 1093 fdctrl_reset_irq(fdctrl); 1094 /* Initialise controller */ 1095 fdctrl->sra = 0; 1096 fdctrl->srb = 0xc0; 1097 if (!fdctrl->drives[1].blk) { 1098 fdctrl->sra |= FD_SRA_nDRV2; 1099 } 1100 fdctrl->cur_drv = 0; 1101 fdctrl->dor = FD_DOR_nRESET; 1102 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; 1103 fdctrl->msr = FD_MSR_RQM; 1104 fdctrl->reset_sensei = 0; 1105 timer_del(fdctrl->result_timer); 1106 /* FIFO state */ 1107 fdctrl->data_pos = 0; 1108 fdctrl->data_len = 0; 1109 fdctrl->data_state = 0; 1110 fdctrl->data_dir = FD_DIR_WRITE; 1111 for (i = 0; i < MAX_FD; i++) 1112 fd_recalibrate(&fdctrl->drives[i]); 1113 fdctrl_to_command_phase(fdctrl); 1114 if (do_irq) { 1115 fdctrl->status0 |= FD_SR0_RDYCHG; 1116 fdctrl_raise_irq(fdctrl); 1117 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; 1118 } 1119 } 1120 1121 static inline FDrive *drv0(FDCtrl *fdctrl) 1122 { 1123 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; 1124 } 1125 1126 static inline FDrive *drv1(FDCtrl *fdctrl) 1127 { 1128 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) 1129 return &fdctrl->drives[1]; 1130 else 1131 return &fdctrl->drives[0]; 1132 } 1133 1134 #if MAX_FD == 4 1135 static inline FDrive *drv2(FDCtrl *fdctrl) 1136 { 1137 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) 1138 return &fdctrl->drives[2]; 1139 else 1140 return &fdctrl->drives[1]; 1141 } 1142 1143 static inline FDrive *drv3(FDCtrl *fdctrl) 1144 { 1145 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) 1146 return &fdctrl->drives[3]; 1147 else 1148 return &fdctrl->drives[2]; 1149 } 1150 #endif 1151 1152 static FDrive *get_cur_drv(FDCtrl *fdctrl) 1153 { 1154 switch (fdctrl->cur_drv) { 1155 case 0: return drv0(fdctrl); 1156 case 1: return drv1(fdctrl); 1157 #if MAX_FD == 4 1158 case 2: return drv2(fdctrl); 1159 case 3: return drv3(fdctrl); 1160 #endif 1161 default: return NULL; 1162 } 1163 } 1164 1165 /* Status A register : 0x00 (read-only) */ 1166 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) 1167 { 1168 uint32_t retval = fdctrl->sra; 1169 1170 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); 1171 1172 return retval; 1173 } 1174 1175 /* Status B register : 0x01 (read-only) */ 1176 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) 1177 { 1178 uint32_t retval = fdctrl->srb; 1179 1180 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); 1181 1182 return retval; 1183 } 1184 1185 /* Digital output register : 0x02 */ 1186 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) 1187 { 1188 uint32_t retval = fdctrl->dor; 1189 1190 /* Selected drive */ 1191 retval |= fdctrl->cur_drv; 1192 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); 1193 1194 return retval; 1195 } 1196 1197 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) 1198 { 1199 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); 1200 1201 /* Motors */ 1202 if (value & FD_DOR_MOTEN0) 1203 fdctrl->srb |= FD_SRB_MTR0; 1204 else 1205 fdctrl->srb &= ~FD_SRB_MTR0; 1206 if (value & FD_DOR_MOTEN1) 1207 fdctrl->srb |= FD_SRB_MTR1; 1208 else 1209 fdctrl->srb &= ~FD_SRB_MTR1; 1210 1211 /* Drive */ 1212 if (value & 1) 1213 fdctrl->srb |= FD_SRB_DR0; 1214 else 1215 fdctrl->srb &= ~FD_SRB_DR0; 1216 1217 /* Reset */ 1218 if (!(value & FD_DOR_nRESET)) { 1219 if (fdctrl->dor & FD_DOR_nRESET) { 1220 FLOPPY_DPRINTF("controller enter RESET state\n"); 1221 } 1222 } else { 1223 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1224 FLOPPY_DPRINTF("controller out of RESET state\n"); 1225 fdctrl_reset(fdctrl, 1); 1226 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1227 } 1228 } 1229 /* Selected drive */ 1230 fdctrl->cur_drv = value & FD_DOR_SELMASK; 1231 1232 fdctrl->dor = value; 1233 } 1234 1235 /* Tape drive register : 0x03 */ 1236 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) 1237 { 1238 uint32_t retval = fdctrl->tdr; 1239 1240 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); 1241 1242 return retval; 1243 } 1244 1245 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) 1246 { 1247 /* Reset mode */ 1248 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1249 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1250 return; 1251 } 1252 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); 1253 /* Disk boot selection indicator */ 1254 fdctrl->tdr = value & FD_TDR_BOOTSEL; 1255 /* Tape indicators: never allow */ 1256 } 1257 1258 /* Main status register : 0x04 (read) */ 1259 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) 1260 { 1261 uint32_t retval = fdctrl->msr; 1262 1263 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1264 fdctrl->dor |= FD_DOR_nRESET; 1265 1266 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); 1267 1268 return retval; 1269 } 1270 1271 /* Data select rate register : 0x04 (write) */ 1272 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) 1273 { 1274 /* Reset mode */ 1275 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1276 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1277 return; 1278 } 1279 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); 1280 /* Reset: autoclear */ 1281 if (value & FD_DSR_SWRESET) { 1282 fdctrl->dor &= ~FD_DOR_nRESET; 1283 fdctrl_reset(fdctrl, 1); 1284 fdctrl->dor |= FD_DOR_nRESET; 1285 } 1286 if (value & FD_DSR_PWRDOWN) { 1287 fdctrl_reset(fdctrl, 1); 1288 } 1289 fdctrl->dsr = value; 1290 } 1291 1292 /* Configuration control register: 0x07 (write) */ 1293 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) 1294 { 1295 /* Reset mode */ 1296 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1297 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1298 return; 1299 } 1300 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); 1301 1302 /* Only the rate selection bits used in AT mode, and we 1303 * store those in the DSR. 1304 */ 1305 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | 1306 (value & FD_DSR_DRATEMASK); 1307 } 1308 1309 static int fdctrl_media_changed(FDrive *drv) 1310 { 1311 return drv->media_changed; 1312 } 1313 1314 /* Digital input register : 0x07 (read-only) */ 1315 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) 1316 { 1317 uint32_t retval = 0; 1318 1319 if (fdctrl_media_changed(get_cur_drv(fdctrl))) { 1320 retval |= FD_DIR_DSKCHG; 1321 } 1322 if (retval != 0) { 1323 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); 1324 } 1325 1326 return retval; 1327 } 1328 1329 /* Clear the FIFO and update the state for receiving the next command */ 1330 static void fdctrl_to_command_phase(FDCtrl *fdctrl) 1331 { 1332 fdctrl->phase = FD_PHASE_COMMAND; 1333 fdctrl->data_dir = FD_DIR_WRITE; 1334 fdctrl->data_pos = 0; 1335 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */ 1336 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); 1337 fdctrl->msr |= FD_MSR_RQM; 1338 } 1339 1340 /* Update the state to allow the guest to read out the command status. 1341 * @fifo_len is the number of result bytes to be read out. */ 1342 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len) 1343 { 1344 fdctrl->phase = FD_PHASE_RESULT; 1345 fdctrl->data_dir = FD_DIR_READ; 1346 fdctrl->data_len = fifo_len; 1347 fdctrl->data_pos = 0; 1348 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; 1349 } 1350 1351 /* Set an error: unimplemented/unknown command */ 1352 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) 1353 { 1354 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n", 1355 fdctrl->fifo[0]); 1356 fdctrl->fifo[0] = FD_SR0_INVCMD; 1357 fdctrl_to_result_phase(fdctrl, 1); 1358 } 1359 1360 /* Seek to next sector 1361 * returns 0 when end of track reached (for DBL_SIDES on head 1) 1362 * otherwise returns 1 1363 */ 1364 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) 1365 { 1366 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", 1367 cur_drv->head, cur_drv->track, cur_drv->sect, 1368 fd_sector(cur_drv)); 1369 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an 1370 error in fact */ 1371 uint8_t new_head = cur_drv->head; 1372 uint8_t new_track = cur_drv->track; 1373 uint8_t new_sect = cur_drv->sect; 1374 1375 int ret = 1; 1376 1377 if (new_sect >= cur_drv->last_sect || 1378 new_sect == fdctrl->eot) { 1379 new_sect = 1; 1380 if (FD_MULTI_TRACK(fdctrl->data_state)) { 1381 if (new_head == 0 && 1382 (cur_drv->flags & FDISK_DBL_SIDES) != 0) { 1383 new_head = 1; 1384 } else { 1385 new_head = 0; 1386 new_track++; 1387 fdctrl->status0 |= FD_SR0_SEEK; 1388 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) { 1389 ret = 0; 1390 } 1391 } 1392 } else { 1393 fdctrl->status0 |= FD_SR0_SEEK; 1394 new_track++; 1395 ret = 0; 1396 } 1397 if (ret == 1) { 1398 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", 1399 new_head, new_track, new_sect, fd_sector(cur_drv)); 1400 } 1401 } else { 1402 new_sect++; 1403 } 1404 fd_seek(cur_drv, new_head, new_track, new_sect, 1); 1405 return ret; 1406 } 1407 1408 /* Callback for transfer end (stop or abort) */ 1409 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, 1410 uint8_t status1, uint8_t status2) 1411 { 1412 FDrive *cur_drv; 1413 cur_drv = get_cur_drv(fdctrl); 1414 1415 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD); 1416 fdctrl->status0 |= GET_CUR_DRV(fdctrl); 1417 if (cur_drv->head) { 1418 fdctrl->status0 |= FD_SR0_HEAD; 1419 } 1420 fdctrl->status0 |= status0; 1421 1422 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", 1423 status0, status1, status2, fdctrl->status0); 1424 fdctrl->fifo[0] = fdctrl->status0; 1425 fdctrl->fifo[1] = status1; 1426 fdctrl->fifo[2] = status2; 1427 fdctrl->fifo[3] = cur_drv->track; 1428 fdctrl->fifo[4] = cur_drv->head; 1429 fdctrl->fifo[5] = cur_drv->sect; 1430 fdctrl->fifo[6] = FD_SECTOR_SC; 1431 fdctrl->data_dir = FD_DIR_READ; 1432 if (!(fdctrl->msr & FD_MSR_NONDMA)) { 1433 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma); 1434 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann); 1435 } 1436 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 1437 fdctrl->msr &= ~FD_MSR_NONDMA; 1438 1439 fdctrl_to_result_phase(fdctrl, 7); 1440 fdctrl_raise_irq(fdctrl); 1441 } 1442 1443 /* Prepare a data transfer (either DMA or FIFO) */ 1444 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) 1445 { 1446 FDrive *cur_drv; 1447 uint8_t kh, kt, ks; 1448 1449 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1450 cur_drv = get_cur_drv(fdctrl); 1451 kt = fdctrl->fifo[2]; 1452 kh = fdctrl->fifo[3]; 1453 ks = fdctrl->fifo[4]; 1454 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", 1455 GET_CUR_DRV(fdctrl), kh, kt, ks, 1456 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1457 NUM_SIDES(cur_drv))); 1458 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1459 case 2: 1460 /* sect too big */ 1461 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1462 fdctrl->fifo[3] = kt; 1463 fdctrl->fifo[4] = kh; 1464 fdctrl->fifo[5] = ks; 1465 return; 1466 case 3: 1467 /* track too big */ 1468 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1469 fdctrl->fifo[3] = kt; 1470 fdctrl->fifo[4] = kh; 1471 fdctrl->fifo[5] = ks; 1472 return; 1473 case 4: 1474 /* No seek enabled */ 1475 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1476 fdctrl->fifo[3] = kt; 1477 fdctrl->fifo[4] = kh; 1478 fdctrl->fifo[5] = ks; 1479 return; 1480 case 1: 1481 fdctrl->status0 |= FD_SR0_SEEK; 1482 break; 1483 default: 1484 break; 1485 } 1486 1487 /* Check the data rate. If the programmed data rate does not match 1488 * the currently inserted medium, the operation has to fail. */ 1489 if (fdctrl->check_media_rate && 1490 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 1491 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n", 1492 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 1493 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 1494 fdctrl->fifo[3] = kt; 1495 fdctrl->fifo[4] = kh; 1496 fdctrl->fifo[5] = ks; 1497 return; 1498 } 1499 1500 /* Set the FIFO state */ 1501 fdctrl->data_dir = direction; 1502 fdctrl->data_pos = 0; 1503 assert(fdctrl->msr & FD_MSR_CMDBUSY); 1504 if (fdctrl->fifo[0] & 0x80) 1505 fdctrl->data_state |= FD_STATE_MULTI; 1506 else 1507 fdctrl->data_state &= ~FD_STATE_MULTI; 1508 if (fdctrl->fifo[5] == 0) { 1509 fdctrl->data_len = fdctrl->fifo[8]; 1510 } else { 1511 int tmp; 1512 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); 1513 tmp = (fdctrl->fifo[6] - ks + 1); 1514 if (fdctrl->fifo[0] & 0x80) 1515 tmp += fdctrl->fifo[6]; 1516 fdctrl->data_len *= tmp; 1517 } 1518 fdctrl->eot = fdctrl->fifo[6]; 1519 if (fdctrl->dor & FD_DOR_DMAEN) { 1520 IsaDmaTransferMode dma_mode; 1521 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma); 1522 bool dma_mode_ok; 1523 /* DMA transfer are enabled. Check if DMA channel is well programmed */ 1524 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann); 1525 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", 1526 dma_mode, direction, 1527 (128 << fdctrl->fifo[5]) * 1528 (cur_drv->last_sect - ks + 1), fdctrl->data_len); 1529 switch (direction) { 1530 case FD_DIR_SCANE: 1531 case FD_DIR_SCANL: 1532 case FD_DIR_SCANH: 1533 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY); 1534 break; 1535 case FD_DIR_WRITE: 1536 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE); 1537 break; 1538 case FD_DIR_READ: 1539 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ); 1540 break; 1541 case FD_DIR_VERIFY: 1542 dma_mode_ok = true; 1543 break; 1544 default: 1545 dma_mode_ok = false; 1546 break; 1547 } 1548 if (dma_mode_ok) { 1549 /* No access is allowed until DMA transfer has completed */ 1550 fdctrl->msr &= ~FD_MSR_RQM; 1551 if (direction != FD_DIR_VERIFY) { 1552 /* Now, we just have to wait for the DMA controller to 1553 * recall us... 1554 */ 1555 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann); 1556 k->schedule(fdctrl->dma); 1557 } else { 1558 /* Start transfer */ 1559 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, 1560 fdctrl->data_len); 1561 } 1562 return; 1563 } else { 1564 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode, 1565 direction); 1566 } 1567 } 1568 FLOPPY_DPRINTF("start non-DMA transfer\n"); 1569 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM; 1570 if (direction != FD_DIR_WRITE) 1571 fdctrl->msr |= FD_MSR_DIO; 1572 /* IO based transfer: calculate len */ 1573 fdctrl_raise_irq(fdctrl); 1574 } 1575 1576 /* Prepare a transfer of deleted data */ 1577 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) 1578 { 1579 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n"); 1580 1581 /* We don't handle deleted data, 1582 * so we don't return *ANYTHING* 1583 */ 1584 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1585 } 1586 1587 /* handlers for DMA transfers */ 1588 static int fdctrl_transfer_handler (void *opaque, int nchan, 1589 int dma_pos, int dma_len) 1590 { 1591 FDCtrl *fdctrl; 1592 FDrive *cur_drv; 1593 int len, start_pos, rel_pos; 1594 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; 1595 IsaDmaClass *k; 1596 1597 fdctrl = opaque; 1598 if (fdctrl->msr & FD_MSR_RQM) { 1599 FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); 1600 return 0; 1601 } 1602 k = ISADMA_GET_CLASS(fdctrl->dma); 1603 cur_drv = get_cur_drv(fdctrl); 1604 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || 1605 fdctrl->data_dir == FD_DIR_SCANH) 1606 status2 = FD_SR2_SNS; 1607 if (dma_len > fdctrl->data_len) 1608 dma_len = fdctrl->data_len; 1609 if (cur_drv->blk == NULL) { 1610 if (fdctrl->data_dir == FD_DIR_WRITE) 1611 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1612 else 1613 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1614 len = 0; 1615 goto transfer_error; 1616 } 1617 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1618 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { 1619 len = dma_len - fdctrl->data_pos; 1620 if (len + rel_pos > FD_SECTOR_LEN) 1621 len = FD_SECTOR_LEN - rel_pos; 1622 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " 1623 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, 1624 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, 1625 cur_drv->track, cur_drv->sect, fd_sector(cur_drv), 1626 fd_sector(cur_drv) * FD_SECTOR_LEN); 1627 if (fdctrl->data_dir != FD_DIR_WRITE || 1628 len < FD_SECTOR_LEN || rel_pos != 0) { 1629 /* READ & SCAN commands and realign to a sector for WRITE */ 1630 if (blk_read(cur_drv->blk, fd_sector(cur_drv), 1631 fdctrl->fifo, 1) < 0) { 1632 FLOPPY_DPRINTF("Floppy: error getting sector %d\n", 1633 fd_sector(cur_drv)); 1634 /* Sure, image size is too small... */ 1635 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1636 } 1637 } 1638 switch (fdctrl->data_dir) { 1639 case FD_DIR_READ: 1640 /* READ commands */ 1641 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos, 1642 fdctrl->data_pos, len); 1643 break; 1644 case FD_DIR_WRITE: 1645 /* WRITE commands */ 1646 if (cur_drv->ro) { 1647 /* Handle readonly medium early, no need to do DMA, touch the 1648 * LED or attempt any writes. A real floppy doesn't attempt 1649 * to write to readonly media either. */ 1650 fdctrl_stop_transfer(fdctrl, 1651 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, 1652 0x00); 1653 goto transfer_error; 1654 } 1655 1656 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos, 1657 fdctrl->data_pos, len); 1658 if (blk_write(cur_drv->blk, fd_sector(cur_drv), 1659 fdctrl->fifo, 1) < 0) { 1660 FLOPPY_DPRINTF("error writing sector %d\n", 1661 fd_sector(cur_drv)); 1662 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1663 goto transfer_error; 1664 } 1665 break; 1666 case FD_DIR_VERIFY: 1667 /* VERIFY commands */ 1668 break; 1669 default: 1670 /* SCAN commands */ 1671 { 1672 uint8_t tmpbuf[FD_SECTOR_LEN]; 1673 int ret; 1674 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos, 1675 len); 1676 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); 1677 if (ret == 0) { 1678 status2 = FD_SR2_SEH; 1679 goto end_transfer; 1680 } 1681 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || 1682 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { 1683 status2 = 0x00; 1684 goto end_transfer; 1685 } 1686 } 1687 break; 1688 } 1689 fdctrl->data_pos += len; 1690 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1691 if (rel_pos == 0) { 1692 /* Seek to next sector */ 1693 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) 1694 break; 1695 } 1696 } 1697 end_transfer: 1698 len = fdctrl->data_pos - start_pos; 1699 FLOPPY_DPRINTF("end transfer %d %d %d\n", 1700 fdctrl->data_pos, len, fdctrl->data_len); 1701 if (fdctrl->data_dir == FD_DIR_SCANE || 1702 fdctrl->data_dir == FD_DIR_SCANL || 1703 fdctrl->data_dir == FD_DIR_SCANH) 1704 status2 = FD_SR2_SEH; 1705 fdctrl->data_len -= len; 1706 fdctrl_stop_transfer(fdctrl, status0, status1, status2); 1707 transfer_error: 1708 1709 return len; 1710 } 1711 1712 /* Data register : 0x05 */ 1713 static uint32_t fdctrl_read_data(FDCtrl *fdctrl) 1714 { 1715 FDrive *cur_drv; 1716 uint32_t retval = 0; 1717 uint32_t pos; 1718 1719 cur_drv = get_cur_drv(fdctrl); 1720 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1721 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { 1722 FLOPPY_DPRINTF("error: controller not ready for reading\n"); 1723 return 0; 1724 } 1725 1726 /* If data_len spans multiple sectors, the current position in the FIFO 1727 * wraps around while fdctrl->data_pos is the real position in the whole 1728 * request. */ 1729 pos = fdctrl->data_pos; 1730 pos %= FD_SECTOR_LEN; 1731 1732 switch (fdctrl->phase) { 1733 case FD_PHASE_EXECUTION: 1734 assert(fdctrl->msr & FD_MSR_NONDMA); 1735 if (pos == 0) { 1736 if (fdctrl->data_pos != 0) 1737 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1738 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1739 fd_sector(cur_drv)); 1740 return 0; 1741 } 1742 if (blk_read(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) 1743 < 0) { 1744 FLOPPY_DPRINTF("error getting sector %d\n", 1745 fd_sector(cur_drv)); 1746 /* Sure, image size is too small... */ 1747 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1748 } 1749 } 1750 1751 if (++fdctrl->data_pos == fdctrl->data_len) { 1752 fdctrl->msr &= ~FD_MSR_RQM; 1753 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1754 } 1755 break; 1756 1757 case FD_PHASE_RESULT: 1758 assert(!(fdctrl->msr & FD_MSR_NONDMA)); 1759 if (++fdctrl->data_pos == fdctrl->data_len) { 1760 fdctrl->msr &= ~FD_MSR_RQM; 1761 fdctrl_to_command_phase(fdctrl); 1762 fdctrl_reset_irq(fdctrl); 1763 } 1764 break; 1765 1766 case FD_PHASE_COMMAND: 1767 default: 1768 abort(); 1769 } 1770 1771 retval = fdctrl->fifo[pos]; 1772 FLOPPY_DPRINTF("data register: 0x%02x\n", retval); 1773 1774 return retval; 1775 } 1776 1777 static void fdctrl_format_sector(FDCtrl *fdctrl) 1778 { 1779 FDrive *cur_drv; 1780 uint8_t kh, kt, ks; 1781 1782 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1783 cur_drv = get_cur_drv(fdctrl); 1784 kt = fdctrl->fifo[6]; 1785 kh = fdctrl->fifo[7]; 1786 ks = fdctrl->fifo[8]; 1787 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", 1788 GET_CUR_DRV(fdctrl), kh, kt, ks, 1789 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1790 NUM_SIDES(cur_drv))); 1791 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1792 case 2: 1793 /* sect too big */ 1794 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1795 fdctrl->fifo[3] = kt; 1796 fdctrl->fifo[4] = kh; 1797 fdctrl->fifo[5] = ks; 1798 return; 1799 case 3: 1800 /* track too big */ 1801 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1802 fdctrl->fifo[3] = kt; 1803 fdctrl->fifo[4] = kh; 1804 fdctrl->fifo[5] = ks; 1805 return; 1806 case 4: 1807 /* No seek enabled */ 1808 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1809 fdctrl->fifo[3] = kt; 1810 fdctrl->fifo[4] = kh; 1811 fdctrl->fifo[5] = ks; 1812 return; 1813 case 1: 1814 fdctrl->status0 |= FD_SR0_SEEK; 1815 break; 1816 default: 1817 break; 1818 } 1819 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1820 if (cur_drv->blk == NULL || 1821 blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1822 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv)); 1823 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1824 } else { 1825 if (cur_drv->sect == cur_drv->last_sect) { 1826 fdctrl->data_state &= ~FD_STATE_FORMAT; 1827 /* Last sector done */ 1828 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1829 } else { 1830 /* More to do */ 1831 fdctrl->data_pos = 0; 1832 fdctrl->data_len = 4; 1833 } 1834 } 1835 } 1836 1837 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) 1838 { 1839 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; 1840 fdctrl->fifo[0] = fdctrl->lock << 4; 1841 fdctrl_to_result_phase(fdctrl, 1); 1842 } 1843 1844 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) 1845 { 1846 FDrive *cur_drv = get_cur_drv(fdctrl); 1847 1848 /* Drives position */ 1849 fdctrl->fifo[0] = drv0(fdctrl)->track; 1850 fdctrl->fifo[1] = drv1(fdctrl)->track; 1851 #if MAX_FD == 4 1852 fdctrl->fifo[2] = drv2(fdctrl)->track; 1853 fdctrl->fifo[3] = drv3(fdctrl)->track; 1854 #else 1855 fdctrl->fifo[2] = 0; 1856 fdctrl->fifo[3] = 0; 1857 #endif 1858 /* timers */ 1859 fdctrl->fifo[4] = fdctrl->timer0; 1860 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); 1861 fdctrl->fifo[6] = cur_drv->last_sect; 1862 fdctrl->fifo[7] = (fdctrl->lock << 7) | 1863 (cur_drv->perpendicular << 2); 1864 fdctrl->fifo[8] = fdctrl->config; 1865 fdctrl->fifo[9] = fdctrl->precomp_trk; 1866 fdctrl_to_result_phase(fdctrl, 10); 1867 } 1868 1869 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) 1870 { 1871 /* Controller's version */ 1872 fdctrl->fifo[0] = fdctrl->version; 1873 fdctrl_to_result_phase(fdctrl, 1); 1874 } 1875 1876 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) 1877 { 1878 fdctrl->fifo[0] = 0x41; /* Stepping 1 */ 1879 fdctrl_to_result_phase(fdctrl, 1); 1880 } 1881 1882 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) 1883 { 1884 FDrive *cur_drv = get_cur_drv(fdctrl); 1885 1886 /* Drives position */ 1887 drv0(fdctrl)->track = fdctrl->fifo[3]; 1888 drv1(fdctrl)->track = fdctrl->fifo[4]; 1889 #if MAX_FD == 4 1890 drv2(fdctrl)->track = fdctrl->fifo[5]; 1891 drv3(fdctrl)->track = fdctrl->fifo[6]; 1892 #endif 1893 /* timers */ 1894 fdctrl->timer0 = fdctrl->fifo[7]; 1895 fdctrl->timer1 = fdctrl->fifo[8]; 1896 cur_drv->last_sect = fdctrl->fifo[9]; 1897 fdctrl->lock = fdctrl->fifo[10] >> 7; 1898 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; 1899 fdctrl->config = fdctrl->fifo[11]; 1900 fdctrl->precomp_trk = fdctrl->fifo[12]; 1901 fdctrl->pwrd = fdctrl->fifo[13]; 1902 fdctrl_to_command_phase(fdctrl); 1903 } 1904 1905 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) 1906 { 1907 FDrive *cur_drv = get_cur_drv(fdctrl); 1908 1909 fdctrl->fifo[0] = 0; 1910 fdctrl->fifo[1] = 0; 1911 /* Drives position */ 1912 fdctrl->fifo[2] = drv0(fdctrl)->track; 1913 fdctrl->fifo[3] = drv1(fdctrl)->track; 1914 #if MAX_FD == 4 1915 fdctrl->fifo[4] = drv2(fdctrl)->track; 1916 fdctrl->fifo[5] = drv3(fdctrl)->track; 1917 #else 1918 fdctrl->fifo[4] = 0; 1919 fdctrl->fifo[5] = 0; 1920 #endif 1921 /* timers */ 1922 fdctrl->fifo[6] = fdctrl->timer0; 1923 fdctrl->fifo[7] = fdctrl->timer1; 1924 fdctrl->fifo[8] = cur_drv->last_sect; 1925 fdctrl->fifo[9] = (fdctrl->lock << 7) | 1926 (cur_drv->perpendicular << 2); 1927 fdctrl->fifo[10] = fdctrl->config; 1928 fdctrl->fifo[11] = fdctrl->precomp_trk; 1929 fdctrl->fifo[12] = fdctrl->pwrd; 1930 fdctrl->fifo[13] = 0; 1931 fdctrl->fifo[14] = 0; 1932 fdctrl_to_result_phase(fdctrl, 15); 1933 } 1934 1935 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) 1936 { 1937 FDrive *cur_drv = get_cur_drv(fdctrl); 1938 1939 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1940 timer_mod(fdctrl->result_timer, 1941 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50)); 1942 } 1943 1944 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) 1945 { 1946 FDrive *cur_drv; 1947 1948 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1949 cur_drv = get_cur_drv(fdctrl); 1950 fdctrl->data_state |= FD_STATE_FORMAT; 1951 if (fdctrl->fifo[0] & 0x80) 1952 fdctrl->data_state |= FD_STATE_MULTI; 1953 else 1954 fdctrl->data_state &= ~FD_STATE_MULTI; 1955 cur_drv->bps = 1956 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; 1957 #if 0 1958 cur_drv->last_sect = 1959 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : 1960 fdctrl->fifo[3] / 2; 1961 #else 1962 cur_drv->last_sect = fdctrl->fifo[3]; 1963 #endif 1964 /* TODO: implement format using DMA expected by the Bochs BIOS 1965 * and Linux fdformat (read 3 bytes per sector via DMA and fill 1966 * the sector with the specified fill byte 1967 */ 1968 fdctrl->data_state &= ~FD_STATE_FORMAT; 1969 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1970 } 1971 1972 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) 1973 { 1974 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; 1975 fdctrl->timer1 = fdctrl->fifo[2] >> 1; 1976 if (fdctrl->fifo[2] & 1) 1977 fdctrl->dor &= ~FD_DOR_DMAEN; 1978 else 1979 fdctrl->dor |= FD_DOR_DMAEN; 1980 /* No result back */ 1981 fdctrl_to_command_phase(fdctrl); 1982 } 1983 1984 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) 1985 { 1986 FDrive *cur_drv; 1987 1988 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1989 cur_drv = get_cur_drv(fdctrl); 1990 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1991 /* 1 Byte status back */ 1992 fdctrl->fifo[0] = (cur_drv->ro << 6) | 1993 (cur_drv->track == 0 ? 0x10 : 0x00) | 1994 (cur_drv->head << 2) | 1995 GET_CUR_DRV(fdctrl) | 1996 0x28; 1997 fdctrl_to_result_phase(fdctrl, 1); 1998 } 1999 2000 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) 2001 { 2002 FDrive *cur_drv; 2003 2004 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2005 cur_drv = get_cur_drv(fdctrl); 2006 fd_recalibrate(cur_drv); 2007 fdctrl_to_command_phase(fdctrl); 2008 /* Raise Interrupt */ 2009 fdctrl->status0 |= FD_SR0_SEEK; 2010 fdctrl_raise_irq(fdctrl); 2011 } 2012 2013 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) 2014 { 2015 FDrive *cur_drv = get_cur_drv(fdctrl); 2016 2017 if (fdctrl->reset_sensei > 0) { 2018 fdctrl->fifo[0] = 2019 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; 2020 fdctrl->reset_sensei--; 2021 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) { 2022 fdctrl->fifo[0] = FD_SR0_INVCMD; 2023 fdctrl_to_result_phase(fdctrl, 1); 2024 return; 2025 } else { 2026 fdctrl->fifo[0] = 2027 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0)) 2028 | GET_CUR_DRV(fdctrl); 2029 } 2030 2031 fdctrl->fifo[1] = cur_drv->track; 2032 fdctrl_to_result_phase(fdctrl, 2); 2033 fdctrl_reset_irq(fdctrl); 2034 fdctrl->status0 = FD_SR0_RDYCHG; 2035 } 2036 2037 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) 2038 { 2039 FDrive *cur_drv; 2040 2041 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2042 cur_drv = get_cur_drv(fdctrl); 2043 fdctrl_to_command_phase(fdctrl); 2044 /* The seek command just sends step pulses to the drive and doesn't care if 2045 * there is a medium inserted of if it's banging the head against the drive. 2046 */ 2047 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1); 2048 /* Raise Interrupt */ 2049 fdctrl->status0 |= FD_SR0_SEEK; 2050 fdctrl_raise_irq(fdctrl); 2051 } 2052 2053 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) 2054 { 2055 FDrive *cur_drv = get_cur_drv(fdctrl); 2056 2057 if (fdctrl->fifo[1] & 0x80) 2058 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; 2059 /* No result back */ 2060 fdctrl_to_command_phase(fdctrl); 2061 } 2062 2063 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) 2064 { 2065 fdctrl->config = fdctrl->fifo[2]; 2066 fdctrl->precomp_trk = fdctrl->fifo[3]; 2067 /* No result back */ 2068 fdctrl_to_command_phase(fdctrl); 2069 } 2070 2071 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) 2072 { 2073 fdctrl->pwrd = fdctrl->fifo[1]; 2074 fdctrl->fifo[0] = fdctrl->fifo[1]; 2075 fdctrl_to_result_phase(fdctrl, 1); 2076 } 2077 2078 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) 2079 { 2080 /* No result back */ 2081 fdctrl_to_command_phase(fdctrl); 2082 } 2083 2084 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) 2085 { 2086 FDrive *cur_drv = get_cur_drv(fdctrl); 2087 uint32_t pos; 2088 2089 pos = fdctrl->data_pos - 1; 2090 pos %= FD_SECTOR_LEN; 2091 if (fdctrl->fifo[pos] & 0x80) { 2092 /* Command parameters done */ 2093 if (fdctrl->fifo[pos] & 0x40) { 2094 fdctrl->fifo[0] = fdctrl->fifo[1]; 2095 fdctrl->fifo[2] = 0; 2096 fdctrl->fifo[3] = 0; 2097 fdctrl_to_result_phase(fdctrl, 4); 2098 } else { 2099 fdctrl_to_command_phase(fdctrl); 2100 } 2101 } else if (fdctrl->data_len > 7) { 2102 /* ERROR */ 2103 fdctrl->fifo[0] = 0x80 | 2104 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); 2105 fdctrl_to_result_phase(fdctrl, 1); 2106 } 2107 } 2108 2109 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) 2110 { 2111 FDrive *cur_drv; 2112 2113 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2114 cur_drv = get_cur_drv(fdctrl); 2115 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { 2116 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1, 2117 cur_drv->sect, 1); 2118 } else { 2119 fd_seek(cur_drv, cur_drv->head, 2120 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1); 2121 } 2122 fdctrl_to_command_phase(fdctrl); 2123 /* Raise Interrupt */ 2124 fdctrl->status0 |= FD_SR0_SEEK; 2125 fdctrl_raise_irq(fdctrl); 2126 } 2127 2128 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) 2129 { 2130 FDrive *cur_drv; 2131 2132 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2133 cur_drv = get_cur_drv(fdctrl); 2134 if (fdctrl->fifo[2] > cur_drv->track) { 2135 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1); 2136 } else { 2137 fd_seek(cur_drv, cur_drv->head, 2138 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1); 2139 } 2140 fdctrl_to_command_phase(fdctrl); 2141 /* Raise Interrupt */ 2142 fdctrl->status0 |= FD_SR0_SEEK; 2143 fdctrl_raise_irq(fdctrl); 2144 } 2145 2146 /* 2147 * Handlers for the execution phase of each command 2148 */ 2149 typedef struct FDCtrlCommand { 2150 uint8_t value; 2151 uint8_t mask; 2152 const char* name; 2153 int parameters; 2154 void (*handler)(FDCtrl *fdctrl, int direction); 2155 int direction; 2156 } FDCtrlCommand; 2157 2158 static const FDCtrlCommand handlers[] = { 2159 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, 2160 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, 2161 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, 2162 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, 2163 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, 2164 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, 2165 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, 2166 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ 2167 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ 2168 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, 2169 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, 2170 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY }, 2171 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, 2172 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, 2173 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, 2174 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, 2175 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, 2176 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, 2177 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, 2178 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, 2179 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, 2180 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, 2181 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, 2182 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, 2183 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, 2184 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, 2185 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, 2186 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, 2187 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, 2188 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, 2189 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ 2190 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ 2191 }; 2192 /* Associate command to an index in the 'handlers' array */ 2193 static uint8_t command_to_handler[256]; 2194 2195 static const FDCtrlCommand *get_command(uint8_t cmd) 2196 { 2197 int idx; 2198 2199 idx = command_to_handler[cmd]; 2200 FLOPPY_DPRINTF("%s command\n", handlers[idx].name); 2201 return &handlers[idx]; 2202 } 2203 2204 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) 2205 { 2206 FDrive *cur_drv; 2207 const FDCtrlCommand *cmd; 2208 uint32_t pos; 2209 2210 /* Reset mode */ 2211 if (!(fdctrl->dor & FD_DOR_nRESET)) { 2212 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 2213 return; 2214 } 2215 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { 2216 FLOPPY_DPRINTF("error: controller not ready for writing\n"); 2217 return; 2218 } 2219 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 2220 2221 FLOPPY_DPRINTF("%s: %02x\n", __func__, value); 2222 2223 /* If data_len spans multiple sectors, the current position in the FIFO 2224 * wraps around while fdctrl->data_pos is the real position in the whole 2225 * request. */ 2226 pos = fdctrl->data_pos++; 2227 pos %= FD_SECTOR_LEN; 2228 fdctrl->fifo[pos] = value; 2229 2230 if (fdctrl->data_pos == fdctrl->data_len) { 2231 fdctrl->msr &= ~FD_MSR_RQM; 2232 } 2233 2234 switch (fdctrl->phase) { 2235 case FD_PHASE_EXECUTION: 2236 /* For DMA requests, RQM should be cleared during execution phase, so 2237 * we would have errored out above. */ 2238 assert(fdctrl->msr & FD_MSR_NONDMA); 2239 2240 /* FIFO data write */ 2241 if (pos == FD_SECTOR_LEN - 1 || 2242 fdctrl->data_pos == fdctrl->data_len) { 2243 cur_drv = get_cur_drv(fdctrl); 2244 if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) 2245 < 0) { 2246 FLOPPY_DPRINTF("error writing sector %d\n", 2247 fd_sector(cur_drv)); 2248 break; 2249 } 2250 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 2251 FLOPPY_DPRINTF("error seeking to next sector %d\n", 2252 fd_sector(cur_drv)); 2253 break; 2254 } 2255 } 2256 2257 /* Switch to result phase when done with the transfer */ 2258 if (fdctrl->data_pos == fdctrl->data_len) { 2259 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2260 } 2261 break; 2262 2263 case FD_PHASE_COMMAND: 2264 assert(!(fdctrl->msr & FD_MSR_NONDMA)); 2265 assert(fdctrl->data_pos < FD_SECTOR_LEN); 2266 2267 if (pos == 0) { 2268 /* The first byte specifies the command. Now we start reading 2269 * as many parameters as this command requires. */ 2270 cmd = get_command(value); 2271 fdctrl->data_len = cmd->parameters + 1; 2272 if (cmd->parameters) { 2273 fdctrl->msr |= FD_MSR_RQM; 2274 } 2275 fdctrl->msr |= FD_MSR_CMDBUSY; 2276 } 2277 2278 if (fdctrl->data_pos == fdctrl->data_len) { 2279 /* We have all parameters now, execute the command */ 2280 fdctrl->phase = FD_PHASE_EXECUTION; 2281 2282 if (fdctrl->data_state & FD_STATE_FORMAT) { 2283 fdctrl_format_sector(fdctrl); 2284 break; 2285 } 2286 2287 cmd = get_command(fdctrl->fifo[0]); 2288 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name); 2289 cmd->handler(fdctrl, cmd->direction); 2290 } 2291 break; 2292 2293 case FD_PHASE_RESULT: 2294 default: 2295 abort(); 2296 } 2297 } 2298 2299 static void fdctrl_result_timer(void *opaque) 2300 { 2301 FDCtrl *fdctrl = opaque; 2302 FDrive *cur_drv = get_cur_drv(fdctrl); 2303 2304 /* Pretend we are spinning. 2305 * This is needed for Coherent, which uses READ ID to check for 2306 * sector interleaving. 2307 */ 2308 if (cur_drv->last_sect != 0) { 2309 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; 2310 } 2311 /* READ_ID can't automatically succeed! */ 2312 if (fdctrl->check_media_rate && 2313 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 2314 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n", 2315 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 2316 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 2317 } else { 2318 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2319 } 2320 } 2321 2322 static void fdctrl_change_cb(void *opaque, bool load) 2323 { 2324 FDrive *drive = opaque; 2325 2326 drive->media_changed = 1; 2327 drive->media_validated = false; 2328 fd_revalidate(drive); 2329 } 2330 2331 static const BlockDevOps fdctrl_block_ops = { 2332 .change_media_cb = fdctrl_change_cb, 2333 }; 2334 2335 /* Init functions */ 2336 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp) 2337 { 2338 unsigned int i; 2339 FDrive *drive; 2340 2341 for (i = 0; i < MAX_FD; i++) { 2342 drive = &fdctrl->drives[i]; 2343 drive->fdctrl = fdctrl; 2344 2345 if (drive->blk) { 2346 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) { 2347 error_setg(errp, "fdc doesn't support drive option werror"); 2348 return; 2349 } 2350 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) { 2351 error_setg(errp, "fdc doesn't support drive option rerror"); 2352 return; 2353 } 2354 } 2355 2356 fd_init(drive); 2357 if (drive->blk) { 2358 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive); 2359 pick_drive_type(drive); 2360 } 2361 fd_revalidate(drive); 2362 } 2363 } 2364 2365 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds) 2366 { 2367 DeviceState *dev; 2368 ISADevice *isadev; 2369 2370 isadev = isa_try_create(bus, TYPE_ISA_FDC); 2371 if (!isadev) { 2372 return NULL; 2373 } 2374 dev = DEVICE(isadev); 2375 2376 if (fds[0]) { 2377 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), 2378 &error_fatal); 2379 } 2380 if (fds[1]) { 2381 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), 2382 &error_fatal); 2383 } 2384 qdev_init_nofail(dev); 2385 2386 return isadev; 2387 } 2388 2389 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, 2390 hwaddr mmio_base, DriveInfo **fds) 2391 { 2392 FDCtrl *fdctrl; 2393 DeviceState *dev; 2394 SysBusDevice *sbd; 2395 FDCtrlSysBus *sys; 2396 2397 dev = qdev_create(NULL, "sysbus-fdc"); 2398 sys = SYSBUS_FDC(dev); 2399 fdctrl = &sys->state; 2400 fdctrl->dma_chann = dma_chann; /* FIXME */ 2401 if (fds[0]) { 2402 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), 2403 &error_fatal); 2404 } 2405 if (fds[1]) { 2406 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), 2407 &error_fatal); 2408 } 2409 qdev_init_nofail(dev); 2410 sbd = SYS_BUS_DEVICE(dev); 2411 sysbus_connect_irq(sbd, 0, irq); 2412 sysbus_mmio_map(sbd, 0, mmio_base); 2413 } 2414 2415 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, 2416 DriveInfo **fds, qemu_irq *fdc_tc) 2417 { 2418 DeviceState *dev; 2419 FDCtrlSysBus *sys; 2420 2421 dev = qdev_create(NULL, "SUNW,fdtwo"); 2422 if (fds[0]) { 2423 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]), 2424 &error_fatal); 2425 } 2426 qdev_init_nofail(dev); 2427 sys = SYSBUS_FDC(dev); 2428 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); 2429 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base); 2430 *fdc_tc = qdev_get_gpio_in(dev, 0); 2431 } 2432 2433 static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp) 2434 { 2435 int i, j; 2436 static int command_tables_inited = 0; 2437 2438 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) { 2439 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'"); 2440 } 2441 2442 /* Fill 'command_to_handler' lookup table */ 2443 if (!command_tables_inited) { 2444 command_tables_inited = 1; 2445 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { 2446 for (j = 0; j < sizeof(command_to_handler); j++) { 2447 if ((j & handlers[i].mask) == handlers[i].value) { 2448 command_to_handler[j] = i; 2449 } 2450 } 2451 } 2452 } 2453 2454 FLOPPY_DPRINTF("init controller\n"); 2455 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); 2456 fdctrl->fifo_size = 512; 2457 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2458 fdctrl_result_timer, fdctrl); 2459 2460 fdctrl->version = 0x90; /* Intel 82078 controller */ 2461 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ 2462 fdctrl->num_floppies = MAX_FD; 2463 2464 if (fdctrl->dma_chann != -1) { 2465 IsaDmaClass *k; 2466 assert(fdctrl->dma); 2467 k = ISADMA_GET_CLASS(fdctrl->dma); 2468 k->register_channel(fdctrl->dma, fdctrl->dma_chann, 2469 &fdctrl_transfer_handler, fdctrl); 2470 } 2471 fdctrl_connect_drives(fdctrl, errp); 2472 } 2473 2474 static const MemoryRegionPortio fdc_portio_list[] = { 2475 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, 2476 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, 2477 PORTIO_END_OF_LIST(), 2478 }; 2479 2480 static void isabus_fdc_realize(DeviceState *dev, Error **errp) 2481 { 2482 ISADevice *isadev = ISA_DEVICE(dev); 2483 FDCtrlISABus *isa = ISA_FDC(dev); 2484 FDCtrl *fdctrl = &isa->state; 2485 Error *err = NULL; 2486 2487 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl, 2488 "fdc"); 2489 2490 isa_init_irq(isadev, &fdctrl->irq, isa->irq); 2491 fdctrl->dma_chann = isa->dma; 2492 if (fdctrl->dma_chann != -1) { 2493 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma); 2494 assert(fdctrl->dma); 2495 } 2496 2497 qdev_set_legacy_instance_id(dev, isa->iobase, 2); 2498 fdctrl_realize_common(fdctrl, &err); 2499 if (err != NULL) { 2500 error_propagate(errp, err); 2501 return; 2502 } 2503 } 2504 2505 static void sysbus_fdc_initfn(Object *obj) 2506 { 2507 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2508 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2509 FDCtrl *fdctrl = &sys->state; 2510 2511 fdctrl->dma_chann = -1; 2512 2513 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl, 2514 "fdc", 0x08); 2515 sysbus_init_mmio(sbd, &fdctrl->iomem); 2516 } 2517 2518 static void sun4m_fdc_initfn(Object *obj) 2519 { 2520 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2521 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2522 FDCtrl *fdctrl = &sys->state; 2523 2524 fdctrl->dma_chann = -1; 2525 2526 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops, 2527 fdctrl, "fdctrl", 0x08); 2528 sysbus_init_mmio(sbd, &fdctrl->iomem); 2529 } 2530 2531 static void sysbus_fdc_common_initfn(Object *obj) 2532 { 2533 DeviceState *dev = DEVICE(obj); 2534 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 2535 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2536 FDCtrl *fdctrl = &sys->state; 2537 2538 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */ 2539 2540 sysbus_init_irq(sbd, &fdctrl->irq); 2541 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1); 2542 } 2543 2544 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp) 2545 { 2546 FDCtrlSysBus *sys = SYSBUS_FDC(dev); 2547 FDCtrl *fdctrl = &sys->state; 2548 2549 fdctrl_realize_common(fdctrl, errp); 2550 } 2551 2552 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i) 2553 { 2554 FDCtrlISABus *isa = ISA_FDC(fdc); 2555 2556 return isa->state.drives[i].drive; 2557 } 2558 2559 static const VMStateDescription vmstate_isa_fdc ={ 2560 .name = "fdc", 2561 .version_id = 2, 2562 .minimum_version_id = 2, 2563 .fields = (VMStateField[]) { 2564 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl), 2565 VMSTATE_END_OF_LIST() 2566 } 2567 }; 2568 2569 static Property isa_fdc_properties[] = { 2570 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0), 2571 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6), 2572 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2), 2573 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk), 2574 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk), 2575 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate, 2576 0, true), 2577 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlISABus, state.drives[0].drive, 2578 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2579 FloppyDriveType), 2580 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlISABus, state.drives[1].drive, 2581 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2582 FloppyDriveType), 2583 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback, 2584 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type, 2585 FloppyDriveType), 2586 DEFINE_PROP_END_OF_LIST(), 2587 }; 2588 2589 static void isabus_fdc_class_init(ObjectClass *klass, void *data) 2590 { 2591 DeviceClass *dc = DEVICE_CLASS(klass); 2592 2593 dc->realize = isabus_fdc_realize; 2594 dc->fw_name = "fdc"; 2595 dc->reset = fdctrl_external_reset_isa; 2596 dc->vmsd = &vmstate_isa_fdc; 2597 dc->props = isa_fdc_properties; 2598 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2599 } 2600 2601 static void isabus_fdc_instance_init(Object *obj) 2602 { 2603 FDCtrlISABus *isa = ISA_FDC(obj); 2604 2605 device_add_bootindex_property(obj, &isa->bootindexA, 2606 "bootindexA", "/floppy@0", 2607 DEVICE(obj), NULL); 2608 device_add_bootindex_property(obj, &isa->bootindexB, 2609 "bootindexB", "/floppy@1", 2610 DEVICE(obj), NULL); 2611 } 2612 2613 static const TypeInfo isa_fdc_info = { 2614 .name = TYPE_ISA_FDC, 2615 .parent = TYPE_ISA_DEVICE, 2616 .instance_size = sizeof(FDCtrlISABus), 2617 .class_init = isabus_fdc_class_init, 2618 .instance_init = isabus_fdc_instance_init, 2619 }; 2620 2621 static const VMStateDescription vmstate_sysbus_fdc ={ 2622 .name = "fdc", 2623 .version_id = 2, 2624 .minimum_version_id = 2, 2625 .fields = (VMStateField[]) { 2626 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl), 2627 VMSTATE_END_OF_LIST() 2628 } 2629 }; 2630 2631 static Property sysbus_fdc_properties[] = { 2632 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk), 2633 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk), 2634 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlSysBus, state.drives[0].drive, 2635 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2636 FloppyDriveType), 2637 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlSysBus, state.drives[1].drive, 2638 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2639 FloppyDriveType), 2640 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback, 2641 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type, 2642 FloppyDriveType), 2643 DEFINE_PROP_END_OF_LIST(), 2644 }; 2645 2646 static void sysbus_fdc_class_init(ObjectClass *klass, void *data) 2647 { 2648 DeviceClass *dc = DEVICE_CLASS(klass); 2649 2650 dc->props = sysbus_fdc_properties; 2651 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2652 } 2653 2654 static const TypeInfo sysbus_fdc_info = { 2655 .name = "sysbus-fdc", 2656 .parent = TYPE_SYSBUS_FDC, 2657 .instance_init = sysbus_fdc_initfn, 2658 .class_init = sysbus_fdc_class_init, 2659 }; 2660 2661 static Property sun4m_fdc_properties[] = { 2662 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk), 2663 DEFINE_PROP_DEFAULT("fdtype", FDCtrlSysBus, state.drives[0].drive, 2664 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2665 FloppyDriveType), 2666 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback, 2667 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type, 2668 FloppyDriveType), 2669 DEFINE_PROP_END_OF_LIST(), 2670 }; 2671 2672 static void sun4m_fdc_class_init(ObjectClass *klass, void *data) 2673 { 2674 DeviceClass *dc = DEVICE_CLASS(klass); 2675 2676 dc->props = sun4m_fdc_properties; 2677 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2678 } 2679 2680 static const TypeInfo sun4m_fdc_info = { 2681 .name = "SUNW,fdtwo", 2682 .parent = TYPE_SYSBUS_FDC, 2683 .instance_init = sun4m_fdc_initfn, 2684 .class_init = sun4m_fdc_class_init, 2685 }; 2686 2687 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data) 2688 { 2689 DeviceClass *dc = DEVICE_CLASS(klass); 2690 2691 dc->realize = sysbus_fdc_common_realize; 2692 dc->reset = fdctrl_external_reset_sysbus; 2693 dc->vmsd = &vmstate_sysbus_fdc; 2694 } 2695 2696 static const TypeInfo sysbus_fdc_type_info = { 2697 .name = TYPE_SYSBUS_FDC, 2698 .parent = TYPE_SYS_BUS_DEVICE, 2699 .instance_size = sizeof(FDCtrlSysBus), 2700 .instance_init = sysbus_fdc_common_initfn, 2701 .abstract = true, 2702 .class_init = sysbus_fdc_common_class_init, 2703 }; 2704 2705 static void fdc_register_types(void) 2706 { 2707 type_register_static(&isa_fdc_info); 2708 type_register_static(&sysbus_fdc_type_info); 2709 type_register_static(&sysbus_fdc_info); 2710 type_register_static(&sun4m_fdc_info); 2711 } 2712 2713 type_init(fdc_register_types) 2714