1 /* 2 * QEMU Floppy disk emulator (Intel 82078) 3 * 4 * Copyright (c) 2003, 2007 Jocelyn Mayer 5 * Copyright (c) 2008 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * The controller is used in Sun4m systems in a slightly different 27 * way. There are changes in DOR register and DMA is not available. 28 */ 29 30 #include "hw/hw.h" 31 #include "hw/block/fdc.h" 32 #include "qemu/error-report.h" 33 #include "qemu/timer.h" 34 #include "hw/isa/isa.h" 35 #include "hw/sysbus.h" 36 #include "hw/qdev-addr.h" 37 #include "sysemu/blockdev.h" 38 #include "sysemu/sysemu.h" 39 #include "qemu/log.h" 40 41 /********************************************************/ 42 /* debug Floppy devices */ 43 //#define DEBUG_FLOPPY 44 45 #ifdef DEBUG_FLOPPY 46 #define FLOPPY_DPRINTF(fmt, ...) \ 47 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) 48 #else 49 #define FLOPPY_DPRINTF(fmt, ...) 50 #endif 51 52 /********************************************************/ 53 /* Floppy drive emulation */ 54 55 typedef enum FDriveRate { 56 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */ 57 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */ 58 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */ 59 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */ 60 } FDriveRate; 61 62 typedef struct FDFormat { 63 FDriveType drive; 64 uint8_t last_sect; 65 uint8_t max_track; 66 uint8_t max_head; 67 FDriveRate rate; 68 } FDFormat; 69 70 static const FDFormat fd_formats[] = { 71 /* First entry is default format */ 72 /* 1.44 MB 3"1/2 floppy disks */ 73 { FDRIVE_DRV_144, 18, 80, 1, FDRIVE_RATE_500K, }, 74 { FDRIVE_DRV_144, 20, 80, 1, FDRIVE_RATE_500K, }, 75 { FDRIVE_DRV_144, 21, 80, 1, FDRIVE_RATE_500K, }, 76 { FDRIVE_DRV_144, 21, 82, 1, FDRIVE_RATE_500K, }, 77 { FDRIVE_DRV_144, 21, 83, 1, FDRIVE_RATE_500K, }, 78 { FDRIVE_DRV_144, 22, 80, 1, FDRIVE_RATE_500K, }, 79 { FDRIVE_DRV_144, 23, 80, 1, FDRIVE_RATE_500K, }, 80 { FDRIVE_DRV_144, 24, 80, 1, FDRIVE_RATE_500K, }, 81 /* 2.88 MB 3"1/2 floppy disks */ 82 { FDRIVE_DRV_288, 36, 80, 1, FDRIVE_RATE_1M, }, 83 { FDRIVE_DRV_288, 39, 80, 1, FDRIVE_RATE_1M, }, 84 { FDRIVE_DRV_288, 40, 80, 1, FDRIVE_RATE_1M, }, 85 { FDRIVE_DRV_288, 44, 80, 1, FDRIVE_RATE_1M, }, 86 { FDRIVE_DRV_288, 48, 80, 1, FDRIVE_RATE_1M, }, 87 /* 720 kB 3"1/2 floppy disks */ 88 { FDRIVE_DRV_144, 9, 80, 1, FDRIVE_RATE_250K, }, 89 { FDRIVE_DRV_144, 10, 80, 1, FDRIVE_RATE_250K, }, 90 { FDRIVE_DRV_144, 10, 82, 1, FDRIVE_RATE_250K, }, 91 { FDRIVE_DRV_144, 10, 83, 1, FDRIVE_RATE_250K, }, 92 { FDRIVE_DRV_144, 13, 80, 1, FDRIVE_RATE_250K, }, 93 { FDRIVE_DRV_144, 14, 80, 1, FDRIVE_RATE_250K, }, 94 /* 1.2 MB 5"1/4 floppy disks */ 95 { FDRIVE_DRV_120, 15, 80, 1, FDRIVE_RATE_500K, }, 96 { FDRIVE_DRV_120, 18, 80, 1, FDRIVE_RATE_500K, }, 97 { FDRIVE_DRV_120, 18, 82, 1, FDRIVE_RATE_500K, }, 98 { FDRIVE_DRV_120, 18, 83, 1, FDRIVE_RATE_500K, }, 99 { FDRIVE_DRV_120, 20, 80, 1, FDRIVE_RATE_500K, }, 100 /* 720 kB 5"1/4 floppy disks */ 101 { FDRIVE_DRV_120, 9, 80, 1, FDRIVE_RATE_250K, }, 102 { FDRIVE_DRV_120, 11, 80, 1, FDRIVE_RATE_250K, }, 103 /* 360 kB 5"1/4 floppy disks */ 104 { FDRIVE_DRV_120, 9, 40, 1, FDRIVE_RATE_300K, }, 105 { FDRIVE_DRV_120, 9, 40, 0, FDRIVE_RATE_300K, }, 106 { FDRIVE_DRV_120, 10, 41, 1, FDRIVE_RATE_300K, }, 107 { FDRIVE_DRV_120, 10, 42, 1, FDRIVE_RATE_300K, }, 108 /* 320 kB 5"1/4 floppy disks */ 109 { FDRIVE_DRV_120, 8, 40, 1, FDRIVE_RATE_250K, }, 110 { FDRIVE_DRV_120, 8, 40, 0, FDRIVE_RATE_250K, }, 111 /* 360 kB must match 5"1/4 better than 3"1/2... */ 112 { FDRIVE_DRV_144, 9, 80, 0, FDRIVE_RATE_250K, }, 113 /* end */ 114 { FDRIVE_DRV_NONE, -1, -1, 0, 0, }, 115 }; 116 117 static void pick_geometry(BlockDriverState *bs, int *nb_heads, 118 int *max_track, int *last_sect, 119 FDriveType drive_in, FDriveType *drive, 120 FDriveRate *rate) 121 { 122 const FDFormat *parse; 123 uint64_t nb_sectors, size; 124 int i, first_match, match; 125 126 bdrv_get_geometry(bs, &nb_sectors); 127 match = -1; 128 first_match = -1; 129 for (i = 0; ; i++) { 130 parse = &fd_formats[i]; 131 if (parse->drive == FDRIVE_DRV_NONE) { 132 break; 133 } 134 if (drive_in == parse->drive || 135 drive_in == FDRIVE_DRV_NONE) { 136 size = (parse->max_head + 1) * parse->max_track * 137 parse->last_sect; 138 if (nb_sectors == size) { 139 match = i; 140 break; 141 } 142 if (first_match == -1) { 143 first_match = i; 144 } 145 } 146 } 147 if (match == -1) { 148 if (first_match == -1) { 149 match = 1; 150 } else { 151 match = first_match; 152 } 153 parse = &fd_formats[match]; 154 } 155 *nb_heads = parse->max_head + 1; 156 *max_track = parse->max_track; 157 *last_sect = parse->last_sect; 158 *drive = parse->drive; 159 *rate = parse->rate; 160 } 161 162 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) 163 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) 164 165 /* Will always be a fixed parameter for us */ 166 #define FD_SECTOR_LEN 512 167 #define FD_SECTOR_SC 2 /* Sector size code */ 168 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ 169 170 typedef struct FDCtrl FDCtrl; 171 172 /* Floppy disk drive emulation */ 173 typedef enum FDiskFlags { 174 FDISK_DBL_SIDES = 0x01, 175 } FDiskFlags; 176 177 typedef struct FDrive { 178 FDCtrl *fdctrl; 179 BlockDriverState *bs; 180 /* Drive status */ 181 FDriveType drive; 182 uint8_t perpendicular; /* 2.88 MB access mode */ 183 /* Position */ 184 uint8_t head; 185 uint8_t track; 186 uint8_t sect; 187 /* Media */ 188 FDiskFlags flags; 189 uint8_t last_sect; /* Nb sector per track */ 190 uint8_t max_track; /* Nb of tracks */ 191 uint16_t bps; /* Bytes per sector */ 192 uint8_t ro; /* Is read-only */ 193 uint8_t media_changed; /* Is media changed */ 194 uint8_t media_rate; /* Data rate of medium */ 195 } FDrive; 196 197 static void fd_init(FDrive *drv) 198 { 199 /* Drive */ 200 drv->drive = FDRIVE_DRV_NONE; 201 drv->perpendicular = 0; 202 /* Disk */ 203 drv->last_sect = 0; 204 drv->max_track = 0; 205 } 206 207 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) 208 209 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, 210 uint8_t last_sect, uint8_t num_sides) 211 { 212 return (((track * num_sides) + head) * last_sect) + sect - 1; 213 } 214 215 /* Returns current position, in sectors, for given drive */ 216 static int fd_sector(FDrive *drv) 217 { 218 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, 219 NUM_SIDES(drv)); 220 } 221 222 /* Seek to a new position: 223 * returns 0 if already on right track 224 * returns 1 if track changed 225 * returns 2 if track is invalid 226 * returns 3 if sector is invalid 227 * returns 4 if seek is disabled 228 */ 229 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, 230 int enable_seek) 231 { 232 uint32_t sector; 233 int ret; 234 235 if (track > drv->max_track || 236 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { 237 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 238 head, track, sect, 1, 239 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 240 drv->max_track, drv->last_sect); 241 return 2; 242 } 243 if (sect > drv->last_sect) { 244 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 245 head, track, sect, 1, 246 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 247 drv->max_track, drv->last_sect); 248 return 3; 249 } 250 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); 251 ret = 0; 252 if (sector != fd_sector(drv)) { 253 #if 0 254 if (!enable_seek) { 255 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x" 256 " (max=%d %02x %02x)\n", 257 head, track, sect, 1, drv->max_track, 258 drv->last_sect); 259 return 4; 260 } 261 #endif 262 drv->head = head; 263 if (drv->track != track) { 264 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) { 265 drv->media_changed = 0; 266 } 267 ret = 1; 268 } 269 drv->track = track; 270 drv->sect = sect; 271 } 272 273 if (drv->bs == NULL || !bdrv_is_inserted(drv->bs)) { 274 ret = 2; 275 } 276 277 return ret; 278 } 279 280 /* Set drive back to track 0 */ 281 static void fd_recalibrate(FDrive *drv) 282 { 283 FLOPPY_DPRINTF("recalibrate\n"); 284 fd_seek(drv, 0, 0, 1, 1); 285 } 286 287 /* Revalidate a disk drive after a disk change */ 288 static void fd_revalidate(FDrive *drv) 289 { 290 int nb_heads, max_track, last_sect, ro; 291 FDriveType drive; 292 FDriveRate rate; 293 294 FLOPPY_DPRINTF("revalidate\n"); 295 if (drv->bs != NULL) { 296 ro = bdrv_is_read_only(drv->bs); 297 pick_geometry(drv->bs, &nb_heads, &max_track, 298 &last_sect, drv->drive, &drive, &rate); 299 if (!bdrv_is_inserted(drv->bs)) { 300 FLOPPY_DPRINTF("No disk in drive\n"); 301 } else { 302 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads, 303 max_track, last_sect, ro ? "ro" : "rw"); 304 } 305 if (nb_heads == 1) { 306 drv->flags &= ~FDISK_DBL_SIDES; 307 } else { 308 drv->flags |= FDISK_DBL_SIDES; 309 } 310 drv->max_track = max_track; 311 drv->last_sect = last_sect; 312 drv->ro = ro; 313 drv->drive = drive; 314 drv->media_rate = rate; 315 } else { 316 FLOPPY_DPRINTF("No drive connected\n"); 317 drv->last_sect = 0; 318 drv->max_track = 0; 319 drv->flags &= ~FDISK_DBL_SIDES; 320 } 321 } 322 323 /********************************************************/ 324 /* Intel 82078 floppy disk controller emulation */ 325 326 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); 327 static void fdctrl_reset_fifo(FDCtrl *fdctrl); 328 static int fdctrl_transfer_handler (void *opaque, int nchan, 329 int dma_pos, int dma_len); 330 static void fdctrl_raise_irq(FDCtrl *fdctrl); 331 static FDrive *get_cur_drv(FDCtrl *fdctrl); 332 333 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); 334 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); 335 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); 336 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); 337 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); 338 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); 339 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); 340 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); 341 static uint32_t fdctrl_read_data(FDCtrl *fdctrl); 342 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); 343 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); 344 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); 345 346 enum { 347 FD_DIR_WRITE = 0, 348 FD_DIR_READ = 1, 349 FD_DIR_SCANE = 2, 350 FD_DIR_SCANL = 3, 351 FD_DIR_SCANH = 4, 352 FD_DIR_VERIFY = 5, 353 }; 354 355 enum { 356 FD_STATE_MULTI = 0x01, /* multi track flag */ 357 FD_STATE_FORMAT = 0x02, /* format flag */ 358 }; 359 360 enum { 361 FD_REG_SRA = 0x00, 362 FD_REG_SRB = 0x01, 363 FD_REG_DOR = 0x02, 364 FD_REG_TDR = 0x03, 365 FD_REG_MSR = 0x04, 366 FD_REG_DSR = 0x04, 367 FD_REG_FIFO = 0x05, 368 FD_REG_DIR = 0x07, 369 FD_REG_CCR = 0x07, 370 }; 371 372 enum { 373 FD_CMD_READ_TRACK = 0x02, 374 FD_CMD_SPECIFY = 0x03, 375 FD_CMD_SENSE_DRIVE_STATUS = 0x04, 376 FD_CMD_WRITE = 0x05, 377 FD_CMD_READ = 0x06, 378 FD_CMD_RECALIBRATE = 0x07, 379 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, 380 FD_CMD_WRITE_DELETED = 0x09, 381 FD_CMD_READ_ID = 0x0a, 382 FD_CMD_READ_DELETED = 0x0c, 383 FD_CMD_FORMAT_TRACK = 0x0d, 384 FD_CMD_DUMPREG = 0x0e, 385 FD_CMD_SEEK = 0x0f, 386 FD_CMD_VERSION = 0x10, 387 FD_CMD_SCAN_EQUAL = 0x11, 388 FD_CMD_PERPENDICULAR_MODE = 0x12, 389 FD_CMD_CONFIGURE = 0x13, 390 FD_CMD_LOCK = 0x14, 391 FD_CMD_VERIFY = 0x16, 392 FD_CMD_POWERDOWN_MODE = 0x17, 393 FD_CMD_PART_ID = 0x18, 394 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, 395 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, 396 FD_CMD_SAVE = 0x2e, 397 FD_CMD_OPTION = 0x33, 398 FD_CMD_RESTORE = 0x4e, 399 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, 400 FD_CMD_RELATIVE_SEEK_OUT = 0x8f, 401 FD_CMD_FORMAT_AND_WRITE = 0xcd, 402 FD_CMD_RELATIVE_SEEK_IN = 0xcf, 403 }; 404 405 enum { 406 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ 407 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ 408 FD_CONFIG_POLL = 0x10, /* Poll enabled */ 409 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ 410 FD_CONFIG_EIS = 0x40, /* No implied seeks */ 411 }; 412 413 enum { 414 FD_SR0_DS0 = 0x01, 415 FD_SR0_DS1 = 0x02, 416 FD_SR0_HEAD = 0x04, 417 FD_SR0_EQPMT = 0x10, 418 FD_SR0_SEEK = 0x20, 419 FD_SR0_ABNTERM = 0x40, 420 FD_SR0_INVCMD = 0x80, 421 FD_SR0_RDYCHG = 0xc0, 422 }; 423 424 enum { 425 FD_SR1_MA = 0x01, /* Missing address mark */ 426 FD_SR1_NW = 0x02, /* Not writable */ 427 FD_SR1_EC = 0x80, /* End of cylinder */ 428 }; 429 430 enum { 431 FD_SR2_SNS = 0x04, /* Scan not satisfied */ 432 FD_SR2_SEH = 0x08, /* Scan equal hit */ 433 }; 434 435 enum { 436 FD_SRA_DIR = 0x01, 437 FD_SRA_nWP = 0x02, 438 FD_SRA_nINDX = 0x04, 439 FD_SRA_HDSEL = 0x08, 440 FD_SRA_nTRK0 = 0x10, 441 FD_SRA_STEP = 0x20, 442 FD_SRA_nDRV2 = 0x40, 443 FD_SRA_INTPEND = 0x80, 444 }; 445 446 enum { 447 FD_SRB_MTR0 = 0x01, 448 FD_SRB_MTR1 = 0x02, 449 FD_SRB_WGATE = 0x04, 450 FD_SRB_RDATA = 0x08, 451 FD_SRB_WDATA = 0x10, 452 FD_SRB_DR0 = 0x20, 453 }; 454 455 enum { 456 #if MAX_FD == 4 457 FD_DOR_SELMASK = 0x03, 458 #else 459 FD_DOR_SELMASK = 0x01, 460 #endif 461 FD_DOR_nRESET = 0x04, 462 FD_DOR_DMAEN = 0x08, 463 FD_DOR_MOTEN0 = 0x10, 464 FD_DOR_MOTEN1 = 0x20, 465 FD_DOR_MOTEN2 = 0x40, 466 FD_DOR_MOTEN3 = 0x80, 467 }; 468 469 enum { 470 #if MAX_FD == 4 471 FD_TDR_BOOTSEL = 0x0c, 472 #else 473 FD_TDR_BOOTSEL = 0x04, 474 #endif 475 }; 476 477 enum { 478 FD_DSR_DRATEMASK= 0x03, 479 FD_DSR_PWRDOWN = 0x40, 480 FD_DSR_SWRESET = 0x80, 481 }; 482 483 enum { 484 FD_MSR_DRV0BUSY = 0x01, 485 FD_MSR_DRV1BUSY = 0x02, 486 FD_MSR_DRV2BUSY = 0x04, 487 FD_MSR_DRV3BUSY = 0x08, 488 FD_MSR_CMDBUSY = 0x10, 489 FD_MSR_NONDMA = 0x20, 490 FD_MSR_DIO = 0x40, 491 FD_MSR_RQM = 0x80, 492 }; 493 494 enum { 495 FD_DIR_DSKCHG = 0x80, 496 }; 497 498 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) 499 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) 500 501 struct FDCtrl { 502 MemoryRegion iomem; 503 qemu_irq irq; 504 /* Controller state */ 505 QEMUTimer *result_timer; 506 int dma_chann; 507 /* Controller's identification */ 508 uint8_t version; 509 /* HW */ 510 uint8_t sra; 511 uint8_t srb; 512 uint8_t dor; 513 uint8_t dor_vmstate; /* only used as temp during vmstate */ 514 uint8_t tdr; 515 uint8_t dsr; 516 uint8_t msr; 517 uint8_t cur_drv; 518 uint8_t status0; 519 uint8_t status1; 520 uint8_t status2; 521 /* Command FIFO */ 522 uint8_t *fifo; 523 int32_t fifo_size; 524 uint32_t data_pos; 525 uint32_t data_len; 526 uint8_t data_state; 527 uint8_t data_dir; 528 uint8_t eot; /* last wanted sector */ 529 /* States kept only to be returned back */ 530 /* precompensation */ 531 uint8_t precomp_trk; 532 uint8_t config; 533 uint8_t lock; 534 /* Power down config (also with status regB access mode */ 535 uint8_t pwrd; 536 /* Floppy drives */ 537 uint8_t num_floppies; 538 /* Sun4m quirks? */ 539 int sun4m; 540 FDrive drives[MAX_FD]; 541 int reset_sensei; 542 uint32_t check_media_rate; 543 /* Timers state */ 544 uint8_t timer0; 545 uint8_t timer1; 546 }; 547 548 typedef struct FDCtrlSysBus { 549 SysBusDevice busdev; 550 struct FDCtrl state; 551 } FDCtrlSysBus; 552 553 typedef struct FDCtrlISABus { 554 ISADevice busdev; 555 uint32_t iobase; 556 uint32_t irq; 557 uint32_t dma; 558 struct FDCtrl state; 559 int32_t bootindexA; 560 int32_t bootindexB; 561 } FDCtrlISABus; 562 563 static uint32_t fdctrl_read (void *opaque, uint32_t reg) 564 { 565 FDCtrl *fdctrl = opaque; 566 uint32_t retval; 567 568 reg &= 7; 569 switch (reg) { 570 case FD_REG_SRA: 571 retval = fdctrl_read_statusA(fdctrl); 572 break; 573 case FD_REG_SRB: 574 retval = fdctrl_read_statusB(fdctrl); 575 break; 576 case FD_REG_DOR: 577 retval = fdctrl_read_dor(fdctrl); 578 break; 579 case FD_REG_TDR: 580 retval = fdctrl_read_tape(fdctrl); 581 break; 582 case FD_REG_MSR: 583 retval = fdctrl_read_main_status(fdctrl); 584 break; 585 case FD_REG_FIFO: 586 retval = fdctrl_read_data(fdctrl); 587 break; 588 case FD_REG_DIR: 589 retval = fdctrl_read_dir(fdctrl); 590 break; 591 default: 592 retval = (uint32_t)(-1); 593 break; 594 } 595 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); 596 597 return retval; 598 } 599 600 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) 601 { 602 FDCtrl *fdctrl = opaque; 603 604 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); 605 606 reg &= 7; 607 switch (reg) { 608 case FD_REG_DOR: 609 fdctrl_write_dor(fdctrl, value); 610 break; 611 case FD_REG_TDR: 612 fdctrl_write_tape(fdctrl, value); 613 break; 614 case FD_REG_DSR: 615 fdctrl_write_rate(fdctrl, value); 616 break; 617 case FD_REG_FIFO: 618 fdctrl_write_data(fdctrl, value); 619 break; 620 case FD_REG_CCR: 621 fdctrl_write_ccr(fdctrl, value); 622 break; 623 default: 624 break; 625 } 626 } 627 628 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg, 629 unsigned ize) 630 { 631 return fdctrl_read(opaque, (uint32_t)reg); 632 } 633 634 static void fdctrl_write_mem (void *opaque, hwaddr reg, 635 uint64_t value, unsigned size) 636 { 637 fdctrl_write(opaque, (uint32_t)reg, value); 638 } 639 640 static const MemoryRegionOps fdctrl_mem_ops = { 641 .read = fdctrl_read_mem, 642 .write = fdctrl_write_mem, 643 .endianness = DEVICE_NATIVE_ENDIAN, 644 }; 645 646 static const MemoryRegionOps fdctrl_mem_strict_ops = { 647 .read = fdctrl_read_mem, 648 .write = fdctrl_write_mem, 649 .endianness = DEVICE_NATIVE_ENDIAN, 650 .valid = { 651 .min_access_size = 1, 652 .max_access_size = 1, 653 }, 654 }; 655 656 static bool fdrive_media_changed_needed(void *opaque) 657 { 658 FDrive *drive = opaque; 659 660 return (drive->bs != NULL && drive->media_changed != 1); 661 } 662 663 static const VMStateDescription vmstate_fdrive_media_changed = { 664 .name = "fdrive/media_changed", 665 .version_id = 1, 666 .minimum_version_id = 1, 667 .minimum_version_id_old = 1, 668 .fields = (VMStateField[]) { 669 VMSTATE_UINT8(media_changed, FDrive), 670 VMSTATE_END_OF_LIST() 671 } 672 }; 673 674 static bool fdrive_media_rate_needed(void *opaque) 675 { 676 FDrive *drive = opaque; 677 678 return drive->fdctrl->check_media_rate; 679 } 680 681 static const VMStateDescription vmstate_fdrive_media_rate = { 682 .name = "fdrive/media_rate", 683 .version_id = 1, 684 .minimum_version_id = 1, 685 .minimum_version_id_old = 1, 686 .fields = (VMStateField[]) { 687 VMSTATE_UINT8(media_rate, FDrive), 688 VMSTATE_END_OF_LIST() 689 } 690 }; 691 692 static const VMStateDescription vmstate_fdrive = { 693 .name = "fdrive", 694 .version_id = 1, 695 .minimum_version_id = 1, 696 .minimum_version_id_old = 1, 697 .fields = (VMStateField[]) { 698 VMSTATE_UINT8(head, FDrive), 699 VMSTATE_UINT8(track, FDrive), 700 VMSTATE_UINT8(sect, FDrive), 701 VMSTATE_END_OF_LIST() 702 }, 703 .subsections = (VMStateSubsection[]) { 704 { 705 .vmsd = &vmstate_fdrive_media_changed, 706 .needed = &fdrive_media_changed_needed, 707 } , { 708 .vmsd = &vmstate_fdrive_media_rate, 709 .needed = &fdrive_media_rate_needed, 710 } , { 711 /* empty */ 712 } 713 } 714 }; 715 716 static void fdc_pre_save(void *opaque) 717 { 718 FDCtrl *s = opaque; 719 720 s->dor_vmstate = s->dor | GET_CUR_DRV(s); 721 } 722 723 static int fdc_post_load(void *opaque, int version_id) 724 { 725 FDCtrl *s = opaque; 726 727 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); 728 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; 729 return 0; 730 } 731 732 static const VMStateDescription vmstate_fdc = { 733 .name = "fdc", 734 .version_id = 2, 735 .minimum_version_id = 2, 736 .minimum_version_id_old = 2, 737 .pre_save = fdc_pre_save, 738 .post_load = fdc_post_load, 739 .fields = (VMStateField []) { 740 /* Controller State */ 741 VMSTATE_UINT8(sra, FDCtrl), 742 VMSTATE_UINT8(srb, FDCtrl), 743 VMSTATE_UINT8(dor_vmstate, FDCtrl), 744 VMSTATE_UINT8(tdr, FDCtrl), 745 VMSTATE_UINT8(dsr, FDCtrl), 746 VMSTATE_UINT8(msr, FDCtrl), 747 VMSTATE_UINT8(status0, FDCtrl), 748 VMSTATE_UINT8(status1, FDCtrl), 749 VMSTATE_UINT8(status2, FDCtrl), 750 /* Command FIFO */ 751 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, 752 uint8_t), 753 VMSTATE_UINT32(data_pos, FDCtrl), 754 VMSTATE_UINT32(data_len, FDCtrl), 755 VMSTATE_UINT8(data_state, FDCtrl), 756 VMSTATE_UINT8(data_dir, FDCtrl), 757 VMSTATE_UINT8(eot, FDCtrl), 758 /* States kept only to be returned back */ 759 VMSTATE_UINT8(timer0, FDCtrl), 760 VMSTATE_UINT8(timer1, FDCtrl), 761 VMSTATE_UINT8(precomp_trk, FDCtrl), 762 VMSTATE_UINT8(config, FDCtrl), 763 VMSTATE_UINT8(lock, FDCtrl), 764 VMSTATE_UINT8(pwrd, FDCtrl), 765 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl), 766 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, 767 vmstate_fdrive, FDrive), 768 VMSTATE_END_OF_LIST() 769 } 770 }; 771 772 static void fdctrl_external_reset_sysbus(DeviceState *d) 773 { 774 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev); 775 FDCtrl *s = &sys->state; 776 777 fdctrl_reset(s, 0); 778 } 779 780 static void fdctrl_external_reset_isa(DeviceState *d) 781 { 782 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev); 783 FDCtrl *s = &isa->state; 784 785 fdctrl_reset(s, 0); 786 } 787 788 static void fdctrl_handle_tc(void *opaque, int irq, int level) 789 { 790 //FDCtrl *s = opaque; 791 792 if (level) { 793 // XXX 794 FLOPPY_DPRINTF("TC pulsed\n"); 795 } 796 } 797 798 /* Change IRQ state */ 799 static void fdctrl_reset_irq(FDCtrl *fdctrl) 800 { 801 fdctrl->status0 = 0; 802 if (!(fdctrl->sra & FD_SRA_INTPEND)) 803 return; 804 FLOPPY_DPRINTF("Reset interrupt\n"); 805 qemu_set_irq(fdctrl->irq, 0); 806 fdctrl->sra &= ~FD_SRA_INTPEND; 807 } 808 809 static void fdctrl_raise_irq(FDCtrl *fdctrl) 810 { 811 /* Sparc mutation */ 812 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) { 813 /* XXX: not sure */ 814 fdctrl->msr &= ~FD_MSR_CMDBUSY; 815 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 816 return; 817 } 818 if (!(fdctrl->sra & FD_SRA_INTPEND)) { 819 qemu_set_irq(fdctrl->irq, 1); 820 fdctrl->sra |= FD_SRA_INTPEND; 821 } 822 823 fdctrl->reset_sensei = 0; 824 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); 825 } 826 827 /* Reset controller */ 828 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) 829 { 830 int i; 831 832 FLOPPY_DPRINTF("reset controller\n"); 833 fdctrl_reset_irq(fdctrl); 834 /* Initialise controller */ 835 fdctrl->sra = 0; 836 fdctrl->srb = 0xc0; 837 if (!fdctrl->drives[1].bs) 838 fdctrl->sra |= FD_SRA_nDRV2; 839 fdctrl->cur_drv = 0; 840 fdctrl->dor = FD_DOR_nRESET; 841 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; 842 fdctrl->msr = FD_MSR_RQM; 843 /* FIFO state */ 844 fdctrl->data_pos = 0; 845 fdctrl->data_len = 0; 846 fdctrl->data_state = 0; 847 fdctrl->data_dir = FD_DIR_WRITE; 848 for (i = 0; i < MAX_FD; i++) 849 fd_recalibrate(&fdctrl->drives[i]); 850 fdctrl_reset_fifo(fdctrl); 851 if (do_irq) { 852 fdctrl->status0 |= FD_SR0_RDYCHG; 853 fdctrl_raise_irq(fdctrl); 854 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; 855 } 856 } 857 858 static inline FDrive *drv0(FDCtrl *fdctrl) 859 { 860 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; 861 } 862 863 static inline FDrive *drv1(FDCtrl *fdctrl) 864 { 865 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) 866 return &fdctrl->drives[1]; 867 else 868 return &fdctrl->drives[0]; 869 } 870 871 #if MAX_FD == 4 872 static inline FDrive *drv2(FDCtrl *fdctrl) 873 { 874 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) 875 return &fdctrl->drives[2]; 876 else 877 return &fdctrl->drives[1]; 878 } 879 880 static inline FDrive *drv3(FDCtrl *fdctrl) 881 { 882 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) 883 return &fdctrl->drives[3]; 884 else 885 return &fdctrl->drives[2]; 886 } 887 #endif 888 889 static FDrive *get_cur_drv(FDCtrl *fdctrl) 890 { 891 switch (fdctrl->cur_drv) { 892 case 0: return drv0(fdctrl); 893 case 1: return drv1(fdctrl); 894 #if MAX_FD == 4 895 case 2: return drv2(fdctrl); 896 case 3: return drv3(fdctrl); 897 #endif 898 default: return NULL; 899 } 900 } 901 902 /* Status A register : 0x00 (read-only) */ 903 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) 904 { 905 uint32_t retval = fdctrl->sra; 906 907 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); 908 909 return retval; 910 } 911 912 /* Status B register : 0x01 (read-only) */ 913 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) 914 { 915 uint32_t retval = fdctrl->srb; 916 917 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); 918 919 return retval; 920 } 921 922 /* Digital output register : 0x02 */ 923 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) 924 { 925 uint32_t retval = fdctrl->dor; 926 927 /* Selected drive */ 928 retval |= fdctrl->cur_drv; 929 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); 930 931 return retval; 932 } 933 934 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) 935 { 936 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); 937 938 /* Motors */ 939 if (value & FD_DOR_MOTEN0) 940 fdctrl->srb |= FD_SRB_MTR0; 941 else 942 fdctrl->srb &= ~FD_SRB_MTR0; 943 if (value & FD_DOR_MOTEN1) 944 fdctrl->srb |= FD_SRB_MTR1; 945 else 946 fdctrl->srb &= ~FD_SRB_MTR1; 947 948 /* Drive */ 949 if (value & 1) 950 fdctrl->srb |= FD_SRB_DR0; 951 else 952 fdctrl->srb &= ~FD_SRB_DR0; 953 954 /* Reset */ 955 if (!(value & FD_DOR_nRESET)) { 956 if (fdctrl->dor & FD_DOR_nRESET) { 957 FLOPPY_DPRINTF("controller enter RESET state\n"); 958 } 959 } else { 960 if (!(fdctrl->dor & FD_DOR_nRESET)) { 961 FLOPPY_DPRINTF("controller out of RESET state\n"); 962 fdctrl_reset(fdctrl, 1); 963 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 964 } 965 } 966 /* Selected drive */ 967 fdctrl->cur_drv = value & FD_DOR_SELMASK; 968 969 fdctrl->dor = value; 970 } 971 972 /* Tape drive register : 0x03 */ 973 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) 974 { 975 uint32_t retval = fdctrl->tdr; 976 977 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); 978 979 return retval; 980 } 981 982 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) 983 { 984 /* Reset mode */ 985 if (!(fdctrl->dor & FD_DOR_nRESET)) { 986 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 987 return; 988 } 989 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); 990 /* Disk boot selection indicator */ 991 fdctrl->tdr = value & FD_TDR_BOOTSEL; 992 /* Tape indicators: never allow */ 993 } 994 995 /* Main status register : 0x04 (read) */ 996 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) 997 { 998 uint32_t retval = fdctrl->msr; 999 1000 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1001 fdctrl->dor |= FD_DOR_nRESET; 1002 1003 /* Sparc mutation */ 1004 if (fdctrl->sun4m) { 1005 retval |= FD_MSR_DIO; 1006 fdctrl_reset_irq(fdctrl); 1007 }; 1008 1009 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); 1010 1011 return retval; 1012 } 1013 1014 /* Data select rate register : 0x04 (write) */ 1015 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) 1016 { 1017 /* Reset mode */ 1018 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1019 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1020 return; 1021 } 1022 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); 1023 /* Reset: autoclear */ 1024 if (value & FD_DSR_SWRESET) { 1025 fdctrl->dor &= ~FD_DOR_nRESET; 1026 fdctrl_reset(fdctrl, 1); 1027 fdctrl->dor |= FD_DOR_nRESET; 1028 } 1029 if (value & FD_DSR_PWRDOWN) { 1030 fdctrl_reset(fdctrl, 1); 1031 } 1032 fdctrl->dsr = value; 1033 } 1034 1035 /* Configuration control register: 0x07 (write) */ 1036 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) 1037 { 1038 /* Reset mode */ 1039 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1040 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1041 return; 1042 } 1043 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); 1044 1045 /* Only the rate selection bits used in AT mode, and we 1046 * store those in the DSR. 1047 */ 1048 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | 1049 (value & FD_DSR_DRATEMASK); 1050 } 1051 1052 static int fdctrl_media_changed(FDrive *drv) 1053 { 1054 return drv->media_changed; 1055 } 1056 1057 /* Digital input register : 0x07 (read-only) */ 1058 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) 1059 { 1060 uint32_t retval = 0; 1061 1062 if (fdctrl_media_changed(get_cur_drv(fdctrl))) { 1063 retval |= FD_DIR_DSKCHG; 1064 } 1065 if (retval != 0) { 1066 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); 1067 } 1068 1069 return retval; 1070 } 1071 1072 /* FIFO state control */ 1073 static void fdctrl_reset_fifo(FDCtrl *fdctrl) 1074 { 1075 fdctrl->data_dir = FD_DIR_WRITE; 1076 fdctrl->data_pos = 0; 1077 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); 1078 } 1079 1080 /* Set FIFO status for the host to read */ 1081 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len) 1082 { 1083 fdctrl->data_dir = FD_DIR_READ; 1084 fdctrl->data_len = fifo_len; 1085 fdctrl->data_pos = 0; 1086 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; 1087 } 1088 1089 /* Set an error: unimplemented/unknown command */ 1090 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) 1091 { 1092 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n", 1093 fdctrl->fifo[0]); 1094 fdctrl->fifo[0] = FD_SR0_INVCMD; 1095 fdctrl_set_fifo(fdctrl, 1); 1096 } 1097 1098 /* Seek to next sector 1099 * returns 0 when end of track reached (for DBL_SIDES on head 1) 1100 * otherwise returns 1 1101 */ 1102 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) 1103 { 1104 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", 1105 cur_drv->head, cur_drv->track, cur_drv->sect, 1106 fd_sector(cur_drv)); 1107 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an 1108 error in fact */ 1109 uint8_t new_head = cur_drv->head; 1110 uint8_t new_track = cur_drv->track; 1111 uint8_t new_sect = cur_drv->sect; 1112 1113 int ret = 1; 1114 1115 if (new_sect >= cur_drv->last_sect || 1116 new_sect == fdctrl->eot) { 1117 new_sect = 1; 1118 if (FD_MULTI_TRACK(fdctrl->data_state)) { 1119 if (new_head == 0 && 1120 (cur_drv->flags & FDISK_DBL_SIDES) != 0) { 1121 new_head = 1; 1122 } else { 1123 new_head = 0; 1124 new_track++; 1125 fdctrl->status0 |= FD_SR0_SEEK; 1126 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) { 1127 ret = 0; 1128 } 1129 } 1130 } else { 1131 fdctrl->status0 |= FD_SR0_SEEK; 1132 new_track++; 1133 ret = 0; 1134 } 1135 if (ret == 1) { 1136 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", 1137 new_head, new_track, new_sect, fd_sector(cur_drv)); 1138 } 1139 } else { 1140 new_sect++; 1141 } 1142 fd_seek(cur_drv, new_head, new_track, new_sect, 1); 1143 return ret; 1144 } 1145 1146 /* Callback for transfer end (stop or abort) */ 1147 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, 1148 uint8_t status1, uint8_t status2) 1149 { 1150 FDrive *cur_drv; 1151 cur_drv = get_cur_drv(fdctrl); 1152 1153 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD); 1154 fdctrl->status0 |= GET_CUR_DRV(fdctrl); 1155 if (cur_drv->head) { 1156 fdctrl->status0 |= FD_SR0_HEAD; 1157 } 1158 fdctrl->status0 |= status0; 1159 1160 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", 1161 status0, status1, status2, fdctrl->status0); 1162 fdctrl->fifo[0] = fdctrl->status0; 1163 fdctrl->fifo[1] = status1; 1164 fdctrl->fifo[2] = status2; 1165 fdctrl->fifo[3] = cur_drv->track; 1166 fdctrl->fifo[4] = cur_drv->head; 1167 fdctrl->fifo[5] = cur_drv->sect; 1168 fdctrl->fifo[6] = FD_SECTOR_SC; 1169 fdctrl->data_dir = FD_DIR_READ; 1170 if (!(fdctrl->msr & FD_MSR_NONDMA)) { 1171 DMA_release_DREQ(fdctrl->dma_chann); 1172 } 1173 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 1174 fdctrl->msr &= ~FD_MSR_NONDMA; 1175 1176 fdctrl_set_fifo(fdctrl, 7); 1177 fdctrl_raise_irq(fdctrl); 1178 } 1179 1180 /* Prepare a data transfer (either DMA or FIFO) */ 1181 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) 1182 { 1183 FDrive *cur_drv; 1184 uint8_t kh, kt, ks; 1185 1186 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1187 cur_drv = get_cur_drv(fdctrl); 1188 kt = fdctrl->fifo[2]; 1189 kh = fdctrl->fifo[3]; 1190 ks = fdctrl->fifo[4]; 1191 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", 1192 GET_CUR_DRV(fdctrl), kh, kt, ks, 1193 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1194 NUM_SIDES(cur_drv))); 1195 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1196 case 2: 1197 /* sect too big */ 1198 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1199 fdctrl->fifo[3] = kt; 1200 fdctrl->fifo[4] = kh; 1201 fdctrl->fifo[5] = ks; 1202 return; 1203 case 3: 1204 /* track too big */ 1205 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1206 fdctrl->fifo[3] = kt; 1207 fdctrl->fifo[4] = kh; 1208 fdctrl->fifo[5] = ks; 1209 return; 1210 case 4: 1211 /* No seek enabled */ 1212 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1213 fdctrl->fifo[3] = kt; 1214 fdctrl->fifo[4] = kh; 1215 fdctrl->fifo[5] = ks; 1216 return; 1217 case 1: 1218 fdctrl->status0 |= FD_SR0_SEEK; 1219 break; 1220 default: 1221 break; 1222 } 1223 1224 /* Check the data rate. If the programmed data rate does not match 1225 * the currently inserted medium, the operation has to fail. */ 1226 if (fdctrl->check_media_rate && 1227 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 1228 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n", 1229 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 1230 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 1231 fdctrl->fifo[3] = kt; 1232 fdctrl->fifo[4] = kh; 1233 fdctrl->fifo[5] = ks; 1234 return; 1235 } 1236 1237 /* Set the FIFO state */ 1238 fdctrl->data_dir = direction; 1239 fdctrl->data_pos = 0; 1240 assert(fdctrl->msr & FD_MSR_CMDBUSY); 1241 if (fdctrl->fifo[0] & 0x80) 1242 fdctrl->data_state |= FD_STATE_MULTI; 1243 else 1244 fdctrl->data_state &= ~FD_STATE_MULTI; 1245 if (fdctrl->fifo[5] == 0) { 1246 fdctrl->data_len = fdctrl->fifo[8]; 1247 } else { 1248 int tmp; 1249 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); 1250 tmp = (fdctrl->fifo[6] - ks + 1); 1251 if (fdctrl->fifo[0] & 0x80) 1252 tmp += fdctrl->fifo[6]; 1253 fdctrl->data_len *= tmp; 1254 } 1255 fdctrl->eot = fdctrl->fifo[6]; 1256 if (fdctrl->dor & FD_DOR_DMAEN) { 1257 int dma_mode; 1258 /* DMA transfer are enabled. Check if DMA channel is well programmed */ 1259 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); 1260 dma_mode = (dma_mode >> 2) & 3; 1261 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", 1262 dma_mode, direction, 1263 (128 << fdctrl->fifo[5]) * 1264 (cur_drv->last_sect - ks + 1), fdctrl->data_len); 1265 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL || 1266 direction == FD_DIR_SCANH) && dma_mode == 0) || 1267 (direction == FD_DIR_WRITE && dma_mode == 2) || 1268 (direction == FD_DIR_READ && dma_mode == 1) || 1269 (direction == FD_DIR_VERIFY)) { 1270 /* No access is allowed until DMA transfer has completed */ 1271 fdctrl->msr &= ~FD_MSR_RQM; 1272 if (direction != FD_DIR_VERIFY) { 1273 /* Now, we just have to wait for the DMA controller to 1274 * recall us... 1275 */ 1276 DMA_hold_DREQ(fdctrl->dma_chann); 1277 DMA_schedule(fdctrl->dma_chann); 1278 } else { 1279 /* Start transfer */ 1280 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, 1281 fdctrl->data_len); 1282 } 1283 return; 1284 } else { 1285 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode, 1286 direction); 1287 } 1288 } 1289 FLOPPY_DPRINTF("start non-DMA transfer\n"); 1290 fdctrl->msr |= FD_MSR_NONDMA; 1291 if (direction != FD_DIR_WRITE) 1292 fdctrl->msr |= FD_MSR_DIO; 1293 /* IO based transfer: calculate len */ 1294 fdctrl_raise_irq(fdctrl); 1295 } 1296 1297 /* Prepare a transfer of deleted data */ 1298 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) 1299 { 1300 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n"); 1301 1302 /* We don't handle deleted data, 1303 * so we don't return *ANYTHING* 1304 */ 1305 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1306 } 1307 1308 /* handlers for DMA transfers */ 1309 static int fdctrl_transfer_handler (void *opaque, int nchan, 1310 int dma_pos, int dma_len) 1311 { 1312 FDCtrl *fdctrl; 1313 FDrive *cur_drv; 1314 int len, start_pos, rel_pos; 1315 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; 1316 1317 fdctrl = opaque; 1318 if (fdctrl->msr & FD_MSR_RQM) { 1319 FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); 1320 return 0; 1321 } 1322 cur_drv = get_cur_drv(fdctrl); 1323 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || 1324 fdctrl->data_dir == FD_DIR_SCANH) 1325 status2 = FD_SR2_SNS; 1326 if (dma_len > fdctrl->data_len) 1327 dma_len = fdctrl->data_len; 1328 if (cur_drv->bs == NULL) { 1329 if (fdctrl->data_dir == FD_DIR_WRITE) 1330 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1331 else 1332 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1333 len = 0; 1334 goto transfer_error; 1335 } 1336 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1337 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { 1338 len = dma_len - fdctrl->data_pos; 1339 if (len + rel_pos > FD_SECTOR_LEN) 1340 len = FD_SECTOR_LEN - rel_pos; 1341 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " 1342 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, 1343 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, 1344 cur_drv->track, cur_drv->sect, fd_sector(cur_drv), 1345 fd_sector(cur_drv) * FD_SECTOR_LEN); 1346 if (fdctrl->data_dir != FD_DIR_WRITE || 1347 len < FD_SECTOR_LEN || rel_pos != 0) { 1348 /* READ & SCAN commands and realign to a sector for WRITE */ 1349 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), 1350 fdctrl->fifo, 1) < 0) { 1351 FLOPPY_DPRINTF("Floppy: error getting sector %d\n", 1352 fd_sector(cur_drv)); 1353 /* Sure, image size is too small... */ 1354 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1355 } 1356 } 1357 switch (fdctrl->data_dir) { 1358 case FD_DIR_READ: 1359 /* READ commands */ 1360 DMA_write_memory (nchan, fdctrl->fifo + rel_pos, 1361 fdctrl->data_pos, len); 1362 break; 1363 case FD_DIR_WRITE: 1364 /* WRITE commands */ 1365 if (cur_drv->ro) { 1366 /* Handle readonly medium early, no need to do DMA, touch the 1367 * LED or attempt any writes. A real floppy doesn't attempt 1368 * to write to readonly media either. */ 1369 fdctrl_stop_transfer(fdctrl, 1370 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, 1371 0x00); 1372 goto transfer_error; 1373 } 1374 1375 DMA_read_memory (nchan, fdctrl->fifo + rel_pos, 1376 fdctrl->data_pos, len); 1377 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), 1378 fdctrl->fifo, 1) < 0) { 1379 FLOPPY_DPRINTF("error writing sector %d\n", 1380 fd_sector(cur_drv)); 1381 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1382 goto transfer_error; 1383 } 1384 break; 1385 case FD_DIR_VERIFY: 1386 /* VERIFY commands */ 1387 break; 1388 default: 1389 /* SCAN commands */ 1390 { 1391 uint8_t tmpbuf[FD_SECTOR_LEN]; 1392 int ret; 1393 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); 1394 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); 1395 if (ret == 0) { 1396 status2 = FD_SR2_SEH; 1397 goto end_transfer; 1398 } 1399 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || 1400 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { 1401 status2 = 0x00; 1402 goto end_transfer; 1403 } 1404 } 1405 break; 1406 } 1407 fdctrl->data_pos += len; 1408 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1409 if (rel_pos == 0) { 1410 /* Seek to next sector */ 1411 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) 1412 break; 1413 } 1414 } 1415 end_transfer: 1416 len = fdctrl->data_pos - start_pos; 1417 FLOPPY_DPRINTF("end transfer %d %d %d\n", 1418 fdctrl->data_pos, len, fdctrl->data_len); 1419 if (fdctrl->data_dir == FD_DIR_SCANE || 1420 fdctrl->data_dir == FD_DIR_SCANL || 1421 fdctrl->data_dir == FD_DIR_SCANH) 1422 status2 = FD_SR2_SEH; 1423 fdctrl->data_len -= len; 1424 fdctrl_stop_transfer(fdctrl, status0, status1, status2); 1425 transfer_error: 1426 1427 return len; 1428 } 1429 1430 /* Data register : 0x05 */ 1431 static uint32_t fdctrl_read_data(FDCtrl *fdctrl) 1432 { 1433 FDrive *cur_drv; 1434 uint32_t retval = 0; 1435 int pos; 1436 1437 cur_drv = get_cur_drv(fdctrl); 1438 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1439 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { 1440 FLOPPY_DPRINTF("error: controller not ready for reading\n"); 1441 return 0; 1442 } 1443 pos = fdctrl->data_pos; 1444 if (fdctrl->msr & FD_MSR_NONDMA) { 1445 pos %= FD_SECTOR_LEN; 1446 if (pos == 0) { 1447 if (fdctrl->data_pos != 0) 1448 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1449 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1450 fd_sector(cur_drv)); 1451 return 0; 1452 } 1453 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1454 FLOPPY_DPRINTF("error getting sector %d\n", 1455 fd_sector(cur_drv)); 1456 /* Sure, image size is too small... */ 1457 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1458 } 1459 } 1460 } 1461 retval = fdctrl->fifo[pos]; 1462 if (++fdctrl->data_pos == fdctrl->data_len) { 1463 fdctrl->data_pos = 0; 1464 /* Switch from transfer mode to status mode 1465 * then from status mode to command mode 1466 */ 1467 if (fdctrl->msr & FD_MSR_NONDMA) { 1468 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1469 } else { 1470 fdctrl_reset_fifo(fdctrl); 1471 fdctrl_reset_irq(fdctrl); 1472 } 1473 } 1474 FLOPPY_DPRINTF("data register: 0x%02x\n", retval); 1475 1476 return retval; 1477 } 1478 1479 static void fdctrl_format_sector(FDCtrl *fdctrl) 1480 { 1481 FDrive *cur_drv; 1482 uint8_t kh, kt, ks; 1483 1484 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1485 cur_drv = get_cur_drv(fdctrl); 1486 kt = fdctrl->fifo[6]; 1487 kh = fdctrl->fifo[7]; 1488 ks = fdctrl->fifo[8]; 1489 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", 1490 GET_CUR_DRV(fdctrl), kh, kt, ks, 1491 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1492 NUM_SIDES(cur_drv))); 1493 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1494 case 2: 1495 /* sect too big */ 1496 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1497 fdctrl->fifo[3] = kt; 1498 fdctrl->fifo[4] = kh; 1499 fdctrl->fifo[5] = ks; 1500 return; 1501 case 3: 1502 /* track too big */ 1503 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1504 fdctrl->fifo[3] = kt; 1505 fdctrl->fifo[4] = kh; 1506 fdctrl->fifo[5] = ks; 1507 return; 1508 case 4: 1509 /* No seek enabled */ 1510 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1511 fdctrl->fifo[3] = kt; 1512 fdctrl->fifo[4] = kh; 1513 fdctrl->fifo[5] = ks; 1514 return; 1515 case 1: 1516 fdctrl->status0 |= FD_SR0_SEEK; 1517 break; 1518 default: 1519 break; 1520 } 1521 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1522 if (cur_drv->bs == NULL || 1523 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1524 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv)); 1525 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1526 } else { 1527 if (cur_drv->sect == cur_drv->last_sect) { 1528 fdctrl->data_state &= ~FD_STATE_FORMAT; 1529 /* Last sector done */ 1530 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1531 } else { 1532 /* More to do */ 1533 fdctrl->data_pos = 0; 1534 fdctrl->data_len = 4; 1535 } 1536 } 1537 } 1538 1539 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) 1540 { 1541 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; 1542 fdctrl->fifo[0] = fdctrl->lock << 4; 1543 fdctrl_set_fifo(fdctrl, 1); 1544 } 1545 1546 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) 1547 { 1548 FDrive *cur_drv = get_cur_drv(fdctrl); 1549 1550 /* Drives position */ 1551 fdctrl->fifo[0] = drv0(fdctrl)->track; 1552 fdctrl->fifo[1] = drv1(fdctrl)->track; 1553 #if MAX_FD == 4 1554 fdctrl->fifo[2] = drv2(fdctrl)->track; 1555 fdctrl->fifo[3] = drv3(fdctrl)->track; 1556 #else 1557 fdctrl->fifo[2] = 0; 1558 fdctrl->fifo[3] = 0; 1559 #endif 1560 /* timers */ 1561 fdctrl->fifo[4] = fdctrl->timer0; 1562 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); 1563 fdctrl->fifo[6] = cur_drv->last_sect; 1564 fdctrl->fifo[7] = (fdctrl->lock << 7) | 1565 (cur_drv->perpendicular << 2); 1566 fdctrl->fifo[8] = fdctrl->config; 1567 fdctrl->fifo[9] = fdctrl->precomp_trk; 1568 fdctrl_set_fifo(fdctrl, 10); 1569 } 1570 1571 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) 1572 { 1573 /* Controller's version */ 1574 fdctrl->fifo[0] = fdctrl->version; 1575 fdctrl_set_fifo(fdctrl, 1); 1576 } 1577 1578 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) 1579 { 1580 fdctrl->fifo[0] = 0x41; /* Stepping 1 */ 1581 fdctrl_set_fifo(fdctrl, 1); 1582 } 1583 1584 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) 1585 { 1586 FDrive *cur_drv = get_cur_drv(fdctrl); 1587 1588 /* Drives position */ 1589 drv0(fdctrl)->track = fdctrl->fifo[3]; 1590 drv1(fdctrl)->track = fdctrl->fifo[4]; 1591 #if MAX_FD == 4 1592 drv2(fdctrl)->track = fdctrl->fifo[5]; 1593 drv3(fdctrl)->track = fdctrl->fifo[6]; 1594 #endif 1595 /* timers */ 1596 fdctrl->timer0 = fdctrl->fifo[7]; 1597 fdctrl->timer1 = fdctrl->fifo[8]; 1598 cur_drv->last_sect = fdctrl->fifo[9]; 1599 fdctrl->lock = fdctrl->fifo[10] >> 7; 1600 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; 1601 fdctrl->config = fdctrl->fifo[11]; 1602 fdctrl->precomp_trk = fdctrl->fifo[12]; 1603 fdctrl->pwrd = fdctrl->fifo[13]; 1604 fdctrl_reset_fifo(fdctrl); 1605 } 1606 1607 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) 1608 { 1609 FDrive *cur_drv = get_cur_drv(fdctrl); 1610 1611 fdctrl->fifo[0] = 0; 1612 fdctrl->fifo[1] = 0; 1613 /* Drives position */ 1614 fdctrl->fifo[2] = drv0(fdctrl)->track; 1615 fdctrl->fifo[3] = drv1(fdctrl)->track; 1616 #if MAX_FD == 4 1617 fdctrl->fifo[4] = drv2(fdctrl)->track; 1618 fdctrl->fifo[5] = drv3(fdctrl)->track; 1619 #else 1620 fdctrl->fifo[4] = 0; 1621 fdctrl->fifo[5] = 0; 1622 #endif 1623 /* timers */ 1624 fdctrl->fifo[6] = fdctrl->timer0; 1625 fdctrl->fifo[7] = fdctrl->timer1; 1626 fdctrl->fifo[8] = cur_drv->last_sect; 1627 fdctrl->fifo[9] = (fdctrl->lock << 7) | 1628 (cur_drv->perpendicular << 2); 1629 fdctrl->fifo[10] = fdctrl->config; 1630 fdctrl->fifo[11] = fdctrl->precomp_trk; 1631 fdctrl->fifo[12] = fdctrl->pwrd; 1632 fdctrl->fifo[13] = 0; 1633 fdctrl->fifo[14] = 0; 1634 fdctrl_set_fifo(fdctrl, 15); 1635 } 1636 1637 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) 1638 { 1639 FDrive *cur_drv = get_cur_drv(fdctrl); 1640 1641 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1642 qemu_mod_timer(fdctrl->result_timer, 1643 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50)); 1644 } 1645 1646 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) 1647 { 1648 FDrive *cur_drv; 1649 1650 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1651 cur_drv = get_cur_drv(fdctrl); 1652 fdctrl->data_state |= FD_STATE_FORMAT; 1653 if (fdctrl->fifo[0] & 0x80) 1654 fdctrl->data_state |= FD_STATE_MULTI; 1655 else 1656 fdctrl->data_state &= ~FD_STATE_MULTI; 1657 cur_drv->bps = 1658 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; 1659 #if 0 1660 cur_drv->last_sect = 1661 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : 1662 fdctrl->fifo[3] / 2; 1663 #else 1664 cur_drv->last_sect = fdctrl->fifo[3]; 1665 #endif 1666 /* TODO: implement format using DMA expected by the Bochs BIOS 1667 * and Linux fdformat (read 3 bytes per sector via DMA and fill 1668 * the sector with the specified fill byte 1669 */ 1670 fdctrl->data_state &= ~FD_STATE_FORMAT; 1671 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1672 } 1673 1674 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) 1675 { 1676 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; 1677 fdctrl->timer1 = fdctrl->fifo[2] >> 1; 1678 if (fdctrl->fifo[2] & 1) 1679 fdctrl->dor &= ~FD_DOR_DMAEN; 1680 else 1681 fdctrl->dor |= FD_DOR_DMAEN; 1682 /* No result back */ 1683 fdctrl_reset_fifo(fdctrl); 1684 } 1685 1686 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) 1687 { 1688 FDrive *cur_drv; 1689 1690 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1691 cur_drv = get_cur_drv(fdctrl); 1692 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1693 /* 1 Byte status back */ 1694 fdctrl->fifo[0] = (cur_drv->ro << 6) | 1695 (cur_drv->track == 0 ? 0x10 : 0x00) | 1696 (cur_drv->head << 2) | 1697 GET_CUR_DRV(fdctrl) | 1698 0x28; 1699 fdctrl_set_fifo(fdctrl, 1); 1700 } 1701 1702 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) 1703 { 1704 FDrive *cur_drv; 1705 1706 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1707 cur_drv = get_cur_drv(fdctrl); 1708 fd_recalibrate(cur_drv); 1709 fdctrl_reset_fifo(fdctrl); 1710 /* Raise Interrupt */ 1711 fdctrl->status0 |= FD_SR0_SEEK; 1712 fdctrl_raise_irq(fdctrl); 1713 } 1714 1715 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) 1716 { 1717 FDrive *cur_drv = get_cur_drv(fdctrl); 1718 1719 if (fdctrl->reset_sensei > 0) { 1720 fdctrl->fifo[0] = 1721 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; 1722 fdctrl->reset_sensei--; 1723 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) { 1724 fdctrl->fifo[0] = FD_SR0_INVCMD; 1725 fdctrl_set_fifo(fdctrl, 1); 1726 return; 1727 } else { 1728 fdctrl->fifo[0] = 1729 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0)) 1730 | GET_CUR_DRV(fdctrl); 1731 } 1732 1733 fdctrl->fifo[1] = cur_drv->track; 1734 fdctrl_set_fifo(fdctrl, 2); 1735 fdctrl_reset_irq(fdctrl); 1736 fdctrl->status0 = FD_SR0_RDYCHG; 1737 } 1738 1739 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) 1740 { 1741 FDrive *cur_drv; 1742 1743 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1744 cur_drv = get_cur_drv(fdctrl); 1745 fdctrl_reset_fifo(fdctrl); 1746 /* The seek command just sends step pulses to the drive and doesn't care if 1747 * there is a medium inserted of if it's banging the head against the drive. 1748 */ 1749 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1); 1750 /* Raise Interrupt */ 1751 fdctrl->status0 |= FD_SR0_SEEK; 1752 fdctrl_raise_irq(fdctrl); 1753 } 1754 1755 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) 1756 { 1757 FDrive *cur_drv = get_cur_drv(fdctrl); 1758 1759 if (fdctrl->fifo[1] & 0x80) 1760 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; 1761 /* No result back */ 1762 fdctrl_reset_fifo(fdctrl); 1763 } 1764 1765 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) 1766 { 1767 fdctrl->config = fdctrl->fifo[2]; 1768 fdctrl->precomp_trk = fdctrl->fifo[3]; 1769 /* No result back */ 1770 fdctrl_reset_fifo(fdctrl); 1771 } 1772 1773 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) 1774 { 1775 fdctrl->pwrd = fdctrl->fifo[1]; 1776 fdctrl->fifo[0] = fdctrl->fifo[1]; 1777 fdctrl_set_fifo(fdctrl, 1); 1778 } 1779 1780 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) 1781 { 1782 /* No result back */ 1783 fdctrl_reset_fifo(fdctrl); 1784 } 1785 1786 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) 1787 { 1788 FDrive *cur_drv = get_cur_drv(fdctrl); 1789 1790 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { 1791 /* Command parameters done */ 1792 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) { 1793 fdctrl->fifo[0] = fdctrl->fifo[1]; 1794 fdctrl->fifo[2] = 0; 1795 fdctrl->fifo[3] = 0; 1796 fdctrl_set_fifo(fdctrl, 4); 1797 } else { 1798 fdctrl_reset_fifo(fdctrl); 1799 } 1800 } else if (fdctrl->data_len > 7) { 1801 /* ERROR */ 1802 fdctrl->fifo[0] = 0x80 | 1803 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); 1804 fdctrl_set_fifo(fdctrl, 1); 1805 } 1806 } 1807 1808 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) 1809 { 1810 FDrive *cur_drv; 1811 1812 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1813 cur_drv = get_cur_drv(fdctrl); 1814 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { 1815 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1, 1816 cur_drv->sect, 1); 1817 } else { 1818 fd_seek(cur_drv, cur_drv->head, 1819 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1); 1820 } 1821 fdctrl_reset_fifo(fdctrl); 1822 /* Raise Interrupt */ 1823 fdctrl->status0 |= FD_SR0_SEEK; 1824 fdctrl_raise_irq(fdctrl); 1825 } 1826 1827 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) 1828 { 1829 FDrive *cur_drv; 1830 1831 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1832 cur_drv = get_cur_drv(fdctrl); 1833 if (fdctrl->fifo[2] > cur_drv->track) { 1834 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1); 1835 } else { 1836 fd_seek(cur_drv, cur_drv->head, 1837 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1); 1838 } 1839 fdctrl_reset_fifo(fdctrl); 1840 /* Raise Interrupt */ 1841 fdctrl->status0 |= FD_SR0_SEEK; 1842 fdctrl_raise_irq(fdctrl); 1843 } 1844 1845 static const struct { 1846 uint8_t value; 1847 uint8_t mask; 1848 const char* name; 1849 int parameters; 1850 void (*handler)(FDCtrl *fdctrl, int direction); 1851 int direction; 1852 } handlers[] = { 1853 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, 1854 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, 1855 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, 1856 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, 1857 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, 1858 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, 1859 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, 1860 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ 1861 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ 1862 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, 1863 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, 1864 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY }, 1865 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, 1866 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, 1867 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, 1868 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, 1869 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, 1870 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, 1871 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, 1872 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, 1873 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, 1874 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, 1875 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, 1876 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, 1877 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, 1878 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, 1879 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, 1880 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, 1881 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, 1882 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, 1883 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ 1884 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ 1885 }; 1886 /* Associate command to an index in the 'handlers' array */ 1887 static uint8_t command_to_handler[256]; 1888 1889 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) 1890 { 1891 FDrive *cur_drv; 1892 int pos; 1893 1894 /* Reset mode */ 1895 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1896 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1897 return; 1898 } 1899 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { 1900 FLOPPY_DPRINTF("error: controller not ready for writing\n"); 1901 return; 1902 } 1903 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1904 /* Is it write command time ? */ 1905 if (fdctrl->msr & FD_MSR_NONDMA) { 1906 /* FIFO data write */ 1907 pos = fdctrl->data_pos++; 1908 pos %= FD_SECTOR_LEN; 1909 fdctrl->fifo[pos] = value; 1910 if (pos == FD_SECTOR_LEN - 1 || 1911 fdctrl->data_pos == fdctrl->data_len) { 1912 cur_drv = get_cur_drv(fdctrl); 1913 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1914 FLOPPY_DPRINTF("error writing sector %d\n", 1915 fd_sector(cur_drv)); 1916 return; 1917 } 1918 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1919 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1920 fd_sector(cur_drv)); 1921 return; 1922 } 1923 } 1924 /* Switch from transfer mode to status mode 1925 * then from status mode to command mode 1926 */ 1927 if (fdctrl->data_pos == fdctrl->data_len) 1928 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1929 return; 1930 } 1931 if (fdctrl->data_pos == 0) { 1932 /* Command */ 1933 pos = command_to_handler[value & 0xff]; 1934 FLOPPY_DPRINTF("%s command\n", handlers[pos].name); 1935 fdctrl->data_len = handlers[pos].parameters + 1; 1936 fdctrl->msr |= FD_MSR_CMDBUSY; 1937 } 1938 1939 FLOPPY_DPRINTF("%s: %02x\n", __func__, value); 1940 fdctrl->fifo[fdctrl->data_pos++] = value; 1941 if (fdctrl->data_pos == fdctrl->data_len) { 1942 /* We now have all parameters 1943 * and will be able to treat the command 1944 */ 1945 if (fdctrl->data_state & FD_STATE_FORMAT) { 1946 fdctrl_format_sector(fdctrl); 1947 return; 1948 } 1949 1950 pos = command_to_handler[fdctrl->fifo[0] & 0xff]; 1951 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name); 1952 (*handlers[pos].handler)(fdctrl, handlers[pos].direction); 1953 } 1954 } 1955 1956 static void fdctrl_result_timer(void *opaque) 1957 { 1958 FDCtrl *fdctrl = opaque; 1959 FDrive *cur_drv = get_cur_drv(fdctrl); 1960 1961 /* Pretend we are spinning. 1962 * This is needed for Coherent, which uses READ ID to check for 1963 * sector interleaving. 1964 */ 1965 if (cur_drv->last_sect != 0) { 1966 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; 1967 } 1968 /* READ_ID can't automatically succeed! */ 1969 if (fdctrl->check_media_rate && 1970 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 1971 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n", 1972 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 1973 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 1974 } else { 1975 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1976 } 1977 } 1978 1979 static void fdctrl_change_cb(void *opaque, bool load) 1980 { 1981 FDrive *drive = opaque; 1982 1983 drive->media_changed = 1; 1984 fd_revalidate(drive); 1985 } 1986 1987 static const BlockDevOps fdctrl_block_ops = { 1988 .change_media_cb = fdctrl_change_cb, 1989 }; 1990 1991 /* Init functions */ 1992 static int fdctrl_connect_drives(FDCtrl *fdctrl) 1993 { 1994 unsigned int i; 1995 FDrive *drive; 1996 1997 for (i = 0; i < MAX_FD; i++) { 1998 drive = &fdctrl->drives[i]; 1999 drive->fdctrl = fdctrl; 2000 2001 if (drive->bs) { 2002 if (bdrv_get_on_error(drive->bs, 0) != BLOCKDEV_ON_ERROR_ENOSPC) { 2003 error_report("fdc doesn't support drive option werror"); 2004 return -1; 2005 } 2006 if (bdrv_get_on_error(drive->bs, 1) != BLOCKDEV_ON_ERROR_REPORT) { 2007 error_report("fdc doesn't support drive option rerror"); 2008 return -1; 2009 } 2010 } 2011 2012 fd_init(drive); 2013 fdctrl_change_cb(drive, 0); 2014 if (drive->bs) { 2015 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive); 2016 } 2017 } 2018 return 0; 2019 } 2020 2021 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds) 2022 { 2023 ISADevice *dev; 2024 2025 dev = isa_try_create(bus, "isa-fdc"); 2026 if (!dev) { 2027 return NULL; 2028 } 2029 2030 if (fds[0]) { 2031 qdev_prop_set_drive_nofail(&dev->qdev, "driveA", fds[0]->bdrv); 2032 } 2033 if (fds[1]) { 2034 qdev_prop_set_drive_nofail(&dev->qdev, "driveB", fds[1]->bdrv); 2035 } 2036 qdev_init_nofail(&dev->qdev); 2037 2038 return dev; 2039 } 2040 2041 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, 2042 hwaddr mmio_base, DriveInfo **fds) 2043 { 2044 FDCtrl *fdctrl; 2045 DeviceState *dev; 2046 FDCtrlSysBus *sys; 2047 2048 dev = qdev_create(NULL, "sysbus-fdc"); 2049 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev); 2050 fdctrl = &sys->state; 2051 fdctrl->dma_chann = dma_chann; /* FIXME */ 2052 if (fds[0]) { 2053 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv); 2054 } 2055 if (fds[1]) { 2056 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv); 2057 } 2058 qdev_init_nofail(dev); 2059 sysbus_connect_irq(&sys->busdev, 0, irq); 2060 sysbus_mmio_map(&sys->busdev, 0, mmio_base); 2061 } 2062 2063 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, 2064 DriveInfo **fds, qemu_irq *fdc_tc) 2065 { 2066 DeviceState *dev; 2067 FDCtrlSysBus *sys; 2068 2069 dev = qdev_create(NULL, "SUNW,fdtwo"); 2070 if (fds[0]) { 2071 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv); 2072 } 2073 qdev_init_nofail(dev); 2074 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev); 2075 sysbus_connect_irq(&sys->busdev, 0, irq); 2076 sysbus_mmio_map(&sys->busdev, 0, io_base); 2077 *fdc_tc = qdev_get_gpio_in(dev, 0); 2078 } 2079 2080 static int fdctrl_init_common(FDCtrl *fdctrl) 2081 { 2082 int i, j; 2083 static int command_tables_inited = 0; 2084 2085 /* Fill 'command_to_handler' lookup table */ 2086 if (!command_tables_inited) { 2087 command_tables_inited = 1; 2088 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { 2089 for (j = 0; j < sizeof(command_to_handler); j++) { 2090 if ((j & handlers[i].mask) == handlers[i].value) { 2091 command_to_handler[j] = i; 2092 } 2093 } 2094 } 2095 } 2096 2097 FLOPPY_DPRINTF("init controller\n"); 2098 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); 2099 fdctrl->fifo_size = 512; 2100 fdctrl->result_timer = qemu_new_timer_ns(vm_clock, 2101 fdctrl_result_timer, fdctrl); 2102 2103 fdctrl->version = 0x90; /* Intel 82078 controller */ 2104 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ 2105 fdctrl->num_floppies = MAX_FD; 2106 2107 if (fdctrl->dma_chann != -1) 2108 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl); 2109 return fdctrl_connect_drives(fdctrl); 2110 } 2111 2112 static const MemoryRegionPortio fdc_portio_list[] = { 2113 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, 2114 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, 2115 PORTIO_END_OF_LIST(), 2116 }; 2117 2118 static int isabus_fdc_init1(ISADevice *dev) 2119 { 2120 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev); 2121 FDCtrl *fdctrl = &isa->state; 2122 int ret; 2123 2124 isa_register_portio_list(dev, isa->iobase, fdc_portio_list, fdctrl, "fdc"); 2125 2126 isa_init_irq(&isa->busdev, &fdctrl->irq, isa->irq); 2127 fdctrl->dma_chann = isa->dma; 2128 2129 qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 2); 2130 ret = fdctrl_init_common(fdctrl); 2131 2132 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0"); 2133 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1"); 2134 2135 return ret; 2136 } 2137 2138 static int sysbus_fdc_init1(SysBusDevice *dev) 2139 { 2140 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev); 2141 FDCtrl *fdctrl = &sys->state; 2142 int ret; 2143 2144 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08); 2145 sysbus_init_mmio(dev, &fdctrl->iomem); 2146 sysbus_init_irq(dev, &fdctrl->irq); 2147 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1); 2148 fdctrl->dma_chann = -1; 2149 2150 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */ 2151 ret = fdctrl_init_common(fdctrl); 2152 2153 return ret; 2154 } 2155 2156 static int sun4m_fdc_init1(SysBusDevice *dev) 2157 { 2158 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state); 2159 2160 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl, 2161 "fdctrl", 0x08); 2162 sysbus_init_mmio(dev, &fdctrl->iomem); 2163 sysbus_init_irq(dev, &fdctrl->irq); 2164 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1); 2165 2166 fdctrl->sun4m = 1; 2167 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */ 2168 return fdctrl_init_common(fdctrl); 2169 } 2170 2171 FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i) 2172 { 2173 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, fdc); 2174 2175 return isa->state.drives[i].drive; 2176 } 2177 2178 static const VMStateDescription vmstate_isa_fdc ={ 2179 .name = "fdc", 2180 .version_id = 2, 2181 .minimum_version_id = 2, 2182 .fields = (VMStateField []) { 2183 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl), 2184 VMSTATE_END_OF_LIST() 2185 } 2186 }; 2187 2188 static Property isa_fdc_properties[] = { 2189 DEFINE_PROP_HEX32("iobase", FDCtrlISABus, iobase, 0x3f0), 2190 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6), 2191 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2), 2192 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs), 2193 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs), 2194 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1), 2195 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1), 2196 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate, 2197 0, true), 2198 DEFINE_PROP_END_OF_LIST(), 2199 }; 2200 2201 static void isabus_fdc_class_init1(ObjectClass *klass, void *data) 2202 { 2203 DeviceClass *dc = DEVICE_CLASS(klass); 2204 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); 2205 ic->init = isabus_fdc_init1; 2206 dc->fw_name = "fdc"; 2207 dc->no_user = 1; 2208 dc->reset = fdctrl_external_reset_isa; 2209 dc->vmsd = &vmstate_isa_fdc; 2210 dc->props = isa_fdc_properties; 2211 } 2212 2213 static const TypeInfo isa_fdc_info = { 2214 .name = "isa-fdc", 2215 .parent = TYPE_ISA_DEVICE, 2216 .instance_size = sizeof(FDCtrlISABus), 2217 .class_init = isabus_fdc_class_init1, 2218 }; 2219 2220 static const VMStateDescription vmstate_sysbus_fdc ={ 2221 .name = "fdc", 2222 .version_id = 2, 2223 .minimum_version_id = 2, 2224 .fields = (VMStateField []) { 2225 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl), 2226 VMSTATE_END_OF_LIST() 2227 } 2228 }; 2229 2230 static Property sysbus_fdc_properties[] = { 2231 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs), 2232 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs), 2233 DEFINE_PROP_END_OF_LIST(), 2234 }; 2235 2236 static void sysbus_fdc_class_init(ObjectClass *klass, void *data) 2237 { 2238 DeviceClass *dc = DEVICE_CLASS(klass); 2239 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 2240 2241 k->init = sysbus_fdc_init1; 2242 dc->reset = fdctrl_external_reset_sysbus; 2243 dc->vmsd = &vmstate_sysbus_fdc; 2244 dc->props = sysbus_fdc_properties; 2245 } 2246 2247 static const TypeInfo sysbus_fdc_info = { 2248 .name = "sysbus-fdc", 2249 .parent = TYPE_SYS_BUS_DEVICE, 2250 .instance_size = sizeof(FDCtrlSysBus), 2251 .class_init = sysbus_fdc_class_init, 2252 }; 2253 2254 static Property sun4m_fdc_properties[] = { 2255 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs), 2256 DEFINE_PROP_END_OF_LIST(), 2257 }; 2258 2259 static void sun4m_fdc_class_init(ObjectClass *klass, void *data) 2260 { 2261 DeviceClass *dc = DEVICE_CLASS(klass); 2262 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 2263 2264 k->init = sun4m_fdc_init1; 2265 dc->reset = fdctrl_external_reset_sysbus; 2266 dc->vmsd = &vmstate_sysbus_fdc; 2267 dc->props = sun4m_fdc_properties; 2268 } 2269 2270 static const TypeInfo sun4m_fdc_info = { 2271 .name = "SUNW,fdtwo", 2272 .parent = TYPE_SYS_BUS_DEVICE, 2273 .instance_size = sizeof(FDCtrlSysBus), 2274 .class_init = sun4m_fdc_class_init, 2275 }; 2276 2277 static void fdc_register_types(void) 2278 { 2279 type_register_static(&isa_fdc_info); 2280 type_register_static(&sysbus_fdc_info); 2281 type_register_static(&sun4m_fdc_info); 2282 } 2283 2284 type_init(fdc_register_types) 2285