1 /* 2 * QEMU Floppy disk emulator (Intel 82078) 3 * 4 * Copyright (c) 2003, 2007 Jocelyn Mayer 5 * Copyright (c) 2008 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * The controller is used in Sun4m systems in a slightly different 27 * way. There are changes in DOR register and DMA is not available. 28 */ 29 30 #include "hw/hw.h" 31 #include "hw/block/fdc.h" 32 #include "qemu/error-report.h" 33 #include "qemu/timer.h" 34 #include "hw/isa/isa.h" 35 #include "hw/sysbus.h" 36 #include "sysemu/blockdev.h" 37 #include "sysemu/sysemu.h" 38 #include "qemu/log.h" 39 40 /********************************************************/ 41 /* debug Floppy devices */ 42 //#define DEBUG_FLOPPY 43 44 #ifdef DEBUG_FLOPPY 45 #define FLOPPY_DPRINTF(fmt, ...) \ 46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) 47 #else 48 #define FLOPPY_DPRINTF(fmt, ...) 49 #endif 50 51 /********************************************************/ 52 /* Floppy drive emulation */ 53 54 typedef enum FDriveRate { 55 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */ 56 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */ 57 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */ 58 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */ 59 } FDriveRate; 60 61 typedef struct FDFormat { 62 FDriveType drive; 63 uint8_t last_sect; 64 uint8_t max_track; 65 uint8_t max_head; 66 FDriveRate rate; 67 } FDFormat; 68 69 static const FDFormat fd_formats[] = { 70 /* First entry is default format */ 71 /* 1.44 MB 3"1/2 floppy disks */ 72 { FDRIVE_DRV_144, 18, 80, 1, FDRIVE_RATE_500K, }, 73 { FDRIVE_DRV_144, 20, 80, 1, FDRIVE_RATE_500K, }, 74 { FDRIVE_DRV_144, 21, 80, 1, FDRIVE_RATE_500K, }, 75 { FDRIVE_DRV_144, 21, 82, 1, FDRIVE_RATE_500K, }, 76 { FDRIVE_DRV_144, 21, 83, 1, FDRIVE_RATE_500K, }, 77 { FDRIVE_DRV_144, 22, 80, 1, FDRIVE_RATE_500K, }, 78 { FDRIVE_DRV_144, 23, 80, 1, FDRIVE_RATE_500K, }, 79 { FDRIVE_DRV_144, 24, 80, 1, FDRIVE_RATE_500K, }, 80 /* 2.88 MB 3"1/2 floppy disks */ 81 { FDRIVE_DRV_288, 36, 80, 1, FDRIVE_RATE_1M, }, 82 { FDRIVE_DRV_288, 39, 80, 1, FDRIVE_RATE_1M, }, 83 { FDRIVE_DRV_288, 40, 80, 1, FDRIVE_RATE_1M, }, 84 { FDRIVE_DRV_288, 44, 80, 1, FDRIVE_RATE_1M, }, 85 { FDRIVE_DRV_288, 48, 80, 1, FDRIVE_RATE_1M, }, 86 /* 720 kB 3"1/2 floppy disks */ 87 { FDRIVE_DRV_144, 9, 80, 1, FDRIVE_RATE_250K, }, 88 { FDRIVE_DRV_144, 10, 80, 1, FDRIVE_RATE_250K, }, 89 { FDRIVE_DRV_144, 10, 82, 1, FDRIVE_RATE_250K, }, 90 { FDRIVE_DRV_144, 10, 83, 1, FDRIVE_RATE_250K, }, 91 { FDRIVE_DRV_144, 13, 80, 1, FDRIVE_RATE_250K, }, 92 { FDRIVE_DRV_144, 14, 80, 1, FDRIVE_RATE_250K, }, 93 /* 1.2 MB 5"1/4 floppy disks */ 94 { FDRIVE_DRV_120, 15, 80, 1, FDRIVE_RATE_500K, }, 95 { FDRIVE_DRV_120, 18, 80, 1, FDRIVE_RATE_500K, }, 96 { FDRIVE_DRV_120, 18, 82, 1, FDRIVE_RATE_500K, }, 97 { FDRIVE_DRV_120, 18, 83, 1, FDRIVE_RATE_500K, }, 98 { FDRIVE_DRV_120, 20, 80, 1, FDRIVE_RATE_500K, }, 99 /* 720 kB 5"1/4 floppy disks */ 100 { FDRIVE_DRV_120, 9, 80, 1, FDRIVE_RATE_250K, }, 101 { FDRIVE_DRV_120, 11, 80, 1, FDRIVE_RATE_250K, }, 102 /* 360 kB 5"1/4 floppy disks */ 103 { FDRIVE_DRV_120, 9, 40, 1, FDRIVE_RATE_300K, }, 104 { FDRIVE_DRV_120, 9, 40, 0, FDRIVE_RATE_300K, }, 105 { FDRIVE_DRV_120, 10, 41, 1, FDRIVE_RATE_300K, }, 106 { FDRIVE_DRV_120, 10, 42, 1, FDRIVE_RATE_300K, }, 107 /* 320 kB 5"1/4 floppy disks */ 108 { FDRIVE_DRV_120, 8, 40, 1, FDRIVE_RATE_250K, }, 109 { FDRIVE_DRV_120, 8, 40, 0, FDRIVE_RATE_250K, }, 110 /* 360 kB must match 5"1/4 better than 3"1/2... */ 111 { FDRIVE_DRV_144, 9, 80, 0, FDRIVE_RATE_250K, }, 112 /* end */ 113 { FDRIVE_DRV_NONE, -1, -1, 0, 0, }, 114 }; 115 116 static void pick_geometry(BlockDriverState *bs, int *nb_heads, 117 int *max_track, int *last_sect, 118 FDriveType drive_in, FDriveType *drive, 119 FDriveRate *rate) 120 { 121 const FDFormat *parse; 122 uint64_t nb_sectors, size; 123 int i, first_match, match; 124 125 bdrv_get_geometry(bs, &nb_sectors); 126 match = -1; 127 first_match = -1; 128 for (i = 0; ; i++) { 129 parse = &fd_formats[i]; 130 if (parse->drive == FDRIVE_DRV_NONE) { 131 break; 132 } 133 if (drive_in == parse->drive || 134 drive_in == FDRIVE_DRV_NONE) { 135 size = (parse->max_head + 1) * parse->max_track * 136 parse->last_sect; 137 if (nb_sectors == size) { 138 match = i; 139 break; 140 } 141 if (first_match == -1) { 142 first_match = i; 143 } 144 } 145 } 146 if (match == -1) { 147 if (first_match == -1) { 148 match = 1; 149 } else { 150 match = first_match; 151 } 152 parse = &fd_formats[match]; 153 } 154 *nb_heads = parse->max_head + 1; 155 *max_track = parse->max_track; 156 *last_sect = parse->last_sect; 157 *drive = parse->drive; 158 *rate = parse->rate; 159 } 160 161 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) 162 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) 163 164 /* Will always be a fixed parameter for us */ 165 #define FD_SECTOR_LEN 512 166 #define FD_SECTOR_SC 2 /* Sector size code */ 167 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ 168 169 typedef struct FDCtrl FDCtrl; 170 171 /* Floppy disk drive emulation */ 172 typedef enum FDiskFlags { 173 FDISK_DBL_SIDES = 0x01, 174 } FDiskFlags; 175 176 typedef struct FDrive { 177 FDCtrl *fdctrl; 178 BlockDriverState *bs; 179 /* Drive status */ 180 FDriveType drive; 181 uint8_t perpendicular; /* 2.88 MB access mode */ 182 /* Position */ 183 uint8_t head; 184 uint8_t track; 185 uint8_t sect; 186 /* Media */ 187 FDiskFlags flags; 188 uint8_t last_sect; /* Nb sector per track */ 189 uint8_t max_track; /* Nb of tracks */ 190 uint16_t bps; /* Bytes per sector */ 191 uint8_t ro; /* Is read-only */ 192 uint8_t media_changed; /* Is media changed */ 193 uint8_t media_rate; /* Data rate of medium */ 194 } FDrive; 195 196 static void fd_init(FDrive *drv) 197 { 198 /* Drive */ 199 drv->drive = FDRIVE_DRV_NONE; 200 drv->perpendicular = 0; 201 /* Disk */ 202 drv->last_sect = 0; 203 drv->max_track = 0; 204 } 205 206 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) 207 208 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, 209 uint8_t last_sect, uint8_t num_sides) 210 { 211 return (((track * num_sides) + head) * last_sect) + sect - 1; 212 } 213 214 /* Returns current position, in sectors, for given drive */ 215 static int fd_sector(FDrive *drv) 216 { 217 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, 218 NUM_SIDES(drv)); 219 } 220 221 /* Seek to a new position: 222 * returns 0 if already on right track 223 * returns 1 if track changed 224 * returns 2 if track is invalid 225 * returns 3 if sector is invalid 226 * returns 4 if seek is disabled 227 */ 228 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, 229 int enable_seek) 230 { 231 uint32_t sector; 232 int ret; 233 234 if (track > drv->max_track || 235 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { 236 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 237 head, track, sect, 1, 238 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 239 drv->max_track, drv->last_sect); 240 return 2; 241 } 242 if (sect > drv->last_sect) { 243 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 244 head, track, sect, 1, 245 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 246 drv->max_track, drv->last_sect); 247 return 3; 248 } 249 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); 250 ret = 0; 251 if (sector != fd_sector(drv)) { 252 #if 0 253 if (!enable_seek) { 254 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x" 255 " (max=%d %02x %02x)\n", 256 head, track, sect, 1, drv->max_track, 257 drv->last_sect); 258 return 4; 259 } 260 #endif 261 drv->head = head; 262 if (drv->track != track) { 263 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) { 264 drv->media_changed = 0; 265 } 266 ret = 1; 267 } 268 drv->track = track; 269 drv->sect = sect; 270 } 271 272 if (drv->bs == NULL || !bdrv_is_inserted(drv->bs)) { 273 ret = 2; 274 } 275 276 return ret; 277 } 278 279 /* Set drive back to track 0 */ 280 static void fd_recalibrate(FDrive *drv) 281 { 282 FLOPPY_DPRINTF("recalibrate\n"); 283 fd_seek(drv, 0, 0, 1, 1); 284 } 285 286 /* Revalidate a disk drive after a disk change */ 287 static void fd_revalidate(FDrive *drv) 288 { 289 int nb_heads, max_track, last_sect, ro; 290 FDriveType drive; 291 FDriveRate rate; 292 293 FLOPPY_DPRINTF("revalidate\n"); 294 if (drv->bs != NULL) { 295 ro = bdrv_is_read_only(drv->bs); 296 pick_geometry(drv->bs, &nb_heads, &max_track, 297 &last_sect, drv->drive, &drive, &rate); 298 if (!bdrv_is_inserted(drv->bs)) { 299 FLOPPY_DPRINTF("No disk in drive\n"); 300 } else { 301 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads, 302 max_track, last_sect, ro ? "ro" : "rw"); 303 } 304 if (nb_heads == 1) { 305 drv->flags &= ~FDISK_DBL_SIDES; 306 } else { 307 drv->flags |= FDISK_DBL_SIDES; 308 } 309 drv->max_track = max_track; 310 drv->last_sect = last_sect; 311 drv->ro = ro; 312 drv->drive = drive; 313 drv->media_rate = rate; 314 } else { 315 FLOPPY_DPRINTF("No drive connected\n"); 316 drv->last_sect = 0; 317 drv->max_track = 0; 318 drv->flags &= ~FDISK_DBL_SIDES; 319 } 320 } 321 322 /********************************************************/ 323 /* Intel 82078 floppy disk controller emulation */ 324 325 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); 326 static void fdctrl_reset_fifo(FDCtrl *fdctrl); 327 static int fdctrl_transfer_handler (void *opaque, int nchan, 328 int dma_pos, int dma_len); 329 static void fdctrl_raise_irq(FDCtrl *fdctrl); 330 static FDrive *get_cur_drv(FDCtrl *fdctrl); 331 332 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); 333 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); 334 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); 335 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); 336 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); 337 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); 338 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); 339 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); 340 static uint32_t fdctrl_read_data(FDCtrl *fdctrl); 341 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); 342 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); 343 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); 344 345 enum { 346 FD_DIR_WRITE = 0, 347 FD_DIR_READ = 1, 348 FD_DIR_SCANE = 2, 349 FD_DIR_SCANL = 3, 350 FD_DIR_SCANH = 4, 351 FD_DIR_VERIFY = 5, 352 }; 353 354 enum { 355 FD_STATE_MULTI = 0x01, /* multi track flag */ 356 FD_STATE_FORMAT = 0x02, /* format flag */ 357 }; 358 359 enum { 360 FD_REG_SRA = 0x00, 361 FD_REG_SRB = 0x01, 362 FD_REG_DOR = 0x02, 363 FD_REG_TDR = 0x03, 364 FD_REG_MSR = 0x04, 365 FD_REG_DSR = 0x04, 366 FD_REG_FIFO = 0x05, 367 FD_REG_DIR = 0x07, 368 FD_REG_CCR = 0x07, 369 }; 370 371 enum { 372 FD_CMD_READ_TRACK = 0x02, 373 FD_CMD_SPECIFY = 0x03, 374 FD_CMD_SENSE_DRIVE_STATUS = 0x04, 375 FD_CMD_WRITE = 0x05, 376 FD_CMD_READ = 0x06, 377 FD_CMD_RECALIBRATE = 0x07, 378 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, 379 FD_CMD_WRITE_DELETED = 0x09, 380 FD_CMD_READ_ID = 0x0a, 381 FD_CMD_READ_DELETED = 0x0c, 382 FD_CMD_FORMAT_TRACK = 0x0d, 383 FD_CMD_DUMPREG = 0x0e, 384 FD_CMD_SEEK = 0x0f, 385 FD_CMD_VERSION = 0x10, 386 FD_CMD_SCAN_EQUAL = 0x11, 387 FD_CMD_PERPENDICULAR_MODE = 0x12, 388 FD_CMD_CONFIGURE = 0x13, 389 FD_CMD_LOCK = 0x14, 390 FD_CMD_VERIFY = 0x16, 391 FD_CMD_POWERDOWN_MODE = 0x17, 392 FD_CMD_PART_ID = 0x18, 393 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, 394 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, 395 FD_CMD_SAVE = 0x2e, 396 FD_CMD_OPTION = 0x33, 397 FD_CMD_RESTORE = 0x4e, 398 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, 399 FD_CMD_RELATIVE_SEEK_OUT = 0x8f, 400 FD_CMD_FORMAT_AND_WRITE = 0xcd, 401 FD_CMD_RELATIVE_SEEK_IN = 0xcf, 402 }; 403 404 enum { 405 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ 406 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ 407 FD_CONFIG_POLL = 0x10, /* Poll enabled */ 408 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ 409 FD_CONFIG_EIS = 0x40, /* No implied seeks */ 410 }; 411 412 enum { 413 FD_SR0_DS0 = 0x01, 414 FD_SR0_DS1 = 0x02, 415 FD_SR0_HEAD = 0x04, 416 FD_SR0_EQPMT = 0x10, 417 FD_SR0_SEEK = 0x20, 418 FD_SR0_ABNTERM = 0x40, 419 FD_SR0_INVCMD = 0x80, 420 FD_SR0_RDYCHG = 0xc0, 421 }; 422 423 enum { 424 FD_SR1_MA = 0x01, /* Missing address mark */ 425 FD_SR1_NW = 0x02, /* Not writable */ 426 FD_SR1_EC = 0x80, /* End of cylinder */ 427 }; 428 429 enum { 430 FD_SR2_SNS = 0x04, /* Scan not satisfied */ 431 FD_SR2_SEH = 0x08, /* Scan equal hit */ 432 }; 433 434 enum { 435 FD_SRA_DIR = 0x01, 436 FD_SRA_nWP = 0x02, 437 FD_SRA_nINDX = 0x04, 438 FD_SRA_HDSEL = 0x08, 439 FD_SRA_nTRK0 = 0x10, 440 FD_SRA_STEP = 0x20, 441 FD_SRA_nDRV2 = 0x40, 442 FD_SRA_INTPEND = 0x80, 443 }; 444 445 enum { 446 FD_SRB_MTR0 = 0x01, 447 FD_SRB_MTR1 = 0x02, 448 FD_SRB_WGATE = 0x04, 449 FD_SRB_RDATA = 0x08, 450 FD_SRB_WDATA = 0x10, 451 FD_SRB_DR0 = 0x20, 452 }; 453 454 enum { 455 #if MAX_FD == 4 456 FD_DOR_SELMASK = 0x03, 457 #else 458 FD_DOR_SELMASK = 0x01, 459 #endif 460 FD_DOR_nRESET = 0x04, 461 FD_DOR_DMAEN = 0x08, 462 FD_DOR_MOTEN0 = 0x10, 463 FD_DOR_MOTEN1 = 0x20, 464 FD_DOR_MOTEN2 = 0x40, 465 FD_DOR_MOTEN3 = 0x80, 466 }; 467 468 enum { 469 #if MAX_FD == 4 470 FD_TDR_BOOTSEL = 0x0c, 471 #else 472 FD_TDR_BOOTSEL = 0x04, 473 #endif 474 }; 475 476 enum { 477 FD_DSR_DRATEMASK= 0x03, 478 FD_DSR_PWRDOWN = 0x40, 479 FD_DSR_SWRESET = 0x80, 480 }; 481 482 enum { 483 FD_MSR_DRV0BUSY = 0x01, 484 FD_MSR_DRV1BUSY = 0x02, 485 FD_MSR_DRV2BUSY = 0x04, 486 FD_MSR_DRV3BUSY = 0x08, 487 FD_MSR_CMDBUSY = 0x10, 488 FD_MSR_NONDMA = 0x20, 489 FD_MSR_DIO = 0x40, 490 FD_MSR_RQM = 0x80, 491 }; 492 493 enum { 494 FD_DIR_DSKCHG = 0x80, 495 }; 496 497 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) 498 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) 499 500 struct FDCtrl { 501 MemoryRegion iomem; 502 qemu_irq irq; 503 /* Controller state */ 504 QEMUTimer *result_timer; 505 int dma_chann; 506 /* Controller's identification */ 507 uint8_t version; 508 /* HW */ 509 uint8_t sra; 510 uint8_t srb; 511 uint8_t dor; 512 uint8_t dor_vmstate; /* only used as temp during vmstate */ 513 uint8_t tdr; 514 uint8_t dsr; 515 uint8_t msr; 516 uint8_t cur_drv; 517 uint8_t status0; 518 uint8_t status1; 519 uint8_t status2; 520 /* Command FIFO */ 521 uint8_t *fifo; 522 int32_t fifo_size; 523 uint32_t data_pos; 524 uint32_t data_len; 525 uint8_t data_state; 526 uint8_t data_dir; 527 uint8_t eot; /* last wanted sector */ 528 /* States kept only to be returned back */ 529 /* precompensation */ 530 uint8_t precomp_trk; 531 uint8_t config; 532 uint8_t lock; 533 /* Power down config (also with status regB access mode */ 534 uint8_t pwrd; 535 /* Floppy drives */ 536 uint8_t num_floppies; 537 /* Sun4m quirks? */ 538 int sun4m; 539 FDrive drives[MAX_FD]; 540 int reset_sensei; 541 uint32_t check_media_rate; 542 /* Timers state */ 543 uint8_t timer0; 544 uint8_t timer1; 545 }; 546 547 #define TYPE_SYSBUS_FDC "base-sysbus-fdc" 548 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC) 549 550 typedef struct FDCtrlSysBus { 551 /*< private >*/ 552 SysBusDevice parent_obj; 553 /*< public >*/ 554 555 struct FDCtrl state; 556 } FDCtrlSysBus; 557 558 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC) 559 560 typedef struct FDCtrlISABus { 561 ISADevice parent_obj; 562 563 uint32_t iobase; 564 uint32_t irq; 565 uint32_t dma; 566 struct FDCtrl state; 567 int32_t bootindexA; 568 int32_t bootindexB; 569 } FDCtrlISABus; 570 571 static uint32_t fdctrl_read (void *opaque, uint32_t reg) 572 { 573 FDCtrl *fdctrl = opaque; 574 uint32_t retval; 575 576 reg &= 7; 577 switch (reg) { 578 case FD_REG_SRA: 579 retval = fdctrl_read_statusA(fdctrl); 580 break; 581 case FD_REG_SRB: 582 retval = fdctrl_read_statusB(fdctrl); 583 break; 584 case FD_REG_DOR: 585 retval = fdctrl_read_dor(fdctrl); 586 break; 587 case FD_REG_TDR: 588 retval = fdctrl_read_tape(fdctrl); 589 break; 590 case FD_REG_MSR: 591 retval = fdctrl_read_main_status(fdctrl); 592 break; 593 case FD_REG_FIFO: 594 retval = fdctrl_read_data(fdctrl); 595 break; 596 case FD_REG_DIR: 597 retval = fdctrl_read_dir(fdctrl); 598 break; 599 default: 600 retval = (uint32_t)(-1); 601 break; 602 } 603 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); 604 605 return retval; 606 } 607 608 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) 609 { 610 FDCtrl *fdctrl = opaque; 611 612 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); 613 614 reg &= 7; 615 switch (reg) { 616 case FD_REG_DOR: 617 fdctrl_write_dor(fdctrl, value); 618 break; 619 case FD_REG_TDR: 620 fdctrl_write_tape(fdctrl, value); 621 break; 622 case FD_REG_DSR: 623 fdctrl_write_rate(fdctrl, value); 624 break; 625 case FD_REG_FIFO: 626 fdctrl_write_data(fdctrl, value); 627 break; 628 case FD_REG_CCR: 629 fdctrl_write_ccr(fdctrl, value); 630 break; 631 default: 632 break; 633 } 634 } 635 636 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg, 637 unsigned ize) 638 { 639 return fdctrl_read(opaque, (uint32_t)reg); 640 } 641 642 static void fdctrl_write_mem (void *opaque, hwaddr reg, 643 uint64_t value, unsigned size) 644 { 645 fdctrl_write(opaque, (uint32_t)reg, value); 646 } 647 648 static const MemoryRegionOps fdctrl_mem_ops = { 649 .read = fdctrl_read_mem, 650 .write = fdctrl_write_mem, 651 .endianness = DEVICE_NATIVE_ENDIAN, 652 }; 653 654 static const MemoryRegionOps fdctrl_mem_strict_ops = { 655 .read = fdctrl_read_mem, 656 .write = fdctrl_write_mem, 657 .endianness = DEVICE_NATIVE_ENDIAN, 658 .valid = { 659 .min_access_size = 1, 660 .max_access_size = 1, 661 }, 662 }; 663 664 static bool fdrive_media_changed_needed(void *opaque) 665 { 666 FDrive *drive = opaque; 667 668 return (drive->bs != NULL && drive->media_changed != 1); 669 } 670 671 static const VMStateDescription vmstate_fdrive_media_changed = { 672 .name = "fdrive/media_changed", 673 .version_id = 1, 674 .minimum_version_id = 1, 675 .fields = (VMStateField[]) { 676 VMSTATE_UINT8(media_changed, FDrive), 677 VMSTATE_END_OF_LIST() 678 } 679 }; 680 681 static bool fdrive_media_rate_needed(void *opaque) 682 { 683 FDrive *drive = opaque; 684 685 return drive->fdctrl->check_media_rate; 686 } 687 688 static const VMStateDescription vmstate_fdrive_media_rate = { 689 .name = "fdrive/media_rate", 690 .version_id = 1, 691 .minimum_version_id = 1, 692 .fields = (VMStateField[]) { 693 VMSTATE_UINT8(media_rate, FDrive), 694 VMSTATE_END_OF_LIST() 695 } 696 }; 697 698 static bool fdrive_perpendicular_needed(void *opaque) 699 { 700 FDrive *drive = opaque; 701 702 return drive->perpendicular != 0; 703 } 704 705 static const VMStateDescription vmstate_fdrive_perpendicular = { 706 .name = "fdrive/perpendicular", 707 .version_id = 1, 708 .minimum_version_id = 1, 709 .fields = (VMStateField[]) { 710 VMSTATE_UINT8(perpendicular, FDrive), 711 VMSTATE_END_OF_LIST() 712 } 713 }; 714 715 static int fdrive_post_load(void *opaque, int version_id) 716 { 717 fd_revalidate(opaque); 718 return 0; 719 } 720 721 static const VMStateDescription vmstate_fdrive = { 722 .name = "fdrive", 723 .version_id = 1, 724 .minimum_version_id = 1, 725 .post_load = fdrive_post_load, 726 .fields = (VMStateField[]) { 727 VMSTATE_UINT8(head, FDrive), 728 VMSTATE_UINT8(track, FDrive), 729 VMSTATE_UINT8(sect, FDrive), 730 VMSTATE_END_OF_LIST() 731 }, 732 .subsections = (VMStateSubsection[]) { 733 { 734 .vmsd = &vmstate_fdrive_media_changed, 735 .needed = &fdrive_media_changed_needed, 736 } , { 737 .vmsd = &vmstate_fdrive_media_rate, 738 .needed = &fdrive_media_rate_needed, 739 } , { 740 .vmsd = &vmstate_fdrive_perpendicular, 741 .needed = &fdrive_perpendicular_needed, 742 } , { 743 /* empty */ 744 } 745 } 746 }; 747 748 static void fdc_pre_save(void *opaque) 749 { 750 FDCtrl *s = opaque; 751 752 s->dor_vmstate = s->dor | GET_CUR_DRV(s); 753 } 754 755 static int fdc_post_load(void *opaque, int version_id) 756 { 757 FDCtrl *s = opaque; 758 759 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); 760 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; 761 return 0; 762 } 763 764 static bool fdc_reset_sensei_needed(void *opaque) 765 { 766 FDCtrl *s = opaque; 767 768 return s->reset_sensei != 0; 769 } 770 771 static const VMStateDescription vmstate_fdc_reset_sensei = { 772 .name = "fdc/reset_sensei", 773 .version_id = 1, 774 .minimum_version_id = 1, 775 .fields = (VMStateField[]) { 776 VMSTATE_INT32(reset_sensei, FDCtrl), 777 VMSTATE_END_OF_LIST() 778 } 779 }; 780 781 static bool fdc_result_timer_needed(void *opaque) 782 { 783 FDCtrl *s = opaque; 784 785 return timer_pending(s->result_timer); 786 } 787 788 static const VMStateDescription vmstate_fdc_result_timer = { 789 .name = "fdc/result_timer", 790 .version_id = 1, 791 .minimum_version_id = 1, 792 .fields = (VMStateField[]) { 793 VMSTATE_TIMER(result_timer, FDCtrl), 794 VMSTATE_END_OF_LIST() 795 } 796 }; 797 798 static const VMStateDescription vmstate_fdc = { 799 .name = "fdc", 800 .version_id = 2, 801 .minimum_version_id = 2, 802 .pre_save = fdc_pre_save, 803 .post_load = fdc_post_load, 804 .fields = (VMStateField[]) { 805 /* Controller State */ 806 VMSTATE_UINT8(sra, FDCtrl), 807 VMSTATE_UINT8(srb, FDCtrl), 808 VMSTATE_UINT8(dor_vmstate, FDCtrl), 809 VMSTATE_UINT8(tdr, FDCtrl), 810 VMSTATE_UINT8(dsr, FDCtrl), 811 VMSTATE_UINT8(msr, FDCtrl), 812 VMSTATE_UINT8(status0, FDCtrl), 813 VMSTATE_UINT8(status1, FDCtrl), 814 VMSTATE_UINT8(status2, FDCtrl), 815 /* Command FIFO */ 816 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, 817 uint8_t), 818 VMSTATE_UINT32(data_pos, FDCtrl), 819 VMSTATE_UINT32(data_len, FDCtrl), 820 VMSTATE_UINT8(data_state, FDCtrl), 821 VMSTATE_UINT8(data_dir, FDCtrl), 822 VMSTATE_UINT8(eot, FDCtrl), 823 /* States kept only to be returned back */ 824 VMSTATE_UINT8(timer0, FDCtrl), 825 VMSTATE_UINT8(timer1, FDCtrl), 826 VMSTATE_UINT8(precomp_trk, FDCtrl), 827 VMSTATE_UINT8(config, FDCtrl), 828 VMSTATE_UINT8(lock, FDCtrl), 829 VMSTATE_UINT8(pwrd, FDCtrl), 830 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl), 831 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, 832 vmstate_fdrive, FDrive), 833 VMSTATE_END_OF_LIST() 834 }, 835 .subsections = (VMStateSubsection[]) { 836 { 837 .vmsd = &vmstate_fdc_reset_sensei, 838 .needed = fdc_reset_sensei_needed, 839 } , { 840 .vmsd = &vmstate_fdc_result_timer, 841 .needed = fdc_result_timer_needed, 842 } , { 843 /* empty */ 844 } 845 } 846 }; 847 848 static void fdctrl_external_reset_sysbus(DeviceState *d) 849 { 850 FDCtrlSysBus *sys = SYSBUS_FDC(d); 851 FDCtrl *s = &sys->state; 852 853 fdctrl_reset(s, 0); 854 } 855 856 static void fdctrl_external_reset_isa(DeviceState *d) 857 { 858 FDCtrlISABus *isa = ISA_FDC(d); 859 FDCtrl *s = &isa->state; 860 861 fdctrl_reset(s, 0); 862 } 863 864 static void fdctrl_handle_tc(void *opaque, int irq, int level) 865 { 866 //FDCtrl *s = opaque; 867 868 if (level) { 869 // XXX 870 FLOPPY_DPRINTF("TC pulsed\n"); 871 } 872 } 873 874 /* Change IRQ state */ 875 static void fdctrl_reset_irq(FDCtrl *fdctrl) 876 { 877 fdctrl->status0 = 0; 878 if (!(fdctrl->sra & FD_SRA_INTPEND)) 879 return; 880 FLOPPY_DPRINTF("Reset interrupt\n"); 881 qemu_set_irq(fdctrl->irq, 0); 882 fdctrl->sra &= ~FD_SRA_INTPEND; 883 } 884 885 static void fdctrl_raise_irq(FDCtrl *fdctrl) 886 { 887 /* Sparc mutation */ 888 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) { 889 /* XXX: not sure */ 890 fdctrl->msr &= ~FD_MSR_CMDBUSY; 891 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 892 return; 893 } 894 if (!(fdctrl->sra & FD_SRA_INTPEND)) { 895 qemu_set_irq(fdctrl->irq, 1); 896 fdctrl->sra |= FD_SRA_INTPEND; 897 } 898 899 fdctrl->reset_sensei = 0; 900 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); 901 } 902 903 /* Reset controller */ 904 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) 905 { 906 int i; 907 908 FLOPPY_DPRINTF("reset controller\n"); 909 fdctrl_reset_irq(fdctrl); 910 /* Initialise controller */ 911 fdctrl->sra = 0; 912 fdctrl->srb = 0xc0; 913 if (!fdctrl->drives[1].bs) 914 fdctrl->sra |= FD_SRA_nDRV2; 915 fdctrl->cur_drv = 0; 916 fdctrl->dor = FD_DOR_nRESET; 917 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; 918 fdctrl->msr = FD_MSR_RQM; 919 fdctrl->reset_sensei = 0; 920 timer_del(fdctrl->result_timer); 921 /* FIFO state */ 922 fdctrl->data_pos = 0; 923 fdctrl->data_len = 0; 924 fdctrl->data_state = 0; 925 fdctrl->data_dir = FD_DIR_WRITE; 926 for (i = 0; i < MAX_FD; i++) 927 fd_recalibrate(&fdctrl->drives[i]); 928 fdctrl_reset_fifo(fdctrl); 929 if (do_irq) { 930 fdctrl->status0 |= FD_SR0_RDYCHG; 931 fdctrl_raise_irq(fdctrl); 932 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; 933 } 934 } 935 936 static inline FDrive *drv0(FDCtrl *fdctrl) 937 { 938 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; 939 } 940 941 static inline FDrive *drv1(FDCtrl *fdctrl) 942 { 943 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) 944 return &fdctrl->drives[1]; 945 else 946 return &fdctrl->drives[0]; 947 } 948 949 #if MAX_FD == 4 950 static inline FDrive *drv2(FDCtrl *fdctrl) 951 { 952 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) 953 return &fdctrl->drives[2]; 954 else 955 return &fdctrl->drives[1]; 956 } 957 958 static inline FDrive *drv3(FDCtrl *fdctrl) 959 { 960 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) 961 return &fdctrl->drives[3]; 962 else 963 return &fdctrl->drives[2]; 964 } 965 #endif 966 967 static FDrive *get_cur_drv(FDCtrl *fdctrl) 968 { 969 switch (fdctrl->cur_drv) { 970 case 0: return drv0(fdctrl); 971 case 1: return drv1(fdctrl); 972 #if MAX_FD == 4 973 case 2: return drv2(fdctrl); 974 case 3: return drv3(fdctrl); 975 #endif 976 default: return NULL; 977 } 978 } 979 980 /* Status A register : 0x00 (read-only) */ 981 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) 982 { 983 uint32_t retval = fdctrl->sra; 984 985 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); 986 987 return retval; 988 } 989 990 /* Status B register : 0x01 (read-only) */ 991 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) 992 { 993 uint32_t retval = fdctrl->srb; 994 995 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); 996 997 return retval; 998 } 999 1000 /* Digital output register : 0x02 */ 1001 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) 1002 { 1003 uint32_t retval = fdctrl->dor; 1004 1005 /* Selected drive */ 1006 retval |= fdctrl->cur_drv; 1007 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); 1008 1009 return retval; 1010 } 1011 1012 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) 1013 { 1014 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); 1015 1016 /* Motors */ 1017 if (value & FD_DOR_MOTEN0) 1018 fdctrl->srb |= FD_SRB_MTR0; 1019 else 1020 fdctrl->srb &= ~FD_SRB_MTR0; 1021 if (value & FD_DOR_MOTEN1) 1022 fdctrl->srb |= FD_SRB_MTR1; 1023 else 1024 fdctrl->srb &= ~FD_SRB_MTR1; 1025 1026 /* Drive */ 1027 if (value & 1) 1028 fdctrl->srb |= FD_SRB_DR0; 1029 else 1030 fdctrl->srb &= ~FD_SRB_DR0; 1031 1032 /* Reset */ 1033 if (!(value & FD_DOR_nRESET)) { 1034 if (fdctrl->dor & FD_DOR_nRESET) { 1035 FLOPPY_DPRINTF("controller enter RESET state\n"); 1036 } 1037 } else { 1038 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1039 FLOPPY_DPRINTF("controller out of RESET state\n"); 1040 fdctrl_reset(fdctrl, 1); 1041 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1042 } 1043 } 1044 /* Selected drive */ 1045 fdctrl->cur_drv = value & FD_DOR_SELMASK; 1046 1047 fdctrl->dor = value; 1048 } 1049 1050 /* Tape drive register : 0x03 */ 1051 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) 1052 { 1053 uint32_t retval = fdctrl->tdr; 1054 1055 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); 1056 1057 return retval; 1058 } 1059 1060 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) 1061 { 1062 /* Reset mode */ 1063 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1064 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1065 return; 1066 } 1067 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); 1068 /* Disk boot selection indicator */ 1069 fdctrl->tdr = value & FD_TDR_BOOTSEL; 1070 /* Tape indicators: never allow */ 1071 } 1072 1073 /* Main status register : 0x04 (read) */ 1074 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) 1075 { 1076 uint32_t retval = fdctrl->msr; 1077 1078 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1079 fdctrl->dor |= FD_DOR_nRESET; 1080 1081 /* Sparc mutation */ 1082 if (fdctrl->sun4m) { 1083 retval |= FD_MSR_DIO; 1084 fdctrl_reset_irq(fdctrl); 1085 }; 1086 1087 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); 1088 1089 return retval; 1090 } 1091 1092 /* Data select rate register : 0x04 (write) */ 1093 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) 1094 { 1095 /* Reset mode */ 1096 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1097 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1098 return; 1099 } 1100 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); 1101 /* Reset: autoclear */ 1102 if (value & FD_DSR_SWRESET) { 1103 fdctrl->dor &= ~FD_DOR_nRESET; 1104 fdctrl_reset(fdctrl, 1); 1105 fdctrl->dor |= FD_DOR_nRESET; 1106 } 1107 if (value & FD_DSR_PWRDOWN) { 1108 fdctrl_reset(fdctrl, 1); 1109 } 1110 fdctrl->dsr = value; 1111 } 1112 1113 /* Configuration control register: 0x07 (write) */ 1114 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) 1115 { 1116 /* Reset mode */ 1117 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1118 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1119 return; 1120 } 1121 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); 1122 1123 /* Only the rate selection bits used in AT mode, and we 1124 * store those in the DSR. 1125 */ 1126 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | 1127 (value & FD_DSR_DRATEMASK); 1128 } 1129 1130 static int fdctrl_media_changed(FDrive *drv) 1131 { 1132 return drv->media_changed; 1133 } 1134 1135 /* Digital input register : 0x07 (read-only) */ 1136 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) 1137 { 1138 uint32_t retval = 0; 1139 1140 if (fdctrl_media_changed(get_cur_drv(fdctrl))) { 1141 retval |= FD_DIR_DSKCHG; 1142 } 1143 if (retval != 0) { 1144 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); 1145 } 1146 1147 return retval; 1148 } 1149 1150 /* FIFO state control */ 1151 static void fdctrl_reset_fifo(FDCtrl *fdctrl) 1152 { 1153 fdctrl->data_dir = FD_DIR_WRITE; 1154 fdctrl->data_pos = 0; 1155 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); 1156 } 1157 1158 /* Set FIFO status for the host to read */ 1159 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len) 1160 { 1161 fdctrl->data_dir = FD_DIR_READ; 1162 fdctrl->data_len = fifo_len; 1163 fdctrl->data_pos = 0; 1164 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; 1165 } 1166 1167 /* Set an error: unimplemented/unknown command */ 1168 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) 1169 { 1170 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n", 1171 fdctrl->fifo[0]); 1172 fdctrl->fifo[0] = FD_SR0_INVCMD; 1173 fdctrl_set_fifo(fdctrl, 1); 1174 } 1175 1176 /* Seek to next sector 1177 * returns 0 when end of track reached (for DBL_SIDES on head 1) 1178 * otherwise returns 1 1179 */ 1180 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) 1181 { 1182 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", 1183 cur_drv->head, cur_drv->track, cur_drv->sect, 1184 fd_sector(cur_drv)); 1185 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an 1186 error in fact */ 1187 uint8_t new_head = cur_drv->head; 1188 uint8_t new_track = cur_drv->track; 1189 uint8_t new_sect = cur_drv->sect; 1190 1191 int ret = 1; 1192 1193 if (new_sect >= cur_drv->last_sect || 1194 new_sect == fdctrl->eot) { 1195 new_sect = 1; 1196 if (FD_MULTI_TRACK(fdctrl->data_state)) { 1197 if (new_head == 0 && 1198 (cur_drv->flags & FDISK_DBL_SIDES) != 0) { 1199 new_head = 1; 1200 } else { 1201 new_head = 0; 1202 new_track++; 1203 fdctrl->status0 |= FD_SR0_SEEK; 1204 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) { 1205 ret = 0; 1206 } 1207 } 1208 } else { 1209 fdctrl->status0 |= FD_SR0_SEEK; 1210 new_track++; 1211 ret = 0; 1212 } 1213 if (ret == 1) { 1214 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", 1215 new_head, new_track, new_sect, fd_sector(cur_drv)); 1216 } 1217 } else { 1218 new_sect++; 1219 } 1220 fd_seek(cur_drv, new_head, new_track, new_sect, 1); 1221 return ret; 1222 } 1223 1224 /* Callback for transfer end (stop or abort) */ 1225 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, 1226 uint8_t status1, uint8_t status2) 1227 { 1228 FDrive *cur_drv; 1229 cur_drv = get_cur_drv(fdctrl); 1230 1231 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD); 1232 fdctrl->status0 |= GET_CUR_DRV(fdctrl); 1233 if (cur_drv->head) { 1234 fdctrl->status0 |= FD_SR0_HEAD; 1235 } 1236 fdctrl->status0 |= status0; 1237 1238 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", 1239 status0, status1, status2, fdctrl->status0); 1240 fdctrl->fifo[0] = fdctrl->status0; 1241 fdctrl->fifo[1] = status1; 1242 fdctrl->fifo[2] = status2; 1243 fdctrl->fifo[3] = cur_drv->track; 1244 fdctrl->fifo[4] = cur_drv->head; 1245 fdctrl->fifo[5] = cur_drv->sect; 1246 fdctrl->fifo[6] = FD_SECTOR_SC; 1247 fdctrl->data_dir = FD_DIR_READ; 1248 if (!(fdctrl->msr & FD_MSR_NONDMA)) { 1249 DMA_release_DREQ(fdctrl->dma_chann); 1250 } 1251 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 1252 fdctrl->msr &= ~FD_MSR_NONDMA; 1253 1254 fdctrl_set_fifo(fdctrl, 7); 1255 fdctrl_raise_irq(fdctrl); 1256 } 1257 1258 /* Prepare a data transfer (either DMA or FIFO) */ 1259 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) 1260 { 1261 FDrive *cur_drv; 1262 uint8_t kh, kt, ks; 1263 1264 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1265 cur_drv = get_cur_drv(fdctrl); 1266 kt = fdctrl->fifo[2]; 1267 kh = fdctrl->fifo[3]; 1268 ks = fdctrl->fifo[4]; 1269 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", 1270 GET_CUR_DRV(fdctrl), kh, kt, ks, 1271 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1272 NUM_SIDES(cur_drv))); 1273 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1274 case 2: 1275 /* sect too big */ 1276 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1277 fdctrl->fifo[3] = kt; 1278 fdctrl->fifo[4] = kh; 1279 fdctrl->fifo[5] = ks; 1280 return; 1281 case 3: 1282 /* track too big */ 1283 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1284 fdctrl->fifo[3] = kt; 1285 fdctrl->fifo[4] = kh; 1286 fdctrl->fifo[5] = ks; 1287 return; 1288 case 4: 1289 /* No seek enabled */ 1290 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1291 fdctrl->fifo[3] = kt; 1292 fdctrl->fifo[4] = kh; 1293 fdctrl->fifo[5] = ks; 1294 return; 1295 case 1: 1296 fdctrl->status0 |= FD_SR0_SEEK; 1297 break; 1298 default: 1299 break; 1300 } 1301 1302 /* Check the data rate. If the programmed data rate does not match 1303 * the currently inserted medium, the operation has to fail. */ 1304 if (fdctrl->check_media_rate && 1305 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 1306 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n", 1307 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 1308 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 1309 fdctrl->fifo[3] = kt; 1310 fdctrl->fifo[4] = kh; 1311 fdctrl->fifo[5] = ks; 1312 return; 1313 } 1314 1315 /* Set the FIFO state */ 1316 fdctrl->data_dir = direction; 1317 fdctrl->data_pos = 0; 1318 assert(fdctrl->msr & FD_MSR_CMDBUSY); 1319 if (fdctrl->fifo[0] & 0x80) 1320 fdctrl->data_state |= FD_STATE_MULTI; 1321 else 1322 fdctrl->data_state &= ~FD_STATE_MULTI; 1323 if (fdctrl->fifo[5] == 0) { 1324 fdctrl->data_len = fdctrl->fifo[8]; 1325 } else { 1326 int tmp; 1327 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); 1328 tmp = (fdctrl->fifo[6] - ks + 1); 1329 if (fdctrl->fifo[0] & 0x80) 1330 tmp += fdctrl->fifo[6]; 1331 fdctrl->data_len *= tmp; 1332 } 1333 fdctrl->eot = fdctrl->fifo[6]; 1334 if (fdctrl->dor & FD_DOR_DMAEN) { 1335 int dma_mode; 1336 /* DMA transfer are enabled. Check if DMA channel is well programmed */ 1337 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); 1338 dma_mode = (dma_mode >> 2) & 3; 1339 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", 1340 dma_mode, direction, 1341 (128 << fdctrl->fifo[5]) * 1342 (cur_drv->last_sect - ks + 1), fdctrl->data_len); 1343 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL || 1344 direction == FD_DIR_SCANH) && dma_mode == 0) || 1345 (direction == FD_DIR_WRITE && dma_mode == 2) || 1346 (direction == FD_DIR_READ && dma_mode == 1) || 1347 (direction == FD_DIR_VERIFY)) { 1348 /* No access is allowed until DMA transfer has completed */ 1349 fdctrl->msr &= ~FD_MSR_RQM; 1350 if (direction != FD_DIR_VERIFY) { 1351 /* Now, we just have to wait for the DMA controller to 1352 * recall us... 1353 */ 1354 DMA_hold_DREQ(fdctrl->dma_chann); 1355 DMA_schedule(fdctrl->dma_chann); 1356 } else { 1357 /* Start transfer */ 1358 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, 1359 fdctrl->data_len); 1360 } 1361 return; 1362 } else { 1363 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode, 1364 direction); 1365 } 1366 } 1367 FLOPPY_DPRINTF("start non-DMA transfer\n"); 1368 fdctrl->msr |= FD_MSR_NONDMA; 1369 if (direction != FD_DIR_WRITE) 1370 fdctrl->msr |= FD_MSR_DIO; 1371 /* IO based transfer: calculate len */ 1372 fdctrl_raise_irq(fdctrl); 1373 } 1374 1375 /* Prepare a transfer of deleted data */ 1376 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) 1377 { 1378 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n"); 1379 1380 /* We don't handle deleted data, 1381 * so we don't return *ANYTHING* 1382 */ 1383 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1384 } 1385 1386 /* handlers for DMA transfers */ 1387 static int fdctrl_transfer_handler (void *opaque, int nchan, 1388 int dma_pos, int dma_len) 1389 { 1390 FDCtrl *fdctrl; 1391 FDrive *cur_drv; 1392 int len, start_pos, rel_pos; 1393 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; 1394 1395 fdctrl = opaque; 1396 if (fdctrl->msr & FD_MSR_RQM) { 1397 FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); 1398 return 0; 1399 } 1400 cur_drv = get_cur_drv(fdctrl); 1401 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || 1402 fdctrl->data_dir == FD_DIR_SCANH) 1403 status2 = FD_SR2_SNS; 1404 if (dma_len > fdctrl->data_len) 1405 dma_len = fdctrl->data_len; 1406 if (cur_drv->bs == NULL) { 1407 if (fdctrl->data_dir == FD_DIR_WRITE) 1408 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1409 else 1410 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1411 len = 0; 1412 goto transfer_error; 1413 } 1414 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1415 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { 1416 len = dma_len - fdctrl->data_pos; 1417 if (len + rel_pos > FD_SECTOR_LEN) 1418 len = FD_SECTOR_LEN - rel_pos; 1419 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " 1420 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, 1421 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, 1422 cur_drv->track, cur_drv->sect, fd_sector(cur_drv), 1423 fd_sector(cur_drv) * FD_SECTOR_LEN); 1424 if (fdctrl->data_dir != FD_DIR_WRITE || 1425 len < FD_SECTOR_LEN || rel_pos != 0) { 1426 /* READ & SCAN commands and realign to a sector for WRITE */ 1427 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), 1428 fdctrl->fifo, 1) < 0) { 1429 FLOPPY_DPRINTF("Floppy: error getting sector %d\n", 1430 fd_sector(cur_drv)); 1431 /* Sure, image size is too small... */ 1432 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1433 } 1434 } 1435 switch (fdctrl->data_dir) { 1436 case FD_DIR_READ: 1437 /* READ commands */ 1438 DMA_write_memory (nchan, fdctrl->fifo + rel_pos, 1439 fdctrl->data_pos, len); 1440 break; 1441 case FD_DIR_WRITE: 1442 /* WRITE commands */ 1443 if (cur_drv->ro) { 1444 /* Handle readonly medium early, no need to do DMA, touch the 1445 * LED or attempt any writes. A real floppy doesn't attempt 1446 * to write to readonly media either. */ 1447 fdctrl_stop_transfer(fdctrl, 1448 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, 1449 0x00); 1450 goto transfer_error; 1451 } 1452 1453 DMA_read_memory (nchan, fdctrl->fifo + rel_pos, 1454 fdctrl->data_pos, len); 1455 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), 1456 fdctrl->fifo, 1) < 0) { 1457 FLOPPY_DPRINTF("error writing sector %d\n", 1458 fd_sector(cur_drv)); 1459 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1460 goto transfer_error; 1461 } 1462 break; 1463 case FD_DIR_VERIFY: 1464 /* VERIFY commands */ 1465 break; 1466 default: 1467 /* SCAN commands */ 1468 { 1469 uint8_t tmpbuf[FD_SECTOR_LEN]; 1470 int ret; 1471 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); 1472 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); 1473 if (ret == 0) { 1474 status2 = FD_SR2_SEH; 1475 goto end_transfer; 1476 } 1477 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || 1478 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { 1479 status2 = 0x00; 1480 goto end_transfer; 1481 } 1482 } 1483 break; 1484 } 1485 fdctrl->data_pos += len; 1486 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1487 if (rel_pos == 0) { 1488 /* Seek to next sector */ 1489 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) 1490 break; 1491 } 1492 } 1493 end_transfer: 1494 len = fdctrl->data_pos - start_pos; 1495 FLOPPY_DPRINTF("end transfer %d %d %d\n", 1496 fdctrl->data_pos, len, fdctrl->data_len); 1497 if (fdctrl->data_dir == FD_DIR_SCANE || 1498 fdctrl->data_dir == FD_DIR_SCANL || 1499 fdctrl->data_dir == FD_DIR_SCANH) 1500 status2 = FD_SR2_SEH; 1501 fdctrl->data_len -= len; 1502 fdctrl_stop_transfer(fdctrl, status0, status1, status2); 1503 transfer_error: 1504 1505 return len; 1506 } 1507 1508 /* Data register : 0x05 */ 1509 static uint32_t fdctrl_read_data(FDCtrl *fdctrl) 1510 { 1511 FDrive *cur_drv; 1512 uint32_t retval = 0; 1513 int pos; 1514 1515 cur_drv = get_cur_drv(fdctrl); 1516 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1517 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { 1518 FLOPPY_DPRINTF("error: controller not ready for reading\n"); 1519 return 0; 1520 } 1521 pos = fdctrl->data_pos; 1522 if (fdctrl->msr & FD_MSR_NONDMA) { 1523 pos %= FD_SECTOR_LEN; 1524 if (pos == 0) { 1525 if (fdctrl->data_pos != 0) 1526 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1527 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1528 fd_sector(cur_drv)); 1529 return 0; 1530 } 1531 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1532 FLOPPY_DPRINTF("error getting sector %d\n", 1533 fd_sector(cur_drv)); 1534 /* Sure, image size is too small... */ 1535 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1536 } 1537 } 1538 } 1539 retval = fdctrl->fifo[pos]; 1540 if (++fdctrl->data_pos == fdctrl->data_len) { 1541 fdctrl->data_pos = 0; 1542 /* Switch from transfer mode to status mode 1543 * then from status mode to command mode 1544 */ 1545 if (fdctrl->msr & FD_MSR_NONDMA) { 1546 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1547 } else { 1548 fdctrl_reset_fifo(fdctrl); 1549 fdctrl_reset_irq(fdctrl); 1550 } 1551 } 1552 FLOPPY_DPRINTF("data register: 0x%02x\n", retval); 1553 1554 return retval; 1555 } 1556 1557 static void fdctrl_format_sector(FDCtrl *fdctrl) 1558 { 1559 FDrive *cur_drv; 1560 uint8_t kh, kt, ks; 1561 1562 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1563 cur_drv = get_cur_drv(fdctrl); 1564 kt = fdctrl->fifo[6]; 1565 kh = fdctrl->fifo[7]; 1566 ks = fdctrl->fifo[8]; 1567 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", 1568 GET_CUR_DRV(fdctrl), kh, kt, ks, 1569 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1570 NUM_SIDES(cur_drv))); 1571 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1572 case 2: 1573 /* sect too big */ 1574 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1575 fdctrl->fifo[3] = kt; 1576 fdctrl->fifo[4] = kh; 1577 fdctrl->fifo[5] = ks; 1578 return; 1579 case 3: 1580 /* track too big */ 1581 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1582 fdctrl->fifo[3] = kt; 1583 fdctrl->fifo[4] = kh; 1584 fdctrl->fifo[5] = ks; 1585 return; 1586 case 4: 1587 /* No seek enabled */ 1588 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1589 fdctrl->fifo[3] = kt; 1590 fdctrl->fifo[4] = kh; 1591 fdctrl->fifo[5] = ks; 1592 return; 1593 case 1: 1594 fdctrl->status0 |= FD_SR0_SEEK; 1595 break; 1596 default: 1597 break; 1598 } 1599 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1600 if (cur_drv->bs == NULL || 1601 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1602 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv)); 1603 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1604 } else { 1605 if (cur_drv->sect == cur_drv->last_sect) { 1606 fdctrl->data_state &= ~FD_STATE_FORMAT; 1607 /* Last sector done */ 1608 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1609 } else { 1610 /* More to do */ 1611 fdctrl->data_pos = 0; 1612 fdctrl->data_len = 4; 1613 } 1614 } 1615 } 1616 1617 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) 1618 { 1619 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; 1620 fdctrl->fifo[0] = fdctrl->lock << 4; 1621 fdctrl_set_fifo(fdctrl, 1); 1622 } 1623 1624 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) 1625 { 1626 FDrive *cur_drv = get_cur_drv(fdctrl); 1627 1628 /* Drives position */ 1629 fdctrl->fifo[0] = drv0(fdctrl)->track; 1630 fdctrl->fifo[1] = drv1(fdctrl)->track; 1631 #if MAX_FD == 4 1632 fdctrl->fifo[2] = drv2(fdctrl)->track; 1633 fdctrl->fifo[3] = drv3(fdctrl)->track; 1634 #else 1635 fdctrl->fifo[2] = 0; 1636 fdctrl->fifo[3] = 0; 1637 #endif 1638 /* timers */ 1639 fdctrl->fifo[4] = fdctrl->timer0; 1640 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); 1641 fdctrl->fifo[6] = cur_drv->last_sect; 1642 fdctrl->fifo[7] = (fdctrl->lock << 7) | 1643 (cur_drv->perpendicular << 2); 1644 fdctrl->fifo[8] = fdctrl->config; 1645 fdctrl->fifo[9] = fdctrl->precomp_trk; 1646 fdctrl_set_fifo(fdctrl, 10); 1647 } 1648 1649 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) 1650 { 1651 /* Controller's version */ 1652 fdctrl->fifo[0] = fdctrl->version; 1653 fdctrl_set_fifo(fdctrl, 1); 1654 } 1655 1656 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) 1657 { 1658 fdctrl->fifo[0] = 0x41; /* Stepping 1 */ 1659 fdctrl_set_fifo(fdctrl, 1); 1660 } 1661 1662 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) 1663 { 1664 FDrive *cur_drv = get_cur_drv(fdctrl); 1665 1666 /* Drives position */ 1667 drv0(fdctrl)->track = fdctrl->fifo[3]; 1668 drv1(fdctrl)->track = fdctrl->fifo[4]; 1669 #if MAX_FD == 4 1670 drv2(fdctrl)->track = fdctrl->fifo[5]; 1671 drv3(fdctrl)->track = fdctrl->fifo[6]; 1672 #endif 1673 /* timers */ 1674 fdctrl->timer0 = fdctrl->fifo[7]; 1675 fdctrl->timer1 = fdctrl->fifo[8]; 1676 cur_drv->last_sect = fdctrl->fifo[9]; 1677 fdctrl->lock = fdctrl->fifo[10] >> 7; 1678 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; 1679 fdctrl->config = fdctrl->fifo[11]; 1680 fdctrl->precomp_trk = fdctrl->fifo[12]; 1681 fdctrl->pwrd = fdctrl->fifo[13]; 1682 fdctrl_reset_fifo(fdctrl); 1683 } 1684 1685 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) 1686 { 1687 FDrive *cur_drv = get_cur_drv(fdctrl); 1688 1689 fdctrl->fifo[0] = 0; 1690 fdctrl->fifo[1] = 0; 1691 /* Drives position */ 1692 fdctrl->fifo[2] = drv0(fdctrl)->track; 1693 fdctrl->fifo[3] = drv1(fdctrl)->track; 1694 #if MAX_FD == 4 1695 fdctrl->fifo[4] = drv2(fdctrl)->track; 1696 fdctrl->fifo[5] = drv3(fdctrl)->track; 1697 #else 1698 fdctrl->fifo[4] = 0; 1699 fdctrl->fifo[5] = 0; 1700 #endif 1701 /* timers */ 1702 fdctrl->fifo[6] = fdctrl->timer0; 1703 fdctrl->fifo[7] = fdctrl->timer1; 1704 fdctrl->fifo[8] = cur_drv->last_sect; 1705 fdctrl->fifo[9] = (fdctrl->lock << 7) | 1706 (cur_drv->perpendicular << 2); 1707 fdctrl->fifo[10] = fdctrl->config; 1708 fdctrl->fifo[11] = fdctrl->precomp_trk; 1709 fdctrl->fifo[12] = fdctrl->pwrd; 1710 fdctrl->fifo[13] = 0; 1711 fdctrl->fifo[14] = 0; 1712 fdctrl_set_fifo(fdctrl, 15); 1713 } 1714 1715 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) 1716 { 1717 FDrive *cur_drv = get_cur_drv(fdctrl); 1718 1719 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1720 timer_mod(fdctrl->result_timer, 1721 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50)); 1722 } 1723 1724 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) 1725 { 1726 FDrive *cur_drv; 1727 1728 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1729 cur_drv = get_cur_drv(fdctrl); 1730 fdctrl->data_state |= FD_STATE_FORMAT; 1731 if (fdctrl->fifo[0] & 0x80) 1732 fdctrl->data_state |= FD_STATE_MULTI; 1733 else 1734 fdctrl->data_state &= ~FD_STATE_MULTI; 1735 cur_drv->bps = 1736 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; 1737 #if 0 1738 cur_drv->last_sect = 1739 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : 1740 fdctrl->fifo[3] / 2; 1741 #else 1742 cur_drv->last_sect = fdctrl->fifo[3]; 1743 #endif 1744 /* TODO: implement format using DMA expected by the Bochs BIOS 1745 * and Linux fdformat (read 3 bytes per sector via DMA and fill 1746 * the sector with the specified fill byte 1747 */ 1748 fdctrl->data_state &= ~FD_STATE_FORMAT; 1749 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1750 } 1751 1752 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) 1753 { 1754 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; 1755 fdctrl->timer1 = fdctrl->fifo[2] >> 1; 1756 if (fdctrl->fifo[2] & 1) 1757 fdctrl->dor &= ~FD_DOR_DMAEN; 1758 else 1759 fdctrl->dor |= FD_DOR_DMAEN; 1760 /* No result back */ 1761 fdctrl_reset_fifo(fdctrl); 1762 } 1763 1764 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) 1765 { 1766 FDrive *cur_drv; 1767 1768 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1769 cur_drv = get_cur_drv(fdctrl); 1770 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1771 /* 1 Byte status back */ 1772 fdctrl->fifo[0] = (cur_drv->ro << 6) | 1773 (cur_drv->track == 0 ? 0x10 : 0x00) | 1774 (cur_drv->head << 2) | 1775 GET_CUR_DRV(fdctrl) | 1776 0x28; 1777 fdctrl_set_fifo(fdctrl, 1); 1778 } 1779 1780 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) 1781 { 1782 FDrive *cur_drv; 1783 1784 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1785 cur_drv = get_cur_drv(fdctrl); 1786 fd_recalibrate(cur_drv); 1787 fdctrl_reset_fifo(fdctrl); 1788 /* Raise Interrupt */ 1789 fdctrl->status0 |= FD_SR0_SEEK; 1790 fdctrl_raise_irq(fdctrl); 1791 } 1792 1793 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) 1794 { 1795 FDrive *cur_drv = get_cur_drv(fdctrl); 1796 1797 if (fdctrl->reset_sensei > 0) { 1798 fdctrl->fifo[0] = 1799 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; 1800 fdctrl->reset_sensei--; 1801 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) { 1802 fdctrl->fifo[0] = FD_SR0_INVCMD; 1803 fdctrl_set_fifo(fdctrl, 1); 1804 return; 1805 } else { 1806 fdctrl->fifo[0] = 1807 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0)) 1808 | GET_CUR_DRV(fdctrl); 1809 } 1810 1811 fdctrl->fifo[1] = cur_drv->track; 1812 fdctrl_set_fifo(fdctrl, 2); 1813 fdctrl_reset_irq(fdctrl); 1814 fdctrl->status0 = FD_SR0_RDYCHG; 1815 } 1816 1817 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) 1818 { 1819 FDrive *cur_drv; 1820 1821 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1822 cur_drv = get_cur_drv(fdctrl); 1823 fdctrl_reset_fifo(fdctrl); 1824 /* The seek command just sends step pulses to the drive and doesn't care if 1825 * there is a medium inserted of if it's banging the head against the drive. 1826 */ 1827 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1); 1828 /* Raise Interrupt */ 1829 fdctrl->status0 |= FD_SR0_SEEK; 1830 fdctrl_raise_irq(fdctrl); 1831 } 1832 1833 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) 1834 { 1835 FDrive *cur_drv = get_cur_drv(fdctrl); 1836 1837 if (fdctrl->fifo[1] & 0x80) 1838 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; 1839 /* No result back */ 1840 fdctrl_reset_fifo(fdctrl); 1841 } 1842 1843 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) 1844 { 1845 fdctrl->config = fdctrl->fifo[2]; 1846 fdctrl->precomp_trk = fdctrl->fifo[3]; 1847 /* No result back */ 1848 fdctrl_reset_fifo(fdctrl); 1849 } 1850 1851 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) 1852 { 1853 fdctrl->pwrd = fdctrl->fifo[1]; 1854 fdctrl->fifo[0] = fdctrl->fifo[1]; 1855 fdctrl_set_fifo(fdctrl, 1); 1856 } 1857 1858 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) 1859 { 1860 /* No result back */ 1861 fdctrl_reset_fifo(fdctrl); 1862 } 1863 1864 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) 1865 { 1866 FDrive *cur_drv = get_cur_drv(fdctrl); 1867 1868 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { 1869 /* Command parameters done */ 1870 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) { 1871 fdctrl->fifo[0] = fdctrl->fifo[1]; 1872 fdctrl->fifo[2] = 0; 1873 fdctrl->fifo[3] = 0; 1874 fdctrl_set_fifo(fdctrl, 4); 1875 } else { 1876 fdctrl_reset_fifo(fdctrl); 1877 } 1878 } else if (fdctrl->data_len > 7) { 1879 /* ERROR */ 1880 fdctrl->fifo[0] = 0x80 | 1881 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); 1882 fdctrl_set_fifo(fdctrl, 1); 1883 } 1884 } 1885 1886 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) 1887 { 1888 FDrive *cur_drv; 1889 1890 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1891 cur_drv = get_cur_drv(fdctrl); 1892 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { 1893 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1, 1894 cur_drv->sect, 1); 1895 } else { 1896 fd_seek(cur_drv, cur_drv->head, 1897 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1); 1898 } 1899 fdctrl_reset_fifo(fdctrl); 1900 /* Raise Interrupt */ 1901 fdctrl->status0 |= FD_SR0_SEEK; 1902 fdctrl_raise_irq(fdctrl); 1903 } 1904 1905 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) 1906 { 1907 FDrive *cur_drv; 1908 1909 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1910 cur_drv = get_cur_drv(fdctrl); 1911 if (fdctrl->fifo[2] > cur_drv->track) { 1912 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1); 1913 } else { 1914 fd_seek(cur_drv, cur_drv->head, 1915 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1); 1916 } 1917 fdctrl_reset_fifo(fdctrl); 1918 /* Raise Interrupt */ 1919 fdctrl->status0 |= FD_SR0_SEEK; 1920 fdctrl_raise_irq(fdctrl); 1921 } 1922 1923 static const struct { 1924 uint8_t value; 1925 uint8_t mask; 1926 const char* name; 1927 int parameters; 1928 void (*handler)(FDCtrl *fdctrl, int direction); 1929 int direction; 1930 } handlers[] = { 1931 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, 1932 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, 1933 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, 1934 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, 1935 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, 1936 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, 1937 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, 1938 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ 1939 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ 1940 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, 1941 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, 1942 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY }, 1943 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, 1944 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, 1945 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, 1946 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, 1947 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, 1948 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, 1949 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, 1950 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, 1951 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, 1952 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, 1953 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, 1954 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, 1955 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, 1956 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, 1957 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, 1958 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, 1959 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, 1960 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, 1961 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ 1962 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ 1963 }; 1964 /* Associate command to an index in the 'handlers' array */ 1965 static uint8_t command_to_handler[256]; 1966 1967 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) 1968 { 1969 FDrive *cur_drv; 1970 int pos; 1971 1972 /* Reset mode */ 1973 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1974 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1975 return; 1976 } 1977 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { 1978 FLOPPY_DPRINTF("error: controller not ready for writing\n"); 1979 return; 1980 } 1981 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1982 /* Is it write command time ? */ 1983 if (fdctrl->msr & FD_MSR_NONDMA) { 1984 /* FIFO data write */ 1985 pos = fdctrl->data_pos++; 1986 pos %= FD_SECTOR_LEN; 1987 fdctrl->fifo[pos] = value; 1988 if (pos == FD_SECTOR_LEN - 1 || 1989 fdctrl->data_pos == fdctrl->data_len) { 1990 cur_drv = get_cur_drv(fdctrl); 1991 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1992 FLOPPY_DPRINTF("error writing sector %d\n", 1993 fd_sector(cur_drv)); 1994 return; 1995 } 1996 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1997 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1998 fd_sector(cur_drv)); 1999 return; 2000 } 2001 } 2002 /* Switch from transfer mode to status mode 2003 * then from status mode to command mode 2004 */ 2005 if (fdctrl->data_pos == fdctrl->data_len) 2006 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2007 return; 2008 } 2009 if (fdctrl->data_pos == 0) { 2010 /* Command */ 2011 pos = command_to_handler[value & 0xff]; 2012 FLOPPY_DPRINTF("%s command\n", handlers[pos].name); 2013 fdctrl->data_len = handlers[pos].parameters + 1; 2014 fdctrl->msr |= FD_MSR_CMDBUSY; 2015 } 2016 2017 FLOPPY_DPRINTF("%s: %02x\n", __func__, value); 2018 fdctrl->fifo[fdctrl->data_pos++] = value; 2019 if (fdctrl->data_pos == fdctrl->data_len) { 2020 /* We now have all parameters 2021 * and will be able to treat the command 2022 */ 2023 if (fdctrl->data_state & FD_STATE_FORMAT) { 2024 fdctrl_format_sector(fdctrl); 2025 return; 2026 } 2027 2028 pos = command_to_handler[fdctrl->fifo[0] & 0xff]; 2029 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name); 2030 (*handlers[pos].handler)(fdctrl, handlers[pos].direction); 2031 } 2032 } 2033 2034 static void fdctrl_result_timer(void *opaque) 2035 { 2036 FDCtrl *fdctrl = opaque; 2037 FDrive *cur_drv = get_cur_drv(fdctrl); 2038 2039 /* Pretend we are spinning. 2040 * This is needed for Coherent, which uses READ ID to check for 2041 * sector interleaving. 2042 */ 2043 if (cur_drv->last_sect != 0) { 2044 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; 2045 } 2046 /* READ_ID can't automatically succeed! */ 2047 if (fdctrl->check_media_rate && 2048 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 2049 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n", 2050 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 2051 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 2052 } else { 2053 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2054 } 2055 } 2056 2057 static void fdctrl_change_cb(void *opaque, bool load) 2058 { 2059 FDrive *drive = opaque; 2060 2061 drive->media_changed = 1; 2062 fd_revalidate(drive); 2063 } 2064 2065 static const BlockDevOps fdctrl_block_ops = { 2066 .change_media_cb = fdctrl_change_cb, 2067 }; 2068 2069 /* Init functions */ 2070 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp) 2071 { 2072 unsigned int i; 2073 FDrive *drive; 2074 2075 for (i = 0; i < MAX_FD; i++) { 2076 drive = &fdctrl->drives[i]; 2077 drive->fdctrl = fdctrl; 2078 2079 if (drive->bs) { 2080 if (bdrv_get_on_error(drive->bs, 0) != BLOCKDEV_ON_ERROR_ENOSPC) { 2081 error_setg(errp, "fdc doesn't support drive option werror"); 2082 return; 2083 } 2084 if (bdrv_get_on_error(drive->bs, 1) != BLOCKDEV_ON_ERROR_REPORT) { 2085 error_setg(errp, "fdc doesn't support drive option rerror"); 2086 return; 2087 } 2088 } 2089 2090 fd_init(drive); 2091 fdctrl_change_cb(drive, 0); 2092 if (drive->bs) { 2093 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive); 2094 } 2095 } 2096 } 2097 2098 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds) 2099 { 2100 DeviceState *dev; 2101 ISADevice *isadev; 2102 2103 isadev = isa_try_create(bus, TYPE_ISA_FDC); 2104 if (!isadev) { 2105 return NULL; 2106 } 2107 dev = DEVICE(isadev); 2108 2109 if (fds[0]) { 2110 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv); 2111 } 2112 if (fds[1]) { 2113 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv); 2114 } 2115 qdev_init_nofail(dev); 2116 2117 return isadev; 2118 } 2119 2120 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, 2121 hwaddr mmio_base, DriveInfo **fds) 2122 { 2123 FDCtrl *fdctrl; 2124 DeviceState *dev; 2125 SysBusDevice *sbd; 2126 FDCtrlSysBus *sys; 2127 2128 dev = qdev_create(NULL, "sysbus-fdc"); 2129 sys = SYSBUS_FDC(dev); 2130 fdctrl = &sys->state; 2131 fdctrl->dma_chann = dma_chann; /* FIXME */ 2132 if (fds[0]) { 2133 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv); 2134 } 2135 if (fds[1]) { 2136 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv); 2137 } 2138 qdev_init_nofail(dev); 2139 sbd = SYS_BUS_DEVICE(dev); 2140 sysbus_connect_irq(sbd, 0, irq); 2141 sysbus_mmio_map(sbd, 0, mmio_base); 2142 } 2143 2144 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, 2145 DriveInfo **fds, qemu_irq *fdc_tc) 2146 { 2147 DeviceState *dev; 2148 FDCtrlSysBus *sys; 2149 2150 dev = qdev_create(NULL, "SUNW,fdtwo"); 2151 if (fds[0]) { 2152 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv); 2153 } 2154 qdev_init_nofail(dev); 2155 sys = SYSBUS_FDC(dev); 2156 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); 2157 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base); 2158 *fdc_tc = qdev_get_gpio_in(dev, 0); 2159 } 2160 2161 static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp) 2162 { 2163 int i, j; 2164 static int command_tables_inited = 0; 2165 2166 /* Fill 'command_to_handler' lookup table */ 2167 if (!command_tables_inited) { 2168 command_tables_inited = 1; 2169 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { 2170 for (j = 0; j < sizeof(command_to_handler); j++) { 2171 if ((j & handlers[i].mask) == handlers[i].value) { 2172 command_to_handler[j] = i; 2173 } 2174 } 2175 } 2176 } 2177 2178 FLOPPY_DPRINTF("init controller\n"); 2179 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); 2180 fdctrl->fifo_size = 512; 2181 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2182 fdctrl_result_timer, fdctrl); 2183 2184 fdctrl->version = 0x90; /* Intel 82078 controller */ 2185 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ 2186 fdctrl->num_floppies = MAX_FD; 2187 2188 if (fdctrl->dma_chann != -1) { 2189 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl); 2190 } 2191 fdctrl_connect_drives(fdctrl, errp); 2192 } 2193 2194 static const MemoryRegionPortio fdc_portio_list[] = { 2195 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, 2196 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, 2197 PORTIO_END_OF_LIST(), 2198 }; 2199 2200 static void isabus_fdc_realize(DeviceState *dev, Error **errp) 2201 { 2202 ISADevice *isadev = ISA_DEVICE(dev); 2203 FDCtrlISABus *isa = ISA_FDC(dev); 2204 FDCtrl *fdctrl = &isa->state; 2205 Error *err = NULL; 2206 2207 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl, 2208 "fdc"); 2209 2210 isa_init_irq(isadev, &fdctrl->irq, isa->irq); 2211 fdctrl->dma_chann = isa->dma; 2212 2213 qdev_set_legacy_instance_id(dev, isa->iobase, 2); 2214 fdctrl_realize_common(fdctrl, &err); 2215 if (err != NULL) { 2216 error_propagate(errp, err); 2217 return; 2218 } 2219 2220 add_boot_device_path(isa->bootindexA, dev, "/floppy@0"); 2221 add_boot_device_path(isa->bootindexB, dev, "/floppy@1"); 2222 } 2223 2224 static void sysbus_fdc_initfn(Object *obj) 2225 { 2226 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2227 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2228 FDCtrl *fdctrl = &sys->state; 2229 2230 fdctrl->dma_chann = -1; 2231 2232 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl, 2233 "fdc", 0x08); 2234 sysbus_init_mmio(sbd, &fdctrl->iomem); 2235 } 2236 2237 static void sun4m_fdc_initfn(Object *obj) 2238 { 2239 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2240 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2241 FDCtrl *fdctrl = &sys->state; 2242 2243 fdctrl->sun4m = 1; 2244 2245 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops, 2246 fdctrl, "fdctrl", 0x08); 2247 sysbus_init_mmio(sbd, &fdctrl->iomem); 2248 } 2249 2250 static void sysbus_fdc_common_initfn(Object *obj) 2251 { 2252 DeviceState *dev = DEVICE(obj); 2253 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 2254 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2255 FDCtrl *fdctrl = &sys->state; 2256 2257 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */ 2258 2259 sysbus_init_irq(sbd, &fdctrl->irq); 2260 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1); 2261 } 2262 2263 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp) 2264 { 2265 FDCtrlSysBus *sys = SYSBUS_FDC(dev); 2266 FDCtrl *fdctrl = &sys->state; 2267 2268 fdctrl_realize_common(fdctrl, errp); 2269 } 2270 2271 FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i) 2272 { 2273 FDCtrlISABus *isa = ISA_FDC(fdc); 2274 2275 return isa->state.drives[i].drive; 2276 } 2277 2278 static const VMStateDescription vmstate_isa_fdc ={ 2279 .name = "fdc", 2280 .version_id = 2, 2281 .minimum_version_id = 2, 2282 .fields = (VMStateField[]) { 2283 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl), 2284 VMSTATE_END_OF_LIST() 2285 } 2286 }; 2287 2288 static Property isa_fdc_properties[] = { 2289 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0), 2290 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6), 2291 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2), 2292 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs), 2293 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs), 2294 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1), 2295 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1), 2296 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate, 2297 0, true), 2298 DEFINE_PROP_END_OF_LIST(), 2299 }; 2300 2301 static void isabus_fdc_class_init(ObjectClass *klass, void *data) 2302 { 2303 DeviceClass *dc = DEVICE_CLASS(klass); 2304 2305 dc->realize = isabus_fdc_realize; 2306 dc->fw_name = "fdc"; 2307 dc->reset = fdctrl_external_reset_isa; 2308 dc->vmsd = &vmstate_isa_fdc; 2309 dc->props = isa_fdc_properties; 2310 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2311 } 2312 2313 static const TypeInfo isa_fdc_info = { 2314 .name = TYPE_ISA_FDC, 2315 .parent = TYPE_ISA_DEVICE, 2316 .instance_size = sizeof(FDCtrlISABus), 2317 .class_init = isabus_fdc_class_init, 2318 }; 2319 2320 static const VMStateDescription vmstate_sysbus_fdc ={ 2321 .name = "fdc", 2322 .version_id = 2, 2323 .minimum_version_id = 2, 2324 .fields = (VMStateField[]) { 2325 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl), 2326 VMSTATE_END_OF_LIST() 2327 } 2328 }; 2329 2330 static Property sysbus_fdc_properties[] = { 2331 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs), 2332 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs), 2333 DEFINE_PROP_END_OF_LIST(), 2334 }; 2335 2336 static void sysbus_fdc_class_init(ObjectClass *klass, void *data) 2337 { 2338 DeviceClass *dc = DEVICE_CLASS(klass); 2339 2340 dc->props = sysbus_fdc_properties; 2341 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2342 } 2343 2344 static const TypeInfo sysbus_fdc_info = { 2345 .name = "sysbus-fdc", 2346 .parent = TYPE_SYSBUS_FDC, 2347 .instance_init = sysbus_fdc_initfn, 2348 .class_init = sysbus_fdc_class_init, 2349 }; 2350 2351 static Property sun4m_fdc_properties[] = { 2352 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs), 2353 DEFINE_PROP_END_OF_LIST(), 2354 }; 2355 2356 static void sun4m_fdc_class_init(ObjectClass *klass, void *data) 2357 { 2358 DeviceClass *dc = DEVICE_CLASS(klass); 2359 2360 dc->props = sun4m_fdc_properties; 2361 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2362 } 2363 2364 static const TypeInfo sun4m_fdc_info = { 2365 .name = "SUNW,fdtwo", 2366 .parent = TYPE_SYSBUS_FDC, 2367 .instance_init = sun4m_fdc_initfn, 2368 .class_init = sun4m_fdc_class_init, 2369 }; 2370 2371 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data) 2372 { 2373 DeviceClass *dc = DEVICE_CLASS(klass); 2374 2375 dc->realize = sysbus_fdc_common_realize; 2376 dc->reset = fdctrl_external_reset_sysbus; 2377 dc->vmsd = &vmstate_sysbus_fdc; 2378 } 2379 2380 static const TypeInfo sysbus_fdc_type_info = { 2381 .name = TYPE_SYSBUS_FDC, 2382 .parent = TYPE_SYS_BUS_DEVICE, 2383 .instance_size = sizeof(FDCtrlSysBus), 2384 .instance_init = sysbus_fdc_common_initfn, 2385 .abstract = true, 2386 .class_init = sysbus_fdc_common_class_init, 2387 }; 2388 2389 static void fdc_register_types(void) 2390 { 2391 type_register_static(&isa_fdc_info); 2392 type_register_static(&sysbus_fdc_type_info); 2393 type_register_static(&sysbus_fdc_info); 2394 type_register_static(&sun4m_fdc_info); 2395 } 2396 2397 type_init(fdc_register_types) 2398