1 /* 2 * QEMU Floppy disk emulator (Intel 82078) 3 * 4 * Copyright (c) 2003, 2007 Jocelyn Mayer 5 * Copyright (c) 2008 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * The controller is used in Sun4m systems in a slightly different 27 * way. There are changes in DOR register and DMA is not available. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/block/fdc.h" 33 #include "qapi/error.h" 34 #include "qemu/error-report.h" 35 #include "qemu/timer.h" 36 #include "hw/isa/isa.h" 37 #include "hw/sysbus.h" 38 #include "hw/block/block.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/blockdev.h" 41 #include "sysemu/sysemu.h" 42 #include "qemu/log.h" 43 #include "qemu/module.h" 44 #include "trace.h" 45 46 /********************************************************/ 47 /* debug Floppy devices */ 48 49 #define DEBUG_FLOPPY 0 50 51 #define FLOPPY_DPRINTF(fmt, ...) \ 52 do { \ 53 if (DEBUG_FLOPPY) { \ 54 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \ 55 } \ 56 } while (0) 57 58 59 /********************************************************/ 60 /* qdev floppy bus */ 61 62 #define TYPE_FLOPPY_BUS "floppy-bus" 63 #define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS) 64 65 typedef struct FDCtrl FDCtrl; 66 typedef struct FDrive FDrive; 67 static FDrive *get_drv(FDCtrl *fdctrl, int unit); 68 69 typedef struct FloppyBus { 70 BusState bus; 71 FDCtrl *fdc; 72 } FloppyBus; 73 74 static const TypeInfo floppy_bus_info = { 75 .name = TYPE_FLOPPY_BUS, 76 .parent = TYPE_BUS, 77 .instance_size = sizeof(FloppyBus), 78 }; 79 80 static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev) 81 { 82 qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL); 83 bus->fdc = fdc; 84 } 85 86 87 /********************************************************/ 88 /* Floppy drive emulation */ 89 90 typedef enum FDriveRate { 91 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */ 92 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */ 93 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */ 94 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */ 95 } FDriveRate; 96 97 typedef enum FDriveSize { 98 FDRIVE_SIZE_UNKNOWN, 99 FDRIVE_SIZE_350, 100 FDRIVE_SIZE_525, 101 } FDriveSize; 102 103 typedef struct FDFormat { 104 FloppyDriveType drive; 105 uint8_t last_sect; 106 uint8_t max_track; 107 uint8_t max_head; 108 FDriveRate rate; 109 } FDFormat; 110 111 /* In many cases, the total sector size of a format is enough to uniquely 112 * identify it. However, there are some total sector collisions between 113 * formats of different physical size, and these are noted below by 114 * highlighting the total sector size for entries with collisions. */ 115 static const FDFormat fd_formats[] = { 116 /* First entry is default format */ 117 /* 1.44 MB 3"1/2 floppy disks */ 118 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */ 119 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */ 120 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, }, 121 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, }, 122 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, }, 123 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, }, 124 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, }, 125 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, }, 126 /* 2.88 MB 3"1/2 floppy disks */ 127 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, }, 128 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, }, 129 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, }, 130 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, }, 131 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, }, 132 /* 720 kB 3"1/2 floppy disks */ 133 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */ 134 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, }, 135 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, }, 136 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, }, 137 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, }, 138 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, }, 139 /* 1.2 MB 5"1/4 floppy disks */ 140 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, }, 141 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */ 142 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, }, 143 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, }, 144 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */ 145 /* 720 kB 5"1/4 floppy disks */ 146 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */ 147 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, }, 148 /* 360 kB 5"1/4 floppy disks */ 149 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */ 150 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, }, 151 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, }, 152 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, }, 153 /* 320 kB 5"1/4 floppy disks */ 154 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, }, 155 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, }, 156 /* 360 kB must match 5"1/4 better than 3"1/2... */ 157 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */ 158 /* end */ 159 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, }, 160 }; 161 162 static FDriveSize drive_size(FloppyDriveType drive) 163 { 164 switch (drive) { 165 case FLOPPY_DRIVE_TYPE_120: 166 return FDRIVE_SIZE_525; 167 case FLOPPY_DRIVE_TYPE_144: 168 case FLOPPY_DRIVE_TYPE_288: 169 return FDRIVE_SIZE_350; 170 default: 171 return FDRIVE_SIZE_UNKNOWN; 172 } 173 } 174 175 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) 176 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) 177 178 /* Will always be a fixed parameter for us */ 179 #define FD_SECTOR_LEN 512 180 #define FD_SECTOR_SC 2 /* Sector size code */ 181 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ 182 183 /* Floppy disk drive emulation */ 184 typedef enum FDiskFlags { 185 FDISK_DBL_SIDES = 0x01, 186 } FDiskFlags; 187 188 struct FDrive { 189 FDCtrl *fdctrl; 190 BlockBackend *blk; 191 BlockConf *conf; 192 /* Drive status */ 193 FloppyDriveType drive; /* CMOS drive type */ 194 uint8_t perpendicular; /* 2.88 MB access mode */ 195 /* Position */ 196 uint8_t head; 197 uint8_t track; 198 uint8_t sect; 199 /* Media */ 200 FloppyDriveType disk; /* Current disk type */ 201 FDiskFlags flags; 202 uint8_t last_sect; /* Nb sector per track */ 203 uint8_t max_track; /* Nb of tracks */ 204 uint16_t bps; /* Bytes per sector */ 205 uint8_t ro; /* Is read-only */ 206 uint8_t media_changed; /* Is media changed */ 207 uint8_t media_rate; /* Data rate of medium */ 208 209 bool media_validated; /* Have we validated the media? */ 210 }; 211 212 213 static FloppyDriveType get_fallback_drive_type(FDrive *drv); 214 215 /* Hack: FD_SEEK is expected to work on empty drives. However, QEMU 216 * currently goes through some pains to keep seeks within the bounds 217 * established by last_sect and max_track. Correcting this is difficult, 218 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel. 219 * 220 * For now: allow empty drives to have large bounds so we can seek around, 221 * with the understanding that when a diskette is inserted, the bounds will 222 * properly tighten to match the geometry of that inserted medium. 223 */ 224 static void fd_empty_seek_hack(FDrive *drv) 225 { 226 drv->last_sect = 0xFF; 227 drv->max_track = 0xFF; 228 } 229 230 static void fd_init(FDrive *drv) 231 { 232 /* Drive */ 233 drv->perpendicular = 0; 234 /* Disk */ 235 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 236 drv->last_sect = 0; 237 drv->max_track = 0; 238 drv->ro = true; 239 drv->media_changed = 1; 240 } 241 242 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) 243 244 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, 245 uint8_t last_sect, uint8_t num_sides) 246 { 247 return (((track * num_sides) + head) * last_sect) + sect - 1; 248 } 249 250 /* Returns current position, in sectors, for given drive */ 251 static int fd_sector(FDrive *drv) 252 { 253 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, 254 NUM_SIDES(drv)); 255 } 256 257 /* Returns current position, in bytes, for given drive */ 258 static int fd_offset(FDrive *drv) 259 { 260 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS); 261 return fd_sector(drv) << BDRV_SECTOR_BITS; 262 } 263 264 /* Seek to a new position: 265 * returns 0 if already on right track 266 * returns 1 if track changed 267 * returns 2 if track is invalid 268 * returns 3 if sector is invalid 269 * returns 4 if seek is disabled 270 */ 271 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, 272 int enable_seek) 273 { 274 uint32_t sector; 275 int ret; 276 277 if (track > drv->max_track || 278 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { 279 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 280 head, track, sect, 1, 281 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 282 drv->max_track, drv->last_sect); 283 return 2; 284 } 285 if (sect > drv->last_sect) { 286 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 287 head, track, sect, 1, 288 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 289 drv->max_track, drv->last_sect); 290 return 3; 291 } 292 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); 293 ret = 0; 294 if (sector != fd_sector(drv)) { 295 #if 0 296 if (!enable_seek) { 297 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x" 298 " (max=%d %02x %02x)\n", 299 head, track, sect, 1, drv->max_track, 300 drv->last_sect); 301 return 4; 302 } 303 #endif 304 drv->head = head; 305 if (drv->track != track) { 306 if (drv->blk != NULL && blk_is_inserted(drv->blk)) { 307 drv->media_changed = 0; 308 } 309 ret = 1; 310 } 311 drv->track = track; 312 drv->sect = sect; 313 } 314 315 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) { 316 ret = 2; 317 } 318 319 return ret; 320 } 321 322 /* Set drive back to track 0 */ 323 static void fd_recalibrate(FDrive *drv) 324 { 325 FLOPPY_DPRINTF("recalibrate\n"); 326 fd_seek(drv, 0, 0, 1, 1); 327 } 328 329 /** 330 * Determine geometry based on inserted diskette. 331 * Will not operate on an empty drive. 332 * 333 * @return: 0 on success, -1 if the drive is empty. 334 */ 335 static int pick_geometry(FDrive *drv) 336 { 337 BlockBackend *blk = drv->blk; 338 const FDFormat *parse; 339 uint64_t nb_sectors, size; 340 int i; 341 int match, size_match, type_match; 342 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO; 343 344 /* We can only pick a geometry if we have a diskette. */ 345 if (!drv->blk || !blk_is_inserted(drv->blk) || 346 drv->drive == FLOPPY_DRIVE_TYPE_NONE) 347 { 348 return -1; 349 } 350 351 /* We need to determine the likely geometry of the inserted medium. 352 * In order of preference, we look for: 353 * (1) The same drive type and number of sectors, 354 * (2) The same diskette size and number of sectors, 355 * (3) The same drive type. 356 * 357 * In all cases, matches that occur higher in the drive table will take 358 * precedence over matches that occur later in the table. 359 */ 360 blk_get_geometry(blk, &nb_sectors); 361 match = size_match = type_match = -1; 362 for (i = 0; ; i++) { 363 parse = &fd_formats[i]; 364 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) { 365 break; 366 } 367 size = (parse->max_head + 1) * parse->max_track * parse->last_sect; 368 if (nb_sectors == size) { 369 if (magic || parse->drive == drv->drive) { 370 /* (1) perfect match -- nb_sectors and drive type */ 371 goto out; 372 } else if (drive_size(parse->drive) == drive_size(drv->drive)) { 373 /* (2) size match -- nb_sectors and physical medium size */ 374 match = (match == -1) ? i : match; 375 } else { 376 /* This is suspicious -- Did the user misconfigure? */ 377 size_match = (size_match == -1) ? i : size_match; 378 } 379 } else if (type_match == -1) { 380 if ((parse->drive == drv->drive) || 381 (magic && (parse->drive == get_fallback_drive_type(drv)))) { 382 /* (3) type match -- nb_sectors mismatch, but matches the type 383 * specified explicitly by the user, or matches the fallback 384 * default type when using the drive autodetect mechanism */ 385 type_match = i; 386 } 387 } 388 } 389 390 /* No exact match found */ 391 if (match == -1) { 392 if (size_match != -1) { 393 parse = &fd_formats[size_match]; 394 FLOPPY_DPRINTF("User requested floppy drive type '%s', " 395 "but inserted medium appears to be a " 396 "%"PRId64" sector '%s' type\n", 397 FloppyDriveType_str(drv->drive), 398 nb_sectors, 399 FloppyDriveType_str(parse->drive)); 400 } 401 assert(type_match != -1 && "misconfigured fd_format"); 402 match = type_match; 403 } 404 parse = &(fd_formats[match]); 405 406 out: 407 if (parse->max_head == 0) { 408 drv->flags &= ~FDISK_DBL_SIDES; 409 } else { 410 drv->flags |= FDISK_DBL_SIDES; 411 } 412 drv->max_track = parse->max_track; 413 drv->last_sect = parse->last_sect; 414 drv->disk = parse->drive; 415 drv->media_rate = parse->rate; 416 return 0; 417 } 418 419 static void pick_drive_type(FDrive *drv) 420 { 421 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) { 422 return; 423 } 424 425 if (pick_geometry(drv) == 0) { 426 drv->drive = drv->disk; 427 } else { 428 drv->drive = get_fallback_drive_type(drv); 429 } 430 431 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO); 432 } 433 434 /* Revalidate a disk drive after a disk change */ 435 static void fd_revalidate(FDrive *drv) 436 { 437 int rc; 438 439 FLOPPY_DPRINTF("revalidate\n"); 440 if (drv->blk != NULL) { 441 drv->ro = blk_is_read_only(drv->blk); 442 if (!blk_is_inserted(drv->blk)) { 443 FLOPPY_DPRINTF("No disk in drive\n"); 444 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 445 fd_empty_seek_hack(drv); 446 } else if (!drv->media_validated) { 447 rc = pick_geometry(drv); 448 if (rc) { 449 FLOPPY_DPRINTF("Could not validate floppy drive media"); 450 } else { 451 drv->media_validated = true; 452 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", 453 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1, 454 drv->max_track, drv->last_sect, 455 drv->ro ? "ro" : "rw"); 456 } 457 } 458 } else { 459 FLOPPY_DPRINTF("No drive connected\n"); 460 drv->last_sect = 0; 461 drv->max_track = 0; 462 drv->flags &= ~FDISK_DBL_SIDES; 463 drv->drive = FLOPPY_DRIVE_TYPE_NONE; 464 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 465 } 466 } 467 468 static void fd_change_cb(void *opaque, bool load, Error **errp) 469 { 470 FDrive *drive = opaque; 471 472 if (!load) { 473 blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort); 474 } else { 475 if (!blkconf_apply_backend_options(drive->conf, 476 blk_is_read_only(drive->blk), false, 477 errp)) { 478 return; 479 } 480 } 481 482 drive->media_changed = 1; 483 drive->media_validated = false; 484 fd_revalidate(drive); 485 } 486 487 static const BlockDevOps fd_block_ops = { 488 .change_media_cb = fd_change_cb, 489 }; 490 491 492 #define TYPE_FLOPPY_DRIVE "floppy" 493 #define FLOPPY_DRIVE(obj) \ 494 OBJECT_CHECK(FloppyDrive, (obj), TYPE_FLOPPY_DRIVE) 495 496 typedef struct FloppyDrive { 497 DeviceState qdev; 498 uint32_t unit; 499 BlockConf conf; 500 FloppyDriveType type; 501 } FloppyDrive; 502 503 static Property floppy_drive_properties[] = { 504 DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1), 505 DEFINE_BLOCK_PROPERTIES(FloppyDrive, conf), 506 DEFINE_PROP_SIGNED("drive-type", FloppyDrive, type, 507 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 508 FloppyDriveType), 509 DEFINE_PROP_END_OF_LIST(), 510 }; 511 512 static void floppy_drive_realize(DeviceState *qdev, Error **errp) 513 { 514 FloppyDrive *dev = FLOPPY_DRIVE(qdev); 515 FloppyBus *bus = FLOPPY_BUS(qdev->parent_bus); 516 FDrive *drive; 517 int ret; 518 519 if (dev->unit == -1) { 520 for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) { 521 drive = get_drv(bus->fdc, dev->unit); 522 if (!drive->blk) { 523 break; 524 } 525 } 526 } 527 528 if (dev->unit >= MAX_FD) { 529 error_setg(errp, "Can't create floppy unit %d, bus supports " 530 "only %d units", dev->unit, MAX_FD); 531 return; 532 } 533 534 drive = get_drv(bus->fdc, dev->unit); 535 if (drive->blk) { 536 error_setg(errp, "Floppy unit %d is in use", dev->unit); 537 return; 538 } 539 540 if (!dev->conf.blk) { 541 /* Anonymous BlockBackend for an empty drive */ 542 dev->conf.blk = blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL); 543 ret = blk_attach_dev(dev->conf.blk, qdev); 544 assert(ret == 0); 545 } 546 547 blkconf_blocksizes(&dev->conf); 548 if (dev->conf.logical_block_size != 512 || 549 dev->conf.physical_block_size != 512) 550 { 551 error_setg(errp, "Physical and logical block size must " 552 "be 512 for floppy"); 553 return; 554 } 555 556 /* rerror/werror aren't supported by fdc and therefore not even registered 557 * with qdev. So set the defaults manually before they are used in 558 * blkconf_apply_backend_options(). */ 559 dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO; 560 dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO; 561 562 if (!blkconf_apply_backend_options(&dev->conf, 563 blk_is_read_only(dev->conf.blk), 564 false, errp)) { 565 return; 566 } 567 568 /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us 569 * for empty drives. */ 570 if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC && 571 blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) { 572 error_setg(errp, "fdc doesn't support drive option werror"); 573 return; 574 } 575 if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) { 576 error_setg(errp, "fdc doesn't support drive option rerror"); 577 return; 578 } 579 580 drive->conf = &dev->conf; 581 drive->blk = dev->conf.blk; 582 drive->fdctrl = bus->fdc; 583 584 fd_init(drive); 585 blk_set_dev_ops(drive->blk, &fd_block_ops, drive); 586 587 /* Keep 'type' qdev property and FDrive->drive in sync */ 588 drive->drive = dev->type; 589 pick_drive_type(drive); 590 dev->type = drive->drive; 591 592 fd_revalidate(drive); 593 } 594 595 static void floppy_drive_class_init(ObjectClass *klass, void *data) 596 { 597 DeviceClass *k = DEVICE_CLASS(klass); 598 k->realize = floppy_drive_realize; 599 set_bit(DEVICE_CATEGORY_STORAGE, k->categories); 600 k->bus_type = TYPE_FLOPPY_BUS; 601 k->props = floppy_drive_properties; 602 k->desc = "virtual floppy drive"; 603 } 604 605 static const TypeInfo floppy_drive_info = { 606 .name = TYPE_FLOPPY_DRIVE, 607 .parent = TYPE_DEVICE, 608 .instance_size = sizeof(FloppyDrive), 609 .class_init = floppy_drive_class_init, 610 }; 611 612 /********************************************************/ 613 /* Intel 82078 floppy disk controller emulation */ 614 615 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); 616 static void fdctrl_to_command_phase(FDCtrl *fdctrl); 617 static int fdctrl_transfer_handler (void *opaque, int nchan, 618 int dma_pos, int dma_len); 619 static void fdctrl_raise_irq(FDCtrl *fdctrl); 620 static FDrive *get_cur_drv(FDCtrl *fdctrl); 621 622 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); 623 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); 624 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); 625 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); 626 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); 627 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); 628 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); 629 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); 630 static uint32_t fdctrl_read_data(FDCtrl *fdctrl); 631 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); 632 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); 633 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); 634 635 enum { 636 FD_DIR_WRITE = 0, 637 FD_DIR_READ = 1, 638 FD_DIR_SCANE = 2, 639 FD_DIR_SCANL = 3, 640 FD_DIR_SCANH = 4, 641 FD_DIR_VERIFY = 5, 642 }; 643 644 enum { 645 FD_STATE_MULTI = 0x01, /* multi track flag */ 646 FD_STATE_FORMAT = 0x02, /* format flag */ 647 }; 648 649 enum { 650 FD_REG_SRA = 0x00, 651 FD_REG_SRB = 0x01, 652 FD_REG_DOR = 0x02, 653 FD_REG_TDR = 0x03, 654 FD_REG_MSR = 0x04, 655 FD_REG_DSR = 0x04, 656 FD_REG_FIFO = 0x05, 657 FD_REG_DIR = 0x07, 658 FD_REG_CCR = 0x07, 659 }; 660 661 enum { 662 FD_CMD_READ_TRACK = 0x02, 663 FD_CMD_SPECIFY = 0x03, 664 FD_CMD_SENSE_DRIVE_STATUS = 0x04, 665 FD_CMD_WRITE = 0x05, 666 FD_CMD_READ = 0x06, 667 FD_CMD_RECALIBRATE = 0x07, 668 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, 669 FD_CMD_WRITE_DELETED = 0x09, 670 FD_CMD_READ_ID = 0x0a, 671 FD_CMD_READ_DELETED = 0x0c, 672 FD_CMD_FORMAT_TRACK = 0x0d, 673 FD_CMD_DUMPREG = 0x0e, 674 FD_CMD_SEEK = 0x0f, 675 FD_CMD_VERSION = 0x10, 676 FD_CMD_SCAN_EQUAL = 0x11, 677 FD_CMD_PERPENDICULAR_MODE = 0x12, 678 FD_CMD_CONFIGURE = 0x13, 679 FD_CMD_LOCK = 0x14, 680 FD_CMD_VERIFY = 0x16, 681 FD_CMD_POWERDOWN_MODE = 0x17, 682 FD_CMD_PART_ID = 0x18, 683 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, 684 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, 685 FD_CMD_SAVE = 0x2e, 686 FD_CMD_OPTION = 0x33, 687 FD_CMD_RESTORE = 0x4e, 688 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, 689 FD_CMD_RELATIVE_SEEK_OUT = 0x8f, 690 FD_CMD_FORMAT_AND_WRITE = 0xcd, 691 FD_CMD_RELATIVE_SEEK_IN = 0xcf, 692 }; 693 694 enum { 695 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ 696 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ 697 FD_CONFIG_POLL = 0x10, /* Poll enabled */ 698 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ 699 FD_CONFIG_EIS = 0x40, /* No implied seeks */ 700 }; 701 702 enum { 703 FD_SR0_DS0 = 0x01, 704 FD_SR0_DS1 = 0x02, 705 FD_SR0_HEAD = 0x04, 706 FD_SR0_EQPMT = 0x10, 707 FD_SR0_SEEK = 0x20, 708 FD_SR0_ABNTERM = 0x40, 709 FD_SR0_INVCMD = 0x80, 710 FD_SR0_RDYCHG = 0xc0, 711 }; 712 713 enum { 714 FD_SR1_MA = 0x01, /* Missing address mark */ 715 FD_SR1_NW = 0x02, /* Not writable */ 716 FD_SR1_EC = 0x80, /* End of cylinder */ 717 }; 718 719 enum { 720 FD_SR2_SNS = 0x04, /* Scan not satisfied */ 721 FD_SR2_SEH = 0x08, /* Scan equal hit */ 722 }; 723 724 enum { 725 FD_SRA_DIR = 0x01, 726 FD_SRA_nWP = 0x02, 727 FD_SRA_nINDX = 0x04, 728 FD_SRA_HDSEL = 0x08, 729 FD_SRA_nTRK0 = 0x10, 730 FD_SRA_STEP = 0x20, 731 FD_SRA_nDRV2 = 0x40, 732 FD_SRA_INTPEND = 0x80, 733 }; 734 735 enum { 736 FD_SRB_MTR0 = 0x01, 737 FD_SRB_MTR1 = 0x02, 738 FD_SRB_WGATE = 0x04, 739 FD_SRB_RDATA = 0x08, 740 FD_SRB_WDATA = 0x10, 741 FD_SRB_DR0 = 0x20, 742 }; 743 744 enum { 745 #if MAX_FD == 4 746 FD_DOR_SELMASK = 0x03, 747 #else 748 FD_DOR_SELMASK = 0x01, 749 #endif 750 FD_DOR_nRESET = 0x04, 751 FD_DOR_DMAEN = 0x08, 752 FD_DOR_MOTEN0 = 0x10, 753 FD_DOR_MOTEN1 = 0x20, 754 FD_DOR_MOTEN2 = 0x40, 755 FD_DOR_MOTEN3 = 0x80, 756 }; 757 758 enum { 759 #if MAX_FD == 4 760 FD_TDR_BOOTSEL = 0x0c, 761 #else 762 FD_TDR_BOOTSEL = 0x04, 763 #endif 764 }; 765 766 enum { 767 FD_DSR_DRATEMASK= 0x03, 768 FD_DSR_PWRDOWN = 0x40, 769 FD_DSR_SWRESET = 0x80, 770 }; 771 772 enum { 773 FD_MSR_DRV0BUSY = 0x01, 774 FD_MSR_DRV1BUSY = 0x02, 775 FD_MSR_DRV2BUSY = 0x04, 776 FD_MSR_DRV3BUSY = 0x08, 777 FD_MSR_CMDBUSY = 0x10, 778 FD_MSR_NONDMA = 0x20, 779 FD_MSR_DIO = 0x40, 780 FD_MSR_RQM = 0x80, 781 }; 782 783 enum { 784 FD_DIR_DSKCHG = 0x80, 785 }; 786 787 /* 788 * See chapter 5.0 "Controller phases" of the spec: 789 * 790 * Command phase: 791 * The host writes a command and its parameters into the FIFO. The command 792 * phase is completed when all parameters for the command have been supplied, 793 * and execution phase is entered. 794 * 795 * Execution phase: 796 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO 797 * contains the payload now, otherwise it's unused. When all bytes of the 798 * required data have been transferred, the state is switched to either result 799 * phase (if the command produces status bytes) or directly back into the 800 * command phase for the next command. 801 * 802 * Result phase: 803 * The host reads out the FIFO, which contains one or more result bytes now. 804 */ 805 enum { 806 /* Only for migration: reconstruct phase from registers like qemu 2.3 */ 807 FD_PHASE_RECONSTRUCT = 0, 808 809 FD_PHASE_COMMAND = 1, 810 FD_PHASE_EXECUTION = 2, 811 FD_PHASE_RESULT = 3, 812 }; 813 814 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) 815 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) 816 817 struct FDCtrl { 818 MemoryRegion iomem; 819 qemu_irq irq; 820 /* Controller state */ 821 QEMUTimer *result_timer; 822 int dma_chann; 823 uint8_t phase; 824 IsaDma *dma; 825 /* Controller's identification */ 826 uint8_t version; 827 /* HW */ 828 uint8_t sra; 829 uint8_t srb; 830 uint8_t dor; 831 uint8_t dor_vmstate; /* only used as temp during vmstate */ 832 uint8_t tdr; 833 uint8_t dsr; 834 uint8_t msr; 835 uint8_t cur_drv; 836 uint8_t status0; 837 uint8_t status1; 838 uint8_t status2; 839 /* Command FIFO */ 840 uint8_t *fifo; 841 int32_t fifo_size; 842 uint32_t data_pos; 843 uint32_t data_len; 844 uint8_t data_state; 845 uint8_t data_dir; 846 uint8_t eot; /* last wanted sector */ 847 /* States kept only to be returned back */ 848 /* precompensation */ 849 uint8_t precomp_trk; 850 uint8_t config; 851 uint8_t lock; 852 /* Power down config (also with status regB access mode */ 853 uint8_t pwrd; 854 /* Floppy drives */ 855 FloppyBus bus; 856 uint8_t num_floppies; 857 FDrive drives[MAX_FD]; 858 struct { 859 BlockBackend *blk; 860 FloppyDriveType type; 861 } qdev_for_drives[MAX_FD]; 862 int reset_sensei; 863 uint32_t check_media_rate; 864 FloppyDriveType fallback; /* type=auto failure fallback */ 865 /* Timers state */ 866 uint8_t timer0; 867 uint8_t timer1; 868 PortioList portio_list; 869 }; 870 871 static FloppyDriveType get_fallback_drive_type(FDrive *drv) 872 { 873 return drv->fdctrl->fallback; 874 } 875 876 #define TYPE_SYSBUS_FDC "base-sysbus-fdc" 877 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC) 878 879 typedef struct FDCtrlSysBus { 880 /*< private >*/ 881 SysBusDevice parent_obj; 882 /*< public >*/ 883 884 struct FDCtrl state; 885 } FDCtrlSysBus; 886 887 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC) 888 889 typedef struct FDCtrlISABus { 890 ISADevice parent_obj; 891 892 uint32_t iobase; 893 uint32_t irq; 894 uint32_t dma; 895 struct FDCtrl state; 896 int32_t bootindexA; 897 int32_t bootindexB; 898 } FDCtrlISABus; 899 900 static uint32_t fdctrl_read (void *opaque, uint32_t reg) 901 { 902 FDCtrl *fdctrl = opaque; 903 uint32_t retval; 904 905 reg &= 7; 906 switch (reg) { 907 case FD_REG_SRA: 908 retval = fdctrl_read_statusA(fdctrl); 909 break; 910 case FD_REG_SRB: 911 retval = fdctrl_read_statusB(fdctrl); 912 break; 913 case FD_REG_DOR: 914 retval = fdctrl_read_dor(fdctrl); 915 break; 916 case FD_REG_TDR: 917 retval = fdctrl_read_tape(fdctrl); 918 break; 919 case FD_REG_MSR: 920 retval = fdctrl_read_main_status(fdctrl); 921 break; 922 case FD_REG_FIFO: 923 retval = fdctrl_read_data(fdctrl); 924 break; 925 case FD_REG_DIR: 926 retval = fdctrl_read_dir(fdctrl); 927 break; 928 default: 929 retval = (uint32_t)(-1); 930 break; 931 } 932 trace_fdc_ioport_read(reg, retval); 933 934 return retval; 935 } 936 937 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) 938 { 939 FDCtrl *fdctrl = opaque; 940 941 reg &= 7; 942 trace_fdc_ioport_write(reg, value); 943 switch (reg) { 944 case FD_REG_DOR: 945 fdctrl_write_dor(fdctrl, value); 946 break; 947 case FD_REG_TDR: 948 fdctrl_write_tape(fdctrl, value); 949 break; 950 case FD_REG_DSR: 951 fdctrl_write_rate(fdctrl, value); 952 break; 953 case FD_REG_FIFO: 954 fdctrl_write_data(fdctrl, value); 955 break; 956 case FD_REG_CCR: 957 fdctrl_write_ccr(fdctrl, value); 958 break; 959 default: 960 break; 961 } 962 } 963 964 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg, 965 unsigned ize) 966 { 967 return fdctrl_read(opaque, (uint32_t)reg); 968 } 969 970 static void fdctrl_write_mem (void *opaque, hwaddr reg, 971 uint64_t value, unsigned size) 972 { 973 fdctrl_write(opaque, (uint32_t)reg, value); 974 } 975 976 static const MemoryRegionOps fdctrl_mem_ops = { 977 .read = fdctrl_read_mem, 978 .write = fdctrl_write_mem, 979 .endianness = DEVICE_NATIVE_ENDIAN, 980 }; 981 982 static const MemoryRegionOps fdctrl_mem_strict_ops = { 983 .read = fdctrl_read_mem, 984 .write = fdctrl_write_mem, 985 .endianness = DEVICE_NATIVE_ENDIAN, 986 .valid = { 987 .min_access_size = 1, 988 .max_access_size = 1, 989 }, 990 }; 991 992 static bool fdrive_media_changed_needed(void *opaque) 993 { 994 FDrive *drive = opaque; 995 996 return (drive->blk != NULL && drive->media_changed != 1); 997 } 998 999 static const VMStateDescription vmstate_fdrive_media_changed = { 1000 .name = "fdrive/media_changed", 1001 .version_id = 1, 1002 .minimum_version_id = 1, 1003 .needed = fdrive_media_changed_needed, 1004 .fields = (VMStateField[]) { 1005 VMSTATE_UINT8(media_changed, FDrive), 1006 VMSTATE_END_OF_LIST() 1007 } 1008 }; 1009 1010 static bool fdrive_media_rate_needed(void *opaque) 1011 { 1012 FDrive *drive = opaque; 1013 1014 return drive->fdctrl->check_media_rate; 1015 } 1016 1017 static const VMStateDescription vmstate_fdrive_media_rate = { 1018 .name = "fdrive/media_rate", 1019 .version_id = 1, 1020 .minimum_version_id = 1, 1021 .needed = fdrive_media_rate_needed, 1022 .fields = (VMStateField[]) { 1023 VMSTATE_UINT8(media_rate, FDrive), 1024 VMSTATE_END_OF_LIST() 1025 } 1026 }; 1027 1028 static bool fdrive_perpendicular_needed(void *opaque) 1029 { 1030 FDrive *drive = opaque; 1031 1032 return drive->perpendicular != 0; 1033 } 1034 1035 static const VMStateDescription vmstate_fdrive_perpendicular = { 1036 .name = "fdrive/perpendicular", 1037 .version_id = 1, 1038 .minimum_version_id = 1, 1039 .needed = fdrive_perpendicular_needed, 1040 .fields = (VMStateField[]) { 1041 VMSTATE_UINT8(perpendicular, FDrive), 1042 VMSTATE_END_OF_LIST() 1043 } 1044 }; 1045 1046 static int fdrive_post_load(void *opaque, int version_id) 1047 { 1048 fd_revalidate(opaque); 1049 return 0; 1050 } 1051 1052 static const VMStateDescription vmstate_fdrive = { 1053 .name = "fdrive", 1054 .version_id = 1, 1055 .minimum_version_id = 1, 1056 .post_load = fdrive_post_load, 1057 .fields = (VMStateField[]) { 1058 VMSTATE_UINT8(head, FDrive), 1059 VMSTATE_UINT8(track, FDrive), 1060 VMSTATE_UINT8(sect, FDrive), 1061 VMSTATE_END_OF_LIST() 1062 }, 1063 .subsections = (const VMStateDescription*[]) { 1064 &vmstate_fdrive_media_changed, 1065 &vmstate_fdrive_media_rate, 1066 &vmstate_fdrive_perpendicular, 1067 NULL 1068 } 1069 }; 1070 1071 /* 1072 * Reconstructs the phase from register values according to the logic that was 1073 * implemented in qemu 2.3. This is the default value that is used if the phase 1074 * subsection is not present on migration. 1075 * 1076 * Don't change this function to reflect newer qemu versions, it is part of 1077 * the migration ABI. 1078 */ 1079 static int reconstruct_phase(FDCtrl *fdctrl) 1080 { 1081 if (fdctrl->msr & FD_MSR_NONDMA) { 1082 return FD_PHASE_EXECUTION; 1083 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) { 1084 /* qemu 2.3 disabled RQM only during DMA transfers */ 1085 return FD_PHASE_EXECUTION; 1086 } else if (fdctrl->msr & FD_MSR_DIO) { 1087 return FD_PHASE_RESULT; 1088 } else { 1089 return FD_PHASE_COMMAND; 1090 } 1091 } 1092 1093 static int fdc_pre_save(void *opaque) 1094 { 1095 FDCtrl *s = opaque; 1096 1097 s->dor_vmstate = s->dor | GET_CUR_DRV(s); 1098 1099 return 0; 1100 } 1101 1102 static int fdc_pre_load(void *opaque) 1103 { 1104 FDCtrl *s = opaque; 1105 s->phase = FD_PHASE_RECONSTRUCT; 1106 return 0; 1107 } 1108 1109 static int fdc_post_load(void *opaque, int version_id) 1110 { 1111 FDCtrl *s = opaque; 1112 1113 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); 1114 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; 1115 1116 if (s->phase == FD_PHASE_RECONSTRUCT) { 1117 s->phase = reconstruct_phase(s); 1118 } 1119 1120 return 0; 1121 } 1122 1123 static bool fdc_reset_sensei_needed(void *opaque) 1124 { 1125 FDCtrl *s = opaque; 1126 1127 return s->reset_sensei != 0; 1128 } 1129 1130 static const VMStateDescription vmstate_fdc_reset_sensei = { 1131 .name = "fdc/reset_sensei", 1132 .version_id = 1, 1133 .minimum_version_id = 1, 1134 .needed = fdc_reset_sensei_needed, 1135 .fields = (VMStateField[]) { 1136 VMSTATE_INT32(reset_sensei, FDCtrl), 1137 VMSTATE_END_OF_LIST() 1138 } 1139 }; 1140 1141 static bool fdc_result_timer_needed(void *opaque) 1142 { 1143 FDCtrl *s = opaque; 1144 1145 return timer_pending(s->result_timer); 1146 } 1147 1148 static const VMStateDescription vmstate_fdc_result_timer = { 1149 .name = "fdc/result_timer", 1150 .version_id = 1, 1151 .minimum_version_id = 1, 1152 .needed = fdc_result_timer_needed, 1153 .fields = (VMStateField[]) { 1154 VMSTATE_TIMER_PTR(result_timer, FDCtrl), 1155 VMSTATE_END_OF_LIST() 1156 } 1157 }; 1158 1159 static bool fdc_phase_needed(void *opaque) 1160 { 1161 FDCtrl *fdctrl = opaque; 1162 1163 return reconstruct_phase(fdctrl) != fdctrl->phase; 1164 } 1165 1166 static const VMStateDescription vmstate_fdc_phase = { 1167 .name = "fdc/phase", 1168 .version_id = 1, 1169 .minimum_version_id = 1, 1170 .needed = fdc_phase_needed, 1171 .fields = (VMStateField[]) { 1172 VMSTATE_UINT8(phase, FDCtrl), 1173 VMSTATE_END_OF_LIST() 1174 } 1175 }; 1176 1177 static const VMStateDescription vmstate_fdc = { 1178 .name = "fdc", 1179 .version_id = 2, 1180 .minimum_version_id = 2, 1181 .pre_save = fdc_pre_save, 1182 .pre_load = fdc_pre_load, 1183 .post_load = fdc_post_load, 1184 .fields = (VMStateField[]) { 1185 /* Controller State */ 1186 VMSTATE_UINT8(sra, FDCtrl), 1187 VMSTATE_UINT8(srb, FDCtrl), 1188 VMSTATE_UINT8(dor_vmstate, FDCtrl), 1189 VMSTATE_UINT8(tdr, FDCtrl), 1190 VMSTATE_UINT8(dsr, FDCtrl), 1191 VMSTATE_UINT8(msr, FDCtrl), 1192 VMSTATE_UINT8(status0, FDCtrl), 1193 VMSTATE_UINT8(status1, FDCtrl), 1194 VMSTATE_UINT8(status2, FDCtrl), 1195 /* Command FIFO */ 1196 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, 1197 uint8_t), 1198 VMSTATE_UINT32(data_pos, FDCtrl), 1199 VMSTATE_UINT32(data_len, FDCtrl), 1200 VMSTATE_UINT8(data_state, FDCtrl), 1201 VMSTATE_UINT8(data_dir, FDCtrl), 1202 VMSTATE_UINT8(eot, FDCtrl), 1203 /* States kept only to be returned back */ 1204 VMSTATE_UINT8(timer0, FDCtrl), 1205 VMSTATE_UINT8(timer1, FDCtrl), 1206 VMSTATE_UINT8(precomp_trk, FDCtrl), 1207 VMSTATE_UINT8(config, FDCtrl), 1208 VMSTATE_UINT8(lock, FDCtrl), 1209 VMSTATE_UINT8(pwrd, FDCtrl), 1210 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl, NULL), 1211 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, 1212 vmstate_fdrive, FDrive), 1213 VMSTATE_END_OF_LIST() 1214 }, 1215 .subsections = (const VMStateDescription*[]) { 1216 &vmstate_fdc_reset_sensei, 1217 &vmstate_fdc_result_timer, 1218 &vmstate_fdc_phase, 1219 NULL 1220 } 1221 }; 1222 1223 static void fdctrl_external_reset_sysbus(DeviceState *d) 1224 { 1225 FDCtrlSysBus *sys = SYSBUS_FDC(d); 1226 FDCtrl *s = &sys->state; 1227 1228 fdctrl_reset(s, 0); 1229 } 1230 1231 static void fdctrl_external_reset_isa(DeviceState *d) 1232 { 1233 FDCtrlISABus *isa = ISA_FDC(d); 1234 FDCtrl *s = &isa->state; 1235 1236 fdctrl_reset(s, 0); 1237 } 1238 1239 static void fdctrl_handle_tc(void *opaque, int irq, int level) 1240 { 1241 //FDCtrl *s = opaque; 1242 1243 if (level) { 1244 // XXX 1245 FLOPPY_DPRINTF("TC pulsed\n"); 1246 } 1247 } 1248 1249 /* Change IRQ state */ 1250 static void fdctrl_reset_irq(FDCtrl *fdctrl) 1251 { 1252 fdctrl->status0 = 0; 1253 if (!(fdctrl->sra & FD_SRA_INTPEND)) 1254 return; 1255 FLOPPY_DPRINTF("Reset interrupt\n"); 1256 qemu_set_irq(fdctrl->irq, 0); 1257 fdctrl->sra &= ~FD_SRA_INTPEND; 1258 } 1259 1260 static void fdctrl_raise_irq(FDCtrl *fdctrl) 1261 { 1262 if (!(fdctrl->sra & FD_SRA_INTPEND)) { 1263 qemu_set_irq(fdctrl->irq, 1); 1264 fdctrl->sra |= FD_SRA_INTPEND; 1265 } 1266 1267 fdctrl->reset_sensei = 0; 1268 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); 1269 } 1270 1271 /* Reset controller */ 1272 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) 1273 { 1274 int i; 1275 1276 FLOPPY_DPRINTF("reset controller\n"); 1277 fdctrl_reset_irq(fdctrl); 1278 /* Initialise controller */ 1279 fdctrl->sra = 0; 1280 fdctrl->srb = 0xc0; 1281 if (!fdctrl->drives[1].blk) { 1282 fdctrl->sra |= FD_SRA_nDRV2; 1283 } 1284 fdctrl->cur_drv = 0; 1285 fdctrl->dor = FD_DOR_nRESET; 1286 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; 1287 fdctrl->msr = FD_MSR_RQM; 1288 fdctrl->reset_sensei = 0; 1289 timer_del(fdctrl->result_timer); 1290 /* FIFO state */ 1291 fdctrl->data_pos = 0; 1292 fdctrl->data_len = 0; 1293 fdctrl->data_state = 0; 1294 fdctrl->data_dir = FD_DIR_WRITE; 1295 for (i = 0; i < MAX_FD; i++) 1296 fd_recalibrate(&fdctrl->drives[i]); 1297 fdctrl_to_command_phase(fdctrl); 1298 if (do_irq) { 1299 fdctrl->status0 |= FD_SR0_RDYCHG; 1300 fdctrl_raise_irq(fdctrl); 1301 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; 1302 } 1303 } 1304 1305 static inline FDrive *drv0(FDCtrl *fdctrl) 1306 { 1307 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; 1308 } 1309 1310 static inline FDrive *drv1(FDCtrl *fdctrl) 1311 { 1312 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) 1313 return &fdctrl->drives[1]; 1314 else 1315 return &fdctrl->drives[0]; 1316 } 1317 1318 #if MAX_FD == 4 1319 static inline FDrive *drv2(FDCtrl *fdctrl) 1320 { 1321 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) 1322 return &fdctrl->drives[2]; 1323 else 1324 return &fdctrl->drives[1]; 1325 } 1326 1327 static inline FDrive *drv3(FDCtrl *fdctrl) 1328 { 1329 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) 1330 return &fdctrl->drives[3]; 1331 else 1332 return &fdctrl->drives[2]; 1333 } 1334 #endif 1335 1336 static FDrive *get_drv(FDCtrl *fdctrl, int unit) 1337 { 1338 switch (unit) { 1339 case 0: return drv0(fdctrl); 1340 case 1: return drv1(fdctrl); 1341 #if MAX_FD == 4 1342 case 2: return drv2(fdctrl); 1343 case 3: return drv3(fdctrl); 1344 #endif 1345 default: return NULL; 1346 } 1347 } 1348 1349 static FDrive *get_cur_drv(FDCtrl *fdctrl) 1350 { 1351 return get_drv(fdctrl, fdctrl->cur_drv); 1352 } 1353 1354 /* Status A register : 0x00 (read-only) */ 1355 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) 1356 { 1357 uint32_t retval = fdctrl->sra; 1358 1359 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); 1360 1361 return retval; 1362 } 1363 1364 /* Status B register : 0x01 (read-only) */ 1365 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) 1366 { 1367 uint32_t retval = fdctrl->srb; 1368 1369 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); 1370 1371 return retval; 1372 } 1373 1374 /* Digital output register : 0x02 */ 1375 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) 1376 { 1377 uint32_t retval = fdctrl->dor; 1378 1379 /* Selected drive */ 1380 retval |= fdctrl->cur_drv; 1381 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); 1382 1383 return retval; 1384 } 1385 1386 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) 1387 { 1388 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); 1389 1390 /* Motors */ 1391 if (value & FD_DOR_MOTEN0) 1392 fdctrl->srb |= FD_SRB_MTR0; 1393 else 1394 fdctrl->srb &= ~FD_SRB_MTR0; 1395 if (value & FD_DOR_MOTEN1) 1396 fdctrl->srb |= FD_SRB_MTR1; 1397 else 1398 fdctrl->srb &= ~FD_SRB_MTR1; 1399 1400 /* Drive */ 1401 if (value & 1) 1402 fdctrl->srb |= FD_SRB_DR0; 1403 else 1404 fdctrl->srb &= ~FD_SRB_DR0; 1405 1406 /* Reset */ 1407 if (!(value & FD_DOR_nRESET)) { 1408 if (fdctrl->dor & FD_DOR_nRESET) { 1409 FLOPPY_DPRINTF("controller enter RESET state\n"); 1410 } 1411 } else { 1412 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1413 FLOPPY_DPRINTF("controller out of RESET state\n"); 1414 fdctrl_reset(fdctrl, 1); 1415 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1416 } 1417 } 1418 /* Selected drive */ 1419 fdctrl->cur_drv = value & FD_DOR_SELMASK; 1420 1421 fdctrl->dor = value; 1422 } 1423 1424 /* Tape drive register : 0x03 */ 1425 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) 1426 { 1427 uint32_t retval = fdctrl->tdr; 1428 1429 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); 1430 1431 return retval; 1432 } 1433 1434 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) 1435 { 1436 /* Reset mode */ 1437 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1438 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1439 return; 1440 } 1441 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); 1442 /* Disk boot selection indicator */ 1443 fdctrl->tdr = value & FD_TDR_BOOTSEL; 1444 /* Tape indicators: never allow */ 1445 } 1446 1447 /* Main status register : 0x04 (read) */ 1448 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) 1449 { 1450 uint32_t retval = fdctrl->msr; 1451 1452 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1453 fdctrl->dor |= FD_DOR_nRESET; 1454 1455 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); 1456 1457 return retval; 1458 } 1459 1460 /* Data select rate register : 0x04 (write) */ 1461 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) 1462 { 1463 /* Reset mode */ 1464 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1465 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1466 return; 1467 } 1468 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); 1469 /* Reset: autoclear */ 1470 if (value & FD_DSR_SWRESET) { 1471 fdctrl->dor &= ~FD_DOR_nRESET; 1472 fdctrl_reset(fdctrl, 1); 1473 fdctrl->dor |= FD_DOR_nRESET; 1474 } 1475 if (value & FD_DSR_PWRDOWN) { 1476 fdctrl_reset(fdctrl, 1); 1477 } 1478 fdctrl->dsr = value; 1479 } 1480 1481 /* Configuration control register: 0x07 (write) */ 1482 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) 1483 { 1484 /* Reset mode */ 1485 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1486 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1487 return; 1488 } 1489 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); 1490 1491 /* Only the rate selection bits used in AT mode, and we 1492 * store those in the DSR. 1493 */ 1494 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | 1495 (value & FD_DSR_DRATEMASK); 1496 } 1497 1498 static int fdctrl_media_changed(FDrive *drv) 1499 { 1500 return drv->media_changed; 1501 } 1502 1503 /* Digital input register : 0x07 (read-only) */ 1504 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) 1505 { 1506 uint32_t retval = 0; 1507 1508 if (fdctrl_media_changed(get_cur_drv(fdctrl))) { 1509 retval |= FD_DIR_DSKCHG; 1510 } 1511 if (retval != 0) { 1512 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); 1513 } 1514 1515 return retval; 1516 } 1517 1518 /* Clear the FIFO and update the state for receiving the next command */ 1519 static void fdctrl_to_command_phase(FDCtrl *fdctrl) 1520 { 1521 fdctrl->phase = FD_PHASE_COMMAND; 1522 fdctrl->data_dir = FD_DIR_WRITE; 1523 fdctrl->data_pos = 0; 1524 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */ 1525 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); 1526 fdctrl->msr |= FD_MSR_RQM; 1527 } 1528 1529 /* Update the state to allow the guest to read out the command status. 1530 * @fifo_len is the number of result bytes to be read out. */ 1531 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len) 1532 { 1533 fdctrl->phase = FD_PHASE_RESULT; 1534 fdctrl->data_dir = FD_DIR_READ; 1535 fdctrl->data_len = fifo_len; 1536 fdctrl->data_pos = 0; 1537 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; 1538 } 1539 1540 /* Set an error: unimplemented/unknown command */ 1541 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) 1542 { 1543 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n", 1544 fdctrl->fifo[0]); 1545 fdctrl->fifo[0] = FD_SR0_INVCMD; 1546 fdctrl_to_result_phase(fdctrl, 1); 1547 } 1548 1549 /* Seek to next sector 1550 * returns 0 when end of track reached (for DBL_SIDES on head 1) 1551 * otherwise returns 1 1552 */ 1553 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) 1554 { 1555 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", 1556 cur_drv->head, cur_drv->track, cur_drv->sect, 1557 fd_sector(cur_drv)); 1558 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an 1559 error in fact */ 1560 uint8_t new_head = cur_drv->head; 1561 uint8_t new_track = cur_drv->track; 1562 uint8_t new_sect = cur_drv->sect; 1563 1564 int ret = 1; 1565 1566 if (new_sect >= cur_drv->last_sect || 1567 new_sect == fdctrl->eot) { 1568 new_sect = 1; 1569 if (FD_MULTI_TRACK(fdctrl->data_state)) { 1570 if (new_head == 0 && 1571 (cur_drv->flags & FDISK_DBL_SIDES) != 0) { 1572 new_head = 1; 1573 } else { 1574 new_head = 0; 1575 new_track++; 1576 fdctrl->status0 |= FD_SR0_SEEK; 1577 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) { 1578 ret = 0; 1579 } 1580 } 1581 } else { 1582 fdctrl->status0 |= FD_SR0_SEEK; 1583 new_track++; 1584 ret = 0; 1585 } 1586 if (ret == 1) { 1587 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", 1588 new_head, new_track, new_sect, fd_sector(cur_drv)); 1589 } 1590 } else { 1591 new_sect++; 1592 } 1593 fd_seek(cur_drv, new_head, new_track, new_sect, 1); 1594 return ret; 1595 } 1596 1597 /* Callback for transfer end (stop or abort) */ 1598 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, 1599 uint8_t status1, uint8_t status2) 1600 { 1601 FDrive *cur_drv; 1602 cur_drv = get_cur_drv(fdctrl); 1603 1604 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD); 1605 fdctrl->status0 |= GET_CUR_DRV(fdctrl); 1606 if (cur_drv->head) { 1607 fdctrl->status0 |= FD_SR0_HEAD; 1608 } 1609 fdctrl->status0 |= status0; 1610 1611 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", 1612 status0, status1, status2, fdctrl->status0); 1613 fdctrl->fifo[0] = fdctrl->status0; 1614 fdctrl->fifo[1] = status1; 1615 fdctrl->fifo[2] = status2; 1616 fdctrl->fifo[3] = cur_drv->track; 1617 fdctrl->fifo[4] = cur_drv->head; 1618 fdctrl->fifo[5] = cur_drv->sect; 1619 fdctrl->fifo[6] = FD_SECTOR_SC; 1620 fdctrl->data_dir = FD_DIR_READ; 1621 if (fdctrl->dma_chann != -1 && !(fdctrl->msr & FD_MSR_NONDMA)) { 1622 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma); 1623 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann); 1624 } 1625 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 1626 fdctrl->msr &= ~FD_MSR_NONDMA; 1627 1628 fdctrl_to_result_phase(fdctrl, 7); 1629 fdctrl_raise_irq(fdctrl); 1630 } 1631 1632 /* Prepare a data transfer (either DMA or FIFO) */ 1633 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) 1634 { 1635 FDrive *cur_drv; 1636 uint8_t kh, kt, ks; 1637 1638 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1639 cur_drv = get_cur_drv(fdctrl); 1640 kt = fdctrl->fifo[2]; 1641 kh = fdctrl->fifo[3]; 1642 ks = fdctrl->fifo[4]; 1643 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", 1644 GET_CUR_DRV(fdctrl), kh, kt, ks, 1645 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1646 NUM_SIDES(cur_drv))); 1647 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1648 case 2: 1649 /* sect too big */ 1650 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1651 fdctrl->fifo[3] = kt; 1652 fdctrl->fifo[4] = kh; 1653 fdctrl->fifo[5] = ks; 1654 return; 1655 case 3: 1656 /* track too big */ 1657 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1658 fdctrl->fifo[3] = kt; 1659 fdctrl->fifo[4] = kh; 1660 fdctrl->fifo[5] = ks; 1661 return; 1662 case 4: 1663 /* No seek enabled */ 1664 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1665 fdctrl->fifo[3] = kt; 1666 fdctrl->fifo[4] = kh; 1667 fdctrl->fifo[5] = ks; 1668 return; 1669 case 1: 1670 fdctrl->status0 |= FD_SR0_SEEK; 1671 break; 1672 default: 1673 break; 1674 } 1675 1676 /* Check the data rate. If the programmed data rate does not match 1677 * the currently inserted medium, the operation has to fail. */ 1678 if (fdctrl->check_media_rate && 1679 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 1680 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n", 1681 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 1682 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 1683 fdctrl->fifo[3] = kt; 1684 fdctrl->fifo[4] = kh; 1685 fdctrl->fifo[5] = ks; 1686 return; 1687 } 1688 1689 /* Set the FIFO state */ 1690 fdctrl->data_dir = direction; 1691 fdctrl->data_pos = 0; 1692 assert(fdctrl->msr & FD_MSR_CMDBUSY); 1693 if (fdctrl->fifo[0] & 0x80) 1694 fdctrl->data_state |= FD_STATE_MULTI; 1695 else 1696 fdctrl->data_state &= ~FD_STATE_MULTI; 1697 if (fdctrl->fifo[5] == 0) { 1698 fdctrl->data_len = fdctrl->fifo[8]; 1699 } else { 1700 int tmp; 1701 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); 1702 tmp = (fdctrl->fifo[6] - ks + 1); 1703 if (fdctrl->fifo[0] & 0x80) 1704 tmp += fdctrl->fifo[6]; 1705 fdctrl->data_len *= tmp; 1706 } 1707 fdctrl->eot = fdctrl->fifo[6]; 1708 if (fdctrl->dor & FD_DOR_DMAEN) { 1709 IsaDmaTransferMode dma_mode; 1710 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma); 1711 bool dma_mode_ok; 1712 /* DMA transfer are enabled. Check if DMA channel is well programmed */ 1713 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann); 1714 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", 1715 dma_mode, direction, 1716 (128 << fdctrl->fifo[5]) * 1717 (cur_drv->last_sect - ks + 1), fdctrl->data_len); 1718 switch (direction) { 1719 case FD_DIR_SCANE: 1720 case FD_DIR_SCANL: 1721 case FD_DIR_SCANH: 1722 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY); 1723 break; 1724 case FD_DIR_WRITE: 1725 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE); 1726 break; 1727 case FD_DIR_READ: 1728 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ); 1729 break; 1730 case FD_DIR_VERIFY: 1731 dma_mode_ok = true; 1732 break; 1733 default: 1734 dma_mode_ok = false; 1735 break; 1736 } 1737 if (dma_mode_ok) { 1738 /* No access is allowed until DMA transfer has completed */ 1739 fdctrl->msr &= ~FD_MSR_RQM; 1740 if (direction != FD_DIR_VERIFY) { 1741 /* Now, we just have to wait for the DMA controller to 1742 * recall us... 1743 */ 1744 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann); 1745 k->schedule(fdctrl->dma); 1746 } else { 1747 /* Start transfer */ 1748 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, 1749 fdctrl->data_len); 1750 } 1751 return; 1752 } else { 1753 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode, 1754 direction); 1755 } 1756 } 1757 FLOPPY_DPRINTF("start non-DMA transfer\n"); 1758 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM; 1759 if (direction != FD_DIR_WRITE) 1760 fdctrl->msr |= FD_MSR_DIO; 1761 /* IO based transfer: calculate len */ 1762 fdctrl_raise_irq(fdctrl); 1763 } 1764 1765 /* Prepare a transfer of deleted data */ 1766 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) 1767 { 1768 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n"); 1769 1770 /* We don't handle deleted data, 1771 * so we don't return *ANYTHING* 1772 */ 1773 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1774 } 1775 1776 /* handlers for DMA transfers */ 1777 static int fdctrl_transfer_handler (void *opaque, int nchan, 1778 int dma_pos, int dma_len) 1779 { 1780 FDCtrl *fdctrl; 1781 FDrive *cur_drv; 1782 int len, start_pos, rel_pos; 1783 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; 1784 IsaDmaClass *k; 1785 1786 fdctrl = opaque; 1787 if (fdctrl->msr & FD_MSR_RQM) { 1788 FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); 1789 return 0; 1790 } 1791 k = ISADMA_GET_CLASS(fdctrl->dma); 1792 cur_drv = get_cur_drv(fdctrl); 1793 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || 1794 fdctrl->data_dir == FD_DIR_SCANH) 1795 status2 = FD_SR2_SNS; 1796 if (dma_len > fdctrl->data_len) 1797 dma_len = fdctrl->data_len; 1798 if (cur_drv->blk == NULL) { 1799 if (fdctrl->data_dir == FD_DIR_WRITE) 1800 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1801 else 1802 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1803 len = 0; 1804 goto transfer_error; 1805 } 1806 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1807 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { 1808 len = dma_len - fdctrl->data_pos; 1809 if (len + rel_pos > FD_SECTOR_LEN) 1810 len = FD_SECTOR_LEN - rel_pos; 1811 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " 1812 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, 1813 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, 1814 cur_drv->track, cur_drv->sect, fd_sector(cur_drv), 1815 fd_sector(cur_drv) * FD_SECTOR_LEN); 1816 if (fdctrl->data_dir != FD_DIR_WRITE || 1817 len < FD_SECTOR_LEN || rel_pos != 0) { 1818 /* READ & SCAN commands and realign to a sector for WRITE */ 1819 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), 1820 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) { 1821 FLOPPY_DPRINTF("Floppy: error getting sector %d\n", 1822 fd_sector(cur_drv)); 1823 /* Sure, image size is too small... */ 1824 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1825 } 1826 } 1827 switch (fdctrl->data_dir) { 1828 case FD_DIR_READ: 1829 /* READ commands */ 1830 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos, 1831 fdctrl->data_pos, len); 1832 break; 1833 case FD_DIR_WRITE: 1834 /* WRITE commands */ 1835 if (cur_drv->ro) { 1836 /* Handle readonly medium early, no need to do DMA, touch the 1837 * LED or attempt any writes. A real floppy doesn't attempt 1838 * to write to readonly media either. */ 1839 fdctrl_stop_transfer(fdctrl, 1840 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, 1841 0x00); 1842 goto transfer_error; 1843 } 1844 1845 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos, 1846 fdctrl->data_pos, len); 1847 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), 1848 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) { 1849 FLOPPY_DPRINTF("error writing sector %d\n", 1850 fd_sector(cur_drv)); 1851 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1852 goto transfer_error; 1853 } 1854 break; 1855 case FD_DIR_VERIFY: 1856 /* VERIFY commands */ 1857 break; 1858 default: 1859 /* SCAN commands */ 1860 { 1861 uint8_t tmpbuf[FD_SECTOR_LEN]; 1862 int ret; 1863 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos, 1864 len); 1865 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); 1866 if (ret == 0) { 1867 status2 = FD_SR2_SEH; 1868 goto end_transfer; 1869 } 1870 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || 1871 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { 1872 status2 = 0x00; 1873 goto end_transfer; 1874 } 1875 } 1876 break; 1877 } 1878 fdctrl->data_pos += len; 1879 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1880 if (rel_pos == 0) { 1881 /* Seek to next sector */ 1882 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) 1883 break; 1884 } 1885 } 1886 end_transfer: 1887 len = fdctrl->data_pos - start_pos; 1888 FLOPPY_DPRINTF("end transfer %d %d %d\n", 1889 fdctrl->data_pos, len, fdctrl->data_len); 1890 if (fdctrl->data_dir == FD_DIR_SCANE || 1891 fdctrl->data_dir == FD_DIR_SCANL || 1892 fdctrl->data_dir == FD_DIR_SCANH) 1893 status2 = FD_SR2_SEH; 1894 fdctrl->data_len -= len; 1895 fdctrl_stop_transfer(fdctrl, status0, status1, status2); 1896 transfer_error: 1897 1898 return len; 1899 } 1900 1901 /* Data register : 0x05 */ 1902 static uint32_t fdctrl_read_data(FDCtrl *fdctrl) 1903 { 1904 FDrive *cur_drv; 1905 uint32_t retval = 0; 1906 uint32_t pos; 1907 1908 cur_drv = get_cur_drv(fdctrl); 1909 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1910 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { 1911 FLOPPY_DPRINTF("error: controller not ready for reading\n"); 1912 return 0; 1913 } 1914 1915 /* If data_len spans multiple sectors, the current position in the FIFO 1916 * wraps around while fdctrl->data_pos is the real position in the whole 1917 * request. */ 1918 pos = fdctrl->data_pos; 1919 pos %= FD_SECTOR_LEN; 1920 1921 switch (fdctrl->phase) { 1922 case FD_PHASE_EXECUTION: 1923 assert(fdctrl->msr & FD_MSR_NONDMA); 1924 if (pos == 0) { 1925 if (fdctrl->data_pos != 0) 1926 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1927 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1928 fd_sector(cur_drv)); 1929 return 0; 1930 } 1931 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo, 1932 BDRV_SECTOR_SIZE) 1933 < 0) { 1934 FLOPPY_DPRINTF("error getting sector %d\n", 1935 fd_sector(cur_drv)); 1936 /* Sure, image size is too small... */ 1937 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1938 } 1939 } 1940 1941 if (++fdctrl->data_pos == fdctrl->data_len) { 1942 fdctrl->msr &= ~FD_MSR_RQM; 1943 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1944 } 1945 break; 1946 1947 case FD_PHASE_RESULT: 1948 assert(!(fdctrl->msr & FD_MSR_NONDMA)); 1949 if (++fdctrl->data_pos == fdctrl->data_len) { 1950 fdctrl->msr &= ~FD_MSR_RQM; 1951 fdctrl_to_command_phase(fdctrl); 1952 fdctrl_reset_irq(fdctrl); 1953 } 1954 break; 1955 1956 case FD_PHASE_COMMAND: 1957 default: 1958 abort(); 1959 } 1960 1961 retval = fdctrl->fifo[pos]; 1962 FLOPPY_DPRINTF("data register: 0x%02x\n", retval); 1963 1964 return retval; 1965 } 1966 1967 static void fdctrl_format_sector(FDCtrl *fdctrl) 1968 { 1969 FDrive *cur_drv; 1970 uint8_t kh, kt, ks; 1971 1972 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1973 cur_drv = get_cur_drv(fdctrl); 1974 kt = fdctrl->fifo[6]; 1975 kh = fdctrl->fifo[7]; 1976 ks = fdctrl->fifo[8]; 1977 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", 1978 GET_CUR_DRV(fdctrl), kh, kt, ks, 1979 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1980 NUM_SIDES(cur_drv))); 1981 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1982 case 2: 1983 /* sect too big */ 1984 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1985 fdctrl->fifo[3] = kt; 1986 fdctrl->fifo[4] = kh; 1987 fdctrl->fifo[5] = ks; 1988 return; 1989 case 3: 1990 /* track too big */ 1991 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1992 fdctrl->fifo[3] = kt; 1993 fdctrl->fifo[4] = kh; 1994 fdctrl->fifo[5] = ks; 1995 return; 1996 case 4: 1997 /* No seek enabled */ 1998 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1999 fdctrl->fifo[3] = kt; 2000 fdctrl->fifo[4] = kh; 2001 fdctrl->fifo[5] = ks; 2002 return; 2003 case 1: 2004 fdctrl->status0 |= FD_SR0_SEEK; 2005 break; 2006 default: 2007 break; 2008 } 2009 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 2010 if (cur_drv->blk == NULL || 2011 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo, 2012 BDRV_SECTOR_SIZE, 0) < 0) { 2013 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv)); 2014 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 2015 } else { 2016 if (cur_drv->sect == cur_drv->last_sect) { 2017 fdctrl->data_state &= ~FD_STATE_FORMAT; 2018 /* Last sector done */ 2019 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2020 } else { 2021 /* More to do */ 2022 fdctrl->data_pos = 0; 2023 fdctrl->data_len = 4; 2024 } 2025 } 2026 } 2027 2028 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) 2029 { 2030 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; 2031 fdctrl->fifo[0] = fdctrl->lock << 4; 2032 fdctrl_to_result_phase(fdctrl, 1); 2033 } 2034 2035 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) 2036 { 2037 FDrive *cur_drv = get_cur_drv(fdctrl); 2038 2039 /* Drives position */ 2040 fdctrl->fifo[0] = drv0(fdctrl)->track; 2041 fdctrl->fifo[1] = drv1(fdctrl)->track; 2042 #if MAX_FD == 4 2043 fdctrl->fifo[2] = drv2(fdctrl)->track; 2044 fdctrl->fifo[3] = drv3(fdctrl)->track; 2045 #else 2046 fdctrl->fifo[2] = 0; 2047 fdctrl->fifo[3] = 0; 2048 #endif 2049 /* timers */ 2050 fdctrl->fifo[4] = fdctrl->timer0; 2051 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); 2052 fdctrl->fifo[6] = cur_drv->last_sect; 2053 fdctrl->fifo[7] = (fdctrl->lock << 7) | 2054 (cur_drv->perpendicular << 2); 2055 fdctrl->fifo[8] = fdctrl->config; 2056 fdctrl->fifo[9] = fdctrl->precomp_trk; 2057 fdctrl_to_result_phase(fdctrl, 10); 2058 } 2059 2060 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) 2061 { 2062 /* Controller's version */ 2063 fdctrl->fifo[0] = fdctrl->version; 2064 fdctrl_to_result_phase(fdctrl, 1); 2065 } 2066 2067 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) 2068 { 2069 fdctrl->fifo[0] = 0x41; /* Stepping 1 */ 2070 fdctrl_to_result_phase(fdctrl, 1); 2071 } 2072 2073 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) 2074 { 2075 FDrive *cur_drv = get_cur_drv(fdctrl); 2076 2077 /* Drives position */ 2078 drv0(fdctrl)->track = fdctrl->fifo[3]; 2079 drv1(fdctrl)->track = fdctrl->fifo[4]; 2080 #if MAX_FD == 4 2081 drv2(fdctrl)->track = fdctrl->fifo[5]; 2082 drv3(fdctrl)->track = fdctrl->fifo[6]; 2083 #endif 2084 /* timers */ 2085 fdctrl->timer0 = fdctrl->fifo[7]; 2086 fdctrl->timer1 = fdctrl->fifo[8]; 2087 cur_drv->last_sect = fdctrl->fifo[9]; 2088 fdctrl->lock = fdctrl->fifo[10] >> 7; 2089 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; 2090 fdctrl->config = fdctrl->fifo[11]; 2091 fdctrl->precomp_trk = fdctrl->fifo[12]; 2092 fdctrl->pwrd = fdctrl->fifo[13]; 2093 fdctrl_to_command_phase(fdctrl); 2094 } 2095 2096 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) 2097 { 2098 FDrive *cur_drv = get_cur_drv(fdctrl); 2099 2100 fdctrl->fifo[0] = 0; 2101 fdctrl->fifo[1] = 0; 2102 /* Drives position */ 2103 fdctrl->fifo[2] = drv0(fdctrl)->track; 2104 fdctrl->fifo[3] = drv1(fdctrl)->track; 2105 #if MAX_FD == 4 2106 fdctrl->fifo[4] = drv2(fdctrl)->track; 2107 fdctrl->fifo[5] = drv3(fdctrl)->track; 2108 #else 2109 fdctrl->fifo[4] = 0; 2110 fdctrl->fifo[5] = 0; 2111 #endif 2112 /* timers */ 2113 fdctrl->fifo[6] = fdctrl->timer0; 2114 fdctrl->fifo[7] = fdctrl->timer1; 2115 fdctrl->fifo[8] = cur_drv->last_sect; 2116 fdctrl->fifo[9] = (fdctrl->lock << 7) | 2117 (cur_drv->perpendicular << 2); 2118 fdctrl->fifo[10] = fdctrl->config; 2119 fdctrl->fifo[11] = fdctrl->precomp_trk; 2120 fdctrl->fifo[12] = fdctrl->pwrd; 2121 fdctrl->fifo[13] = 0; 2122 fdctrl->fifo[14] = 0; 2123 fdctrl_to_result_phase(fdctrl, 15); 2124 } 2125 2126 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) 2127 { 2128 FDrive *cur_drv = get_cur_drv(fdctrl); 2129 2130 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 2131 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 2132 (NANOSECONDS_PER_SECOND / 50)); 2133 } 2134 2135 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) 2136 { 2137 FDrive *cur_drv; 2138 2139 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2140 cur_drv = get_cur_drv(fdctrl); 2141 fdctrl->data_state |= FD_STATE_FORMAT; 2142 if (fdctrl->fifo[0] & 0x80) 2143 fdctrl->data_state |= FD_STATE_MULTI; 2144 else 2145 fdctrl->data_state &= ~FD_STATE_MULTI; 2146 cur_drv->bps = 2147 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; 2148 #if 0 2149 cur_drv->last_sect = 2150 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : 2151 fdctrl->fifo[3] / 2; 2152 #else 2153 cur_drv->last_sect = fdctrl->fifo[3]; 2154 #endif 2155 /* TODO: implement format using DMA expected by the Bochs BIOS 2156 * and Linux fdformat (read 3 bytes per sector via DMA and fill 2157 * the sector with the specified fill byte 2158 */ 2159 fdctrl->data_state &= ~FD_STATE_FORMAT; 2160 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2161 } 2162 2163 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) 2164 { 2165 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; 2166 fdctrl->timer1 = fdctrl->fifo[2] >> 1; 2167 if (fdctrl->fifo[2] & 1) 2168 fdctrl->dor &= ~FD_DOR_DMAEN; 2169 else 2170 fdctrl->dor |= FD_DOR_DMAEN; 2171 /* No result back */ 2172 fdctrl_to_command_phase(fdctrl); 2173 } 2174 2175 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) 2176 { 2177 FDrive *cur_drv; 2178 2179 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2180 cur_drv = get_cur_drv(fdctrl); 2181 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 2182 /* 1 Byte status back */ 2183 fdctrl->fifo[0] = (cur_drv->ro << 6) | 2184 (cur_drv->track == 0 ? 0x10 : 0x00) | 2185 (cur_drv->head << 2) | 2186 GET_CUR_DRV(fdctrl) | 2187 0x28; 2188 fdctrl_to_result_phase(fdctrl, 1); 2189 } 2190 2191 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) 2192 { 2193 FDrive *cur_drv; 2194 2195 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2196 cur_drv = get_cur_drv(fdctrl); 2197 fd_recalibrate(cur_drv); 2198 fdctrl_to_command_phase(fdctrl); 2199 /* Raise Interrupt */ 2200 fdctrl->status0 |= FD_SR0_SEEK; 2201 fdctrl_raise_irq(fdctrl); 2202 } 2203 2204 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) 2205 { 2206 FDrive *cur_drv = get_cur_drv(fdctrl); 2207 2208 if (fdctrl->reset_sensei > 0) { 2209 fdctrl->fifo[0] = 2210 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; 2211 fdctrl->reset_sensei--; 2212 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) { 2213 fdctrl->fifo[0] = FD_SR0_INVCMD; 2214 fdctrl_to_result_phase(fdctrl, 1); 2215 return; 2216 } else { 2217 fdctrl->fifo[0] = 2218 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0)) 2219 | GET_CUR_DRV(fdctrl); 2220 } 2221 2222 fdctrl->fifo[1] = cur_drv->track; 2223 fdctrl_to_result_phase(fdctrl, 2); 2224 fdctrl_reset_irq(fdctrl); 2225 fdctrl->status0 = FD_SR0_RDYCHG; 2226 } 2227 2228 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) 2229 { 2230 FDrive *cur_drv; 2231 2232 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2233 cur_drv = get_cur_drv(fdctrl); 2234 fdctrl_to_command_phase(fdctrl); 2235 /* The seek command just sends step pulses to the drive and doesn't care if 2236 * there is a medium inserted of if it's banging the head against the drive. 2237 */ 2238 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1); 2239 /* Raise Interrupt */ 2240 fdctrl->status0 |= FD_SR0_SEEK; 2241 fdctrl_raise_irq(fdctrl); 2242 } 2243 2244 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) 2245 { 2246 FDrive *cur_drv = get_cur_drv(fdctrl); 2247 2248 if (fdctrl->fifo[1] & 0x80) 2249 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; 2250 /* No result back */ 2251 fdctrl_to_command_phase(fdctrl); 2252 } 2253 2254 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) 2255 { 2256 fdctrl->config = fdctrl->fifo[2]; 2257 fdctrl->precomp_trk = fdctrl->fifo[3]; 2258 /* No result back */ 2259 fdctrl_to_command_phase(fdctrl); 2260 } 2261 2262 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) 2263 { 2264 fdctrl->pwrd = fdctrl->fifo[1]; 2265 fdctrl->fifo[0] = fdctrl->fifo[1]; 2266 fdctrl_to_result_phase(fdctrl, 1); 2267 } 2268 2269 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) 2270 { 2271 /* No result back */ 2272 fdctrl_to_command_phase(fdctrl); 2273 } 2274 2275 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) 2276 { 2277 FDrive *cur_drv = get_cur_drv(fdctrl); 2278 uint32_t pos; 2279 2280 pos = fdctrl->data_pos - 1; 2281 pos %= FD_SECTOR_LEN; 2282 if (fdctrl->fifo[pos] & 0x80) { 2283 /* Command parameters done */ 2284 if (fdctrl->fifo[pos] & 0x40) { 2285 fdctrl->fifo[0] = fdctrl->fifo[1]; 2286 fdctrl->fifo[2] = 0; 2287 fdctrl->fifo[3] = 0; 2288 fdctrl_to_result_phase(fdctrl, 4); 2289 } else { 2290 fdctrl_to_command_phase(fdctrl); 2291 } 2292 } else if (fdctrl->data_len > 7) { 2293 /* ERROR */ 2294 fdctrl->fifo[0] = 0x80 | 2295 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); 2296 fdctrl_to_result_phase(fdctrl, 1); 2297 } 2298 } 2299 2300 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) 2301 { 2302 FDrive *cur_drv; 2303 2304 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2305 cur_drv = get_cur_drv(fdctrl); 2306 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { 2307 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1, 2308 cur_drv->sect, 1); 2309 } else { 2310 fd_seek(cur_drv, cur_drv->head, 2311 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1); 2312 } 2313 fdctrl_to_command_phase(fdctrl); 2314 /* Raise Interrupt */ 2315 fdctrl->status0 |= FD_SR0_SEEK; 2316 fdctrl_raise_irq(fdctrl); 2317 } 2318 2319 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) 2320 { 2321 FDrive *cur_drv; 2322 2323 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2324 cur_drv = get_cur_drv(fdctrl); 2325 if (fdctrl->fifo[2] > cur_drv->track) { 2326 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1); 2327 } else { 2328 fd_seek(cur_drv, cur_drv->head, 2329 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1); 2330 } 2331 fdctrl_to_command_phase(fdctrl); 2332 /* Raise Interrupt */ 2333 fdctrl->status0 |= FD_SR0_SEEK; 2334 fdctrl_raise_irq(fdctrl); 2335 } 2336 2337 /* 2338 * Handlers for the execution phase of each command 2339 */ 2340 typedef struct FDCtrlCommand { 2341 uint8_t value; 2342 uint8_t mask; 2343 const char* name; 2344 int parameters; 2345 void (*handler)(FDCtrl *fdctrl, int direction); 2346 int direction; 2347 } FDCtrlCommand; 2348 2349 static const FDCtrlCommand handlers[] = { 2350 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, 2351 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, 2352 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, 2353 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, 2354 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, 2355 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, 2356 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, 2357 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ 2358 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ 2359 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, 2360 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, 2361 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY }, 2362 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, 2363 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, 2364 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, 2365 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, 2366 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, 2367 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, 2368 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, 2369 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, 2370 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, 2371 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, 2372 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, 2373 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, 2374 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, 2375 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, 2376 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, 2377 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, 2378 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, 2379 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, 2380 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ 2381 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ 2382 }; 2383 /* Associate command to an index in the 'handlers' array */ 2384 static uint8_t command_to_handler[256]; 2385 2386 static const FDCtrlCommand *get_command(uint8_t cmd) 2387 { 2388 int idx; 2389 2390 idx = command_to_handler[cmd]; 2391 FLOPPY_DPRINTF("%s command\n", handlers[idx].name); 2392 return &handlers[idx]; 2393 } 2394 2395 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) 2396 { 2397 FDrive *cur_drv; 2398 const FDCtrlCommand *cmd; 2399 uint32_t pos; 2400 2401 /* Reset mode */ 2402 if (!(fdctrl->dor & FD_DOR_nRESET)) { 2403 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 2404 return; 2405 } 2406 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { 2407 FLOPPY_DPRINTF("error: controller not ready for writing\n"); 2408 return; 2409 } 2410 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 2411 2412 FLOPPY_DPRINTF("%s: %02x\n", __func__, value); 2413 2414 /* If data_len spans multiple sectors, the current position in the FIFO 2415 * wraps around while fdctrl->data_pos is the real position in the whole 2416 * request. */ 2417 pos = fdctrl->data_pos++; 2418 pos %= FD_SECTOR_LEN; 2419 fdctrl->fifo[pos] = value; 2420 2421 if (fdctrl->data_pos == fdctrl->data_len) { 2422 fdctrl->msr &= ~FD_MSR_RQM; 2423 } 2424 2425 switch (fdctrl->phase) { 2426 case FD_PHASE_EXECUTION: 2427 /* For DMA requests, RQM should be cleared during execution phase, so 2428 * we would have errored out above. */ 2429 assert(fdctrl->msr & FD_MSR_NONDMA); 2430 2431 /* FIFO data write */ 2432 if (pos == FD_SECTOR_LEN - 1 || 2433 fdctrl->data_pos == fdctrl->data_len) { 2434 cur_drv = get_cur_drv(fdctrl); 2435 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo, 2436 BDRV_SECTOR_SIZE, 0) < 0) { 2437 FLOPPY_DPRINTF("error writing sector %d\n", 2438 fd_sector(cur_drv)); 2439 break; 2440 } 2441 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 2442 FLOPPY_DPRINTF("error seeking to next sector %d\n", 2443 fd_sector(cur_drv)); 2444 break; 2445 } 2446 } 2447 2448 /* Switch to result phase when done with the transfer */ 2449 if (fdctrl->data_pos == fdctrl->data_len) { 2450 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2451 } 2452 break; 2453 2454 case FD_PHASE_COMMAND: 2455 assert(!(fdctrl->msr & FD_MSR_NONDMA)); 2456 assert(fdctrl->data_pos < FD_SECTOR_LEN); 2457 2458 if (pos == 0) { 2459 /* The first byte specifies the command. Now we start reading 2460 * as many parameters as this command requires. */ 2461 cmd = get_command(value); 2462 fdctrl->data_len = cmd->parameters + 1; 2463 if (cmd->parameters) { 2464 fdctrl->msr |= FD_MSR_RQM; 2465 } 2466 fdctrl->msr |= FD_MSR_CMDBUSY; 2467 } 2468 2469 if (fdctrl->data_pos == fdctrl->data_len) { 2470 /* We have all parameters now, execute the command */ 2471 fdctrl->phase = FD_PHASE_EXECUTION; 2472 2473 if (fdctrl->data_state & FD_STATE_FORMAT) { 2474 fdctrl_format_sector(fdctrl); 2475 break; 2476 } 2477 2478 cmd = get_command(fdctrl->fifo[0]); 2479 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name); 2480 cmd->handler(fdctrl, cmd->direction); 2481 } 2482 break; 2483 2484 case FD_PHASE_RESULT: 2485 default: 2486 abort(); 2487 } 2488 } 2489 2490 static void fdctrl_result_timer(void *opaque) 2491 { 2492 FDCtrl *fdctrl = opaque; 2493 FDrive *cur_drv = get_cur_drv(fdctrl); 2494 2495 /* Pretend we are spinning. 2496 * This is needed for Coherent, which uses READ ID to check for 2497 * sector interleaving. 2498 */ 2499 if (cur_drv->last_sect != 0) { 2500 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; 2501 } 2502 /* READ_ID can't automatically succeed! */ 2503 if (fdctrl->check_media_rate && 2504 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 2505 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n", 2506 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 2507 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 2508 } else { 2509 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2510 } 2511 } 2512 2513 /* Init functions */ 2514 static void fdctrl_connect_drives(FDCtrl *fdctrl, DeviceState *fdc_dev, 2515 Error **errp) 2516 { 2517 unsigned int i; 2518 FDrive *drive; 2519 DeviceState *dev; 2520 BlockBackend *blk; 2521 Error *local_err = NULL; 2522 2523 for (i = 0; i < MAX_FD; i++) { 2524 drive = &fdctrl->drives[i]; 2525 drive->fdctrl = fdctrl; 2526 2527 /* If the drive is not present, we skip creating the qdev device, but 2528 * still have to initialise the controller. */ 2529 blk = fdctrl->qdev_for_drives[i].blk; 2530 if (!blk) { 2531 fd_init(drive); 2532 fd_revalidate(drive); 2533 continue; 2534 } 2535 2536 dev = qdev_create(&fdctrl->bus.bus, "floppy"); 2537 qdev_prop_set_uint32(dev, "unit", i); 2538 qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type); 2539 2540 blk_ref(blk); 2541 blk_detach_dev(blk, fdc_dev); 2542 fdctrl->qdev_for_drives[i].blk = NULL; 2543 qdev_prop_set_drive(dev, "drive", blk, &local_err); 2544 blk_unref(blk); 2545 2546 if (local_err) { 2547 error_propagate(errp, local_err); 2548 return; 2549 } 2550 2551 object_property_set_bool(OBJECT(dev), true, "realized", &local_err); 2552 if (local_err) { 2553 error_propagate(errp, local_err); 2554 return; 2555 } 2556 } 2557 } 2558 2559 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds) 2560 { 2561 DeviceState *dev; 2562 ISADevice *isadev; 2563 2564 isadev = isa_try_create(bus, TYPE_ISA_FDC); 2565 if (!isadev) { 2566 return NULL; 2567 } 2568 dev = DEVICE(isadev); 2569 2570 if (fds[0]) { 2571 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), 2572 &error_fatal); 2573 } 2574 if (fds[1]) { 2575 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), 2576 &error_fatal); 2577 } 2578 qdev_init_nofail(dev); 2579 2580 return isadev; 2581 } 2582 2583 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, 2584 hwaddr mmio_base, DriveInfo **fds) 2585 { 2586 FDCtrl *fdctrl; 2587 DeviceState *dev; 2588 SysBusDevice *sbd; 2589 FDCtrlSysBus *sys; 2590 2591 dev = qdev_create(NULL, "sysbus-fdc"); 2592 sys = SYSBUS_FDC(dev); 2593 fdctrl = &sys->state; 2594 fdctrl->dma_chann = dma_chann; /* FIXME */ 2595 if (fds[0]) { 2596 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), 2597 &error_fatal); 2598 } 2599 if (fds[1]) { 2600 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), 2601 &error_fatal); 2602 } 2603 qdev_init_nofail(dev); 2604 sbd = SYS_BUS_DEVICE(dev); 2605 sysbus_connect_irq(sbd, 0, irq); 2606 sysbus_mmio_map(sbd, 0, mmio_base); 2607 } 2608 2609 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, 2610 DriveInfo **fds, qemu_irq *fdc_tc) 2611 { 2612 DeviceState *dev; 2613 FDCtrlSysBus *sys; 2614 2615 dev = qdev_create(NULL, "SUNW,fdtwo"); 2616 if (fds[0]) { 2617 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]), 2618 &error_fatal); 2619 } 2620 qdev_init_nofail(dev); 2621 sys = SYSBUS_FDC(dev); 2622 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); 2623 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base); 2624 *fdc_tc = qdev_get_gpio_in(dev, 0); 2625 } 2626 2627 static void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl, 2628 Error **errp) 2629 { 2630 int i, j; 2631 static int command_tables_inited = 0; 2632 2633 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) { 2634 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'"); 2635 } 2636 2637 /* Fill 'command_to_handler' lookup table */ 2638 if (!command_tables_inited) { 2639 command_tables_inited = 1; 2640 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { 2641 for (j = 0; j < sizeof(command_to_handler); j++) { 2642 if ((j & handlers[i].mask) == handlers[i].value) { 2643 command_to_handler[j] = i; 2644 } 2645 } 2646 } 2647 } 2648 2649 FLOPPY_DPRINTF("init controller\n"); 2650 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); 2651 fdctrl->fifo_size = 512; 2652 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2653 fdctrl_result_timer, fdctrl); 2654 2655 fdctrl->version = 0x90; /* Intel 82078 controller */ 2656 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ 2657 fdctrl->num_floppies = MAX_FD; 2658 2659 if (fdctrl->dma_chann != -1) { 2660 IsaDmaClass *k; 2661 assert(fdctrl->dma); 2662 k = ISADMA_GET_CLASS(fdctrl->dma); 2663 k->register_channel(fdctrl->dma, fdctrl->dma_chann, 2664 &fdctrl_transfer_handler, fdctrl); 2665 } 2666 2667 floppy_bus_create(fdctrl, &fdctrl->bus, dev); 2668 fdctrl_connect_drives(fdctrl, dev, errp); 2669 } 2670 2671 static const MemoryRegionPortio fdc_portio_list[] = { 2672 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, 2673 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, 2674 PORTIO_END_OF_LIST(), 2675 }; 2676 2677 static void isabus_fdc_realize(DeviceState *dev, Error **errp) 2678 { 2679 ISADevice *isadev = ISA_DEVICE(dev); 2680 FDCtrlISABus *isa = ISA_FDC(dev); 2681 FDCtrl *fdctrl = &isa->state; 2682 Error *err = NULL; 2683 2684 isa_register_portio_list(isadev, &fdctrl->portio_list, 2685 isa->iobase, fdc_portio_list, fdctrl, 2686 "fdc"); 2687 2688 isa_init_irq(isadev, &fdctrl->irq, isa->irq); 2689 fdctrl->dma_chann = isa->dma; 2690 if (fdctrl->dma_chann != -1) { 2691 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma); 2692 if (!fdctrl->dma) { 2693 error_setg(errp, "ISA controller does not support DMA"); 2694 return; 2695 } 2696 } 2697 2698 qdev_set_legacy_instance_id(dev, isa->iobase, 2); 2699 fdctrl_realize_common(dev, fdctrl, &err); 2700 if (err != NULL) { 2701 error_propagate(errp, err); 2702 return; 2703 } 2704 } 2705 2706 static void sysbus_fdc_initfn(Object *obj) 2707 { 2708 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2709 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2710 FDCtrl *fdctrl = &sys->state; 2711 2712 fdctrl->dma_chann = -1; 2713 2714 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl, 2715 "fdc", 0x08); 2716 sysbus_init_mmio(sbd, &fdctrl->iomem); 2717 } 2718 2719 static void sun4m_fdc_initfn(Object *obj) 2720 { 2721 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2722 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2723 FDCtrl *fdctrl = &sys->state; 2724 2725 fdctrl->dma_chann = -1; 2726 2727 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops, 2728 fdctrl, "fdctrl", 0x08); 2729 sysbus_init_mmio(sbd, &fdctrl->iomem); 2730 } 2731 2732 static void sysbus_fdc_common_initfn(Object *obj) 2733 { 2734 DeviceState *dev = DEVICE(obj); 2735 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 2736 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2737 FDCtrl *fdctrl = &sys->state; 2738 2739 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */ 2740 2741 sysbus_init_irq(sbd, &fdctrl->irq); 2742 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1); 2743 } 2744 2745 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp) 2746 { 2747 FDCtrlSysBus *sys = SYSBUS_FDC(dev); 2748 FDCtrl *fdctrl = &sys->state; 2749 2750 fdctrl_realize_common(dev, fdctrl, errp); 2751 } 2752 2753 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i) 2754 { 2755 FDCtrlISABus *isa = ISA_FDC(fdc); 2756 2757 return isa->state.drives[i].drive; 2758 } 2759 2760 void isa_fdc_get_drive_max_chs(FloppyDriveType type, 2761 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs) 2762 { 2763 const FDFormat *fdf; 2764 2765 *maxc = *maxh = *maxs = 0; 2766 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) { 2767 if (fdf->drive != type) { 2768 continue; 2769 } 2770 if (*maxc < fdf->max_track) { 2771 *maxc = fdf->max_track; 2772 } 2773 if (*maxh < fdf->max_head) { 2774 *maxh = fdf->max_head; 2775 } 2776 if (*maxs < fdf->last_sect) { 2777 *maxs = fdf->last_sect; 2778 } 2779 } 2780 (*maxc)--; 2781 } 2782 2783 static const VMStateDescription vmstate_isa_fdc ={ 2784 .name = "fdc", 2785 .version_id = 2, 2786 .minimum_version_id = 2, 2787 .fields = (VMStateField[]) { 2788 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl), 2789 VMSTATE_END_OF_LIST() 2790 } 2791 }; 2792 2793 static Property isa_fdc_properties[] = { 2794 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0), 2795 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6), 2796 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2), 2797 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.qdev_for_drives[0].blk), 2798 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.qdev_for_drives[1].blk), 2799 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate, 2800 0, true), 2801 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlISABus, state.qdev_for_drives[0].type, 2802 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2803 FloppyDriveType), 2804 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlISABus, state.qdev_for_drives[1].type, 2805 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2806 FloppyDriveType), 2807 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback, 2808 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type, 2809 FloppyDriveType), 2810 DEFINE_PROP_END_OF_LIST(), 2811 }; 2812 2813 static void isabus_fdc_class_init(ObjectClass *klass, void *data) 2814 { 2815 DeviceClass *dc = DEVICE_CLASS(klass); 2816 2817 dc->realize = isabus_fdc_realize; 2818 dc->fw_name = "fdc"; 2819 dc->reset = fdctrl_external_reset_isa; 2820 dc->vmsd = &vmstate_isa_fdc; 2821 dc->props = isa_fdc_properties; 2822 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2823 } 2824 2825 static void isabus_fdc_instance_init(Object *obj) 2826 { 2827 FDCtrlISABus *isa = ISA_FDC(obj); 2828 2829 device_add_bootindex_property(obj, &isa->bootindexA, 2830 "bootindexA", "/floppy@0", 2831 DEVICE(obj), NULL); 2832 device_add_bootindex_property(obj, &isa->bootindexB, 2833 "bootindexB", "/floppy@1", 2834 DEVICE(obj), NULL); 2835 } 2836 2837 static const TypeInfo isa_fdc_info = { 2838 .name = TYPE_ISA_FDC, 2839 .parent = TYPE_ISA_DEVICE, 2840 .instance_size = sizeof(FDCtrlISABus), 2841 .class_init = isabus_fdc_class_init, 2842 .instance_init = isabus_fdc_instance_init, 2843 }; 2844 2845 static const VMStateDescription vmstate_sysbus_fdc ={ 2846 .name = "fdc", 2847 .version_id = 2, 2848 .minimum_version_id = 2, 2849 .fields = (VMStateField[]) { 2850 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl), 2851 VMSTATE_END_OF_LIST() 2852 } 2853 }; 2854 2855 static Property sysbus_fdc_properties[] = { 2856 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.qdev_for_drives[0].blk), 2857 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.qdev_for_drives[1].blk), 2858 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlSysBus, state.qdev_for_drives[0].type, 2859 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2860 FloppyDriveType), 2861 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlSysBus, state.qdev_for_drives[1].type, 2862 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2863 FloppyDriveType), 2864 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback, 2865 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type, 2866 FloppyDriveType), 2867 DEFINE_PROP_END_OF_LIST(), 2868 }; 2869 2870 static void sysbus_fdc_class_init(ObjectClass *klass, void *data) 2871 { 2872 DeviceClass *dc = DEVICE_CLASS(klass); 2873 2874 dc->props = sysbus_fdc_properties; 2875 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2876 } 2877 2878 static const TypeInfo sysbus_fdc_info = { 2879 .name = "sysbus-fdc", 2880 .parent = TYPE_SYSBUS_FDC, 2881 .instance_init = sysbus_fdc_initfn, 2882 .class_init = sysbus_fdc_class_init, 2883 }; 2884 2885 static Property sun4m_fdc_properties[] = { 2886 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.qdev_for_drives[0].blk), 2887 DEFINE_PROP_SIGNED("fdtype", FDCtrlSysBus, state.qdev_for_drives[0].type, 2888 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2889 FloppyDriveType), 2890 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback, 2891 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type, 2892 FloppyDriveType), 2893 DEFINE_PROP_END_OF_LIST(), 2894 }; 2895 2896 static void sun4m_fdc_class_init(ObjectClass *klass, void *data) 2897 { 2898 DeviceClass *dc = DEVICE_CLASS(klass); 2899 2900 dc->props = sun4m_fdc_properties; 2901 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2902 } 2903 2904 static const TypeInfo sun4m_fdc_info = { 2905 .name = "SUNW,fdtwo", 2906 .parent = TYPE_SYSBUS_FDC, 2907 .instance_init = sun4m_fdc_initfn, 2908 .class_init = sun4m_fdc_class_init, 2909 }; 2910 2911 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data) 2912 { 2913 DeviceClass *dc = DEVICE_CLASS(klass); 2914 2915 dc->realize = sysbus_fdc_common_realize; 2916 dc->reset = fdctrl_external_reset_sysbus; 2917 dc->vmsd = &vmstate_sysbus_fdc; 2918 } 2919 2920 static const TypeInfo sysbus_fdc_type_info = { 2921 .name = TYPE_SYSBUS_FDC, 2922 .parent = TYPE_SYS_BUS_DEVICE, 2923 .instance_size = sizeof(FDCtrlSysBus), 2924 .instance_init = sysbus_fdc_common_initfn, 2925 .abstract = true, 2926 .class_init = sysbus_fdc_common_class_init, 2927 }; 2928 2929 static void fdc_register_types(void) 2930 { 2931 type_register_static(&isa_fdc_info); 2932 type_register_static(&sysbus_fdc_type_info); 2933 type_register_static(&sysbus_fdc_info); 2934 type_register_static(&sun4m_fdc_info); 2935 type_register_static(&floppy_bus_info); 2936 type_register_static(&floppy_drive_info); 2937 } 2938 2939 type_init(fdc_register_types) 2940