1 /* 2 * QEMU Floppy disk emulator (Intel 82078) 3 * 4 * Copyright (c) 2003, 2007 Jocelyn Mayer 5 * Copyright (c) 2008 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * The controller is used in Sun4m systems in a slightly different 27 * way. There are changes in DOR register and DMA is not available. 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/block/fdc.h" 33 #include "qapi/error.h" 34 #include "qemu/error-report.h" 35 #include "qemu/timer.h" 36 #include "hw/isa/isa.h" 37 #include "hw/sysbus.h" 38 #include "hw/block/block.h" 39 #include "sysemu/block-backend.h" 40 #include "sysemu/blockdev.h" 41 #include "sysemu/sysemu.h" 42 #include "qemu/log.h" 43 44 /********************************************************/ 45 /* debug Floppy devices */ 46 47 #define DEBUG_FLOPPY 0 48 49 #define FLOPPY_DPRINTF(fmt, ...) \ 50 do { \ 51 if (DEBUG_FLOPPY) { \ 52 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \ 53 } \ 54 } while (0) 55 56 57 /********************************************************/ 58 /* qdev floppy bus */ 59 60 #define TYPE_FLOPPY_BUS "floppy-bus" 61 #define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS) 62 63 typedef struct FDCtrl FDCtrl; 64 typedef struct FDrive FDrive; 65 static FDrive *get_drv(FDCtrl *fdctrl, int unit); 66 67 typedef struct FloppyBus { 68 BusState bus; 69 FDCtrl *fdc; 70 } FloppyBus; 71 72 static const TypeInfo floppy_bus_info = { 73 .name = TYPE_FLOPPY_BUS, 74 .parent = TYPE_BUS, 75 .instance_size = sizeof(FloppyBus), 76 }; 77 78 static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev) 79 { 80 qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL); 81 bus->fdc = fdc; 82 } 83 84 85 /********************************************************/ 86 /* Floppy drive emulation */ 87 88 typedef enum FDriveRate { 89 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */ 90 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */ 91 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */ 92 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */ 93 } FDriveRate; 94 95 typedef enum FDriveSize { 96 FDRIVE_SIZE_UNKNOWN, 97 FDRIVE_SIZE_350, 98 FDRIVE_SIZE_525, 99 } FDriveSize; 100 101 typedef struct FDFormat { 102 FloppyDriveType drive; 103 uint8_t last_sect; 104 uint8_t max_track; 105 uint8_t max_head; 106 FDriveRate rate; 107 } FDFormat; 108 109 /* In many cases, the total sector size of a format is enough to uniquely 110 * identify it. However, there are some total sector collisions between 111 * formats of different physical size, and these are noted below by 112 * highlighting the total sector size for entries with collisions. */ 113 static const FDFormat fd_formats[] = { 114 /* First entry is default format */ 115 /* 1.44 MB 3"1/2 floppy disks */ 116 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */ 117 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */ 118 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, }, 119 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, }, 120 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, }, 121 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, }, 122 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, }, 123 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, }, 124 /* 2.88 MB 3"1/2 floppy disks */ 125 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, }, 126 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, }, 127 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, }, 128 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, }, 129 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, }, 130 /* 720 kB 3"1/2 floppy disks */ 131 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */ 132 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, }, 133 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, }, 134 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, }, 135 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, }, 136 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, }, 137 /* 1.2 MB 5"1/4 floppy disks */ 138 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, }, 139 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */ 140 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, }, 141 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, }, 142 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */ 143 /* 720 kB 5"1/4 floppy disks */ 144 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */ 145 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, }, 146 /* 360 kB 5"1/4 floppy disks */ 147 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */ 148 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, }, 149 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, }, 150 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, }, 151 /* 320 kB 5"1/4 floppy disks */ 152 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, }, 153 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, }, 154 /* 360 kB must match 5"1/4 better than 3"1/2... */ 155 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */ 156 /* end */ 157 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, }, 158 }; 159 160 static FDriveSize drive_size(FloppyDriveType drive) 161 { 162 switch (drive) { 163 case FLOPPY_DRIVE_TYPE_120: 164 return FDRIVE_SIZE_525; 165 case FLOPPY_DRIVE_TYPE_144: 166 case FLOPPY_DRIVE_TYPE_288: 167 return FDRIVE_SIZE_350; 168 default: 169 return FDRIVE_SIZE_UNKNOWN; 170 } 171 } 172 173 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) 174 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) 175 176 /* Will always be a fixed parameter for us */ 177 #define FD_SECTOR_LEN 512 178 #define FD_SECTOR_SC 2 /* Sector size code */ 179 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ 180 181 /* Floppy disk drive emulation */ 182 typedef enum FDiskFlags { 183 FDISK_DBL_SIDES = 0x01, 184 } FDiskFlags; 185 186 struct FDrive { 187 FDCtrl *fdctrl; 188 BlockBackend *blk; 189 BlockConf *conf; 190 /* Drive status */ 191 FloppyDriveType drive; /* CMOS drive type */ 192 uint8_t perpendicular; /* 2.88 MB access mode */ 193 /* Position */ 194 uint8_t head; 195 uint8_t track; 196 uint8_t sect; 197 /* Media */ 198 FloppyDriveType disk; /* Current disk type */ 199 FDiskFlags flags; 200 uint8_t last_sect; /* Nb sector per track */ 201 uint8_t max_track; /* Nb of tracks */ 202 uint16_t bps; /* Bytes per sector */ 203 uint8_t ro; /* Is read-only */ 204 uint8_t media_changed; /* Is media changed */ 205 uint8_t media_rate; /* Data rate of medium */ 206 207 bool media_validated; /* Have we validated the media? */ 208 }; 209 210 211 static FloppyDriveType get_fallback_drive_type(FDrive *drv); 212 213 /* Hack: FD_SEEK is expected to work on empty drives. However, QEMU 214 * currently goes through some pains to keep seeks within the bounds 215 * established by last_sect and max_track. Correcting this is difficult, 216 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel. 217 * 218 * For now: allow empty drives to have large bounds so we can seek around, 219 * with the understanding that when a diskette is inserted, the bounds will 220 * properly tighten to match the geometry of that inserted medium. 221 */ 222 static void fd_empty_seek_hack(FDrive *drv) 223 { 224 drv->last_sect = 0xFF; 225 drv->max_track = 0xFF; 226 } 227 228 static void fd_init(FDrive *drv) 229 { 230 /* Drive */ 231 drv->perpendicular = 0; 232 /* Disk */ 233 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 234 drv->last_sect = 0; 235 drv->max_track = 0; 236 drv->ro = true; 237 drv->media_changed = 1; 238 } 239 240 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) 241 242 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, 243 uint8_t last_sect, uint8_t num_sides) 244 { 245 return (((track * num_sides) + head) * last_sect) + sect - 1; 246 } 247 248 /* Returns current position, in sectors, for given drive */ 249 static int fd_sector(FDrive *drv) 250 { 251 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, 252 NUM_SIDES(drv)); 253 } 254 255 /* Returns current position, in bytes, for given drive */ 256 static int fd_offset(FDrive *drv) 257 { 258 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS); 259 return fd_sector(drv) << BDRV_SECTOR_BITS; 260 } 261 262 /* Seek to a new position: 263 * returns 0 if already on right track 264 * returns 1 if track changed 265 * returns 2 if track is invalid 266 * returns 3 if sector is invalid 267 * returns 4 if seek is disabled 268 */ 269 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, 270 int enable_seek) 271 { 272 uint32_t sector; 273 int ret; 274 275 if (track > drv->max_track || 276 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { 277 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 278 head, track, sect, 1, 279 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 280 drv->max_track, drv->last_sect); 281 return 2; 282 } 283 if (sect > drv->last_sect) { 284 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 285 head, track, sect, 1, 286 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 287 drv->max_track, drv->last_sect); 288 return 3; 289 } 290 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); 291 ret = 0; 292 if (sector != fd_sector(drv)) { 293 #if 0 294 if (!enable_seek) { 295 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x" 296 " (max=%d %02x %02x)\n", 297 head, track, sect, 1, drv->max_track, 298 drv->last_sect); 299 return 4; 300 } 301 #endif 302 drv->head = head; 303 if (drv->track != track) { 304 if (drv->blk != NULL && blk_is_inserted(drv->blk)) { 305 drv->media_changed = 0; 306 } 307 ret = 1; 308 } 309 drv->track = track; 310 drv->sect = sect; 311 } 312 313 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) { 314 ret = 2; 315 } 316 317 return ret; 318 } 319 320 /* Set drive back to track 0 */ 321 static void fd_recalibrate(FDrive *drv) 322 { 323 FLOPPY_DPRINTF("recalibrate\n"); 324 fd_seek(drv, 0, 0, 1, 1); 325 } 326 327 /** 328 * Determine geometry based on inserted diskette. 329 * Will not operate on an empty drive. 330 * 331 * @return: 0 on success, -1 if the drive is empty. 332 */ 333 static int pick_geometry(FDrive *drv) 334 { 335 BlockBackend *blk = drv->blk; 336 const FDFormat *parse; 337 uint64_t nb_sectors, size; 338 int i; 339 int match, size_match, type_match; 340 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO; 341 342 /* We can only pick a geometry if we have a diskette. */ 343 if (!drv->blk || !blk_is_inserted(drv->blk) || 344 drv->drive == FLOPPY_DRIVE_TYPE_NONE) 345 { 346 return -1; 347 } 348 349 /* We need to determine the likely geometry of the inserted medium. 350 * In order of preference, we look for: 351 * (1) The same drive type and number of sectors, 352 * (2) The same diskette size and number of sectors, 353 * (3) The same drive type. 354 * 355 * In all cases, matches that occur higher in the drive table will take 356 * precedence over matches that occur later in the table. 357 */ 358 blk_get_geometry(blk, &nb_sectors); 359 match = size_match = type_match = -1; 360 for (i = 0; ; i++) { 361 parse = &fd_formats[i]; 362 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) { 363 break; 364 } 365 size = (parse->max_head + 1) * parse->max_track * parse->last_sect; 366 if (nb_sectors == size) { 367 if (magic || parse->drive == drv->drive) { 368 /* (1) perfect match -- nb_sectors and drive type */ 369 goto out; 370 } else if (drive_size(parse->drive) == drive_size(drv->drive)) { 371 /* (2) size match -- nb_sectors and physical medium size */ 372 match = (match == -1) ? i : match; 373 } else { 374 /* This is suspicious -- Did the user misconfigure? */ 375 size_match = (size_match == -1) ? i : size_match; 376 } 377 } else if (type_match == -1) { 378 if ((parse->drive == drv->drive) || 379 (magic && (parse->drive == get_fallback_drive_type(drv)))) { 380 /* (3) type match -- nb_sectors mismatch, but matches the type 381 * specified explicitly by the user, or matches the fallback 382 * default type when using the drive autodetect mechanism */ 383 type_match = i; 384 } 385 } 386 } 387 388 /* No exact match found */ 389 if (match == -1) { 390 if (size_match != -1) { 391 parse = &fd_formats[size_match]; 392 FLOPPY_DPRINTF("User requested floppy drive type '%s', " 393 "but inserted medium appears to be a " 394 "%"PRId64" sector '%s' type\n", 395 FloppyDriveType_str(drv->drive), 396 nb_sectors, 397 FloppyDriveType_str(parse->drive)); 398 } 399 match = type_match; 400 } 401 402 /* No match of any kind found -- fd_format is misconfigured, abort. */ 403 if (match == -1) { 404 error_setg(&error_abort, "No candidate geometries present in table " 405 " for floppy drive type '%s'", 406 FloppyDriveType_str(drv->drive)); 407 } 408 409 parse = &(fd_formats[match]); 410 411 out: 412 if (parse->max_head == 0) { 413 drv->flags &= ~FDISK_DBL_SIDES; 414 } else { 415 drv->flags |= FDISK_DBL_SIDES; 416 } 417 drv->max_track = parse->max_track; 418 drv->last_sect = parse->last_sect; 419 drv->disk = parse->drive; 420 drv->media_rate = parse->rate; 421 return 0; 422 } 423 424 static void pick_drive_type(FDrive *drv) 425 { 426 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) { 427 return; 428 } 429 430 if (pick_geometry(drv) == 0) { 431 drv->drive = drv->disk; 432 } else { 433 drv->drive = get_fallback_drive_type(drv); 434 } 435 436 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO); 437 } 438 439 /* Revalidate a disk drive after a disk change */ 440 static void fd_revalidate(FDrive *drv) 441 { 442 int rc; 443 444 FLOPPY_DPRINTF("revalidate\n"); 445 if (drv->blk != NULL) { 446 drv->ro = blk_is_read_only(drv->blk); 447 if (!blk_is_inserted(drv->blk)) { 448 FLOPPY_DPRINTF("No disk in drive\n"); 449 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 450 fd_empty_seek_hack(drv); 451 } else if (!drv->media_validated) { 452 rc = pick_geometry(drv); 453 if (rc) { 454 FLOPPY_DPRINTF("Could not validate floppy drive media"); 455 } else { 456 drv->media_validated = true; 457 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", 458 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1, 459 drv->max_track, drv->last_sect, 460 drv->ro ? "ro" : "rw"); 461 } 462 } 463 } else { 464 FLOPPY_DPRINTF("No drive connected\n"); 465 drv->last_sect = 0; 466 drv->max_track = 0; 467 drv->flags &= ~FDISK_DBL_SIDES; 468 drv->drive = FLOPPY_DRIVE_TYPE_NONE; 469 drv->disk = FLOPPY_DRIVE_TYPE_NONE; 470 } 471 } 472 473 static void fd_change_cb(void *opaque, bool load, Error **errp) 474 { 475 FDrive *drive = opaque; 476 477 if (!load) { 478 blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort); 479 } else { 480 if (!blkconf_apply_backend_options(drive->conf, 481 blk_is_read_only(drive->blk), false, 482 errp)) { 483 return; 484 } 485 } 486 487 drive->media_changed = 1; 488 drive->media_validated = false; 489 fd_revalidate(drive); 490 } 491 492 static const BlockDevOps fd_block_ops = { 493 .change_media_cb = fd_change_cb, 494 }; 495 496 497 #define TYPE_FLOPPY_DRIVE "floppy" 498 #define FLOPPY_DRIVE(obj) \ 499 OBJECT_CHECK(FloppyDrive, (obj), TYPE_FLOPPY_DRIVE) 500 501 typedef struct FloppyDrive { 502 DeviceState qdev; 503 uint32_t unit; 504 BlockConf conf; 505 FloppyDriveType type; 506 } FloppyDrive; 507 508 static Property floppy_drive_properties[] = { 509 DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1), 510 DEFINE_BLOCK_PROPERTIES(FloppyDrive, conf), 511 DEFINE_PROP_SIGNED("drive-type", FloppyDrive, type, 512 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 513 FloppyDriveType), 514 DEFINE_PROP_END_OF_LIST(), 515 }; 516 517 static void floppy_drive_realize(DeviceState *qdev, Error **errp) 518 { 519 FloppyDrive *dev = FLOPPY_DRIVE(qdev); 520 FloppyBus *bus = FLOPPY_BUS(qdev->parent_bus); 521 FDrive *drive; 522 int ret; 523 524 if (dev->unit == -1) { 525 for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) { 526 drive = get_drv(bus->fdc, dev->unit); 527 if (!drive->blk) { 528 break; 529 } 530 } 531 } 532 533 if (dev->unit >= MAX_FD) { 534 error_setg(errp, "Can't create floppy unit %d, bus supports " 535 "only %d units", dev->unit, MAX_FD); 536 return; 537 } 538 539 drive = get_drv(bus->fdc, dev->unit); 540 if (drive->blk) { 541 error_setg(errp, "Floppy unit %d is in use", dev->unit); 542 return; 543 } 544 545 if (!dev->conf.blk) { 546 /* Anonymous BlockBackend for an empty drive */ 547 dev->conf.blk = blk_new(0, BLK_PERM_ALL); 548 ret = blk_attach_dev(dev->conf.blk, qdev); 549 assert(ret == 0); 550 } 551 552 blkconf_blocksizes(&dev->conf); 553 if (dev->conf.logical_block_size != 512 || 554 dev->conf.physical_block_size != 512) 555 { 556 error_setg(errp, "Physical and logical block size must " 557 "be 512 for floppy"); 558 return; 559 } 560 561 /* rerror/werror aren't supported by fdc and therefore not even registered 562 * with qdev. So set the defaults manually before they are used in 563 * blkconf_apply_backend_options(). */ 564 dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO; 565 dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO; 566 567 if (!blkconf_apply_backend_options(&dev->conf, 568 blk_is_read_only(dev->conf.blk), 569 false, errp)) { 570 return; 571 } 572 573 /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us 574 * for empty drives. */ 575 if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC && 576 blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) { 577 error_setg(errp, "fdc doesn't support drive option werror"); 578 return; 579 } 580 if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) { 581 error_setg(errp, "fdc doesn't support drive option rerror"); 582 return; 583 } 584 585 drive->conf = &dev->conf; 586 drive->blk = dev->conf.blk; 587 drive->fdctrl = bus->fdc; 588 589 fd_init(drive); 590 blk_set_dev_ops(drive->blk, &fd_block_ops, drive); 591 592 /* Keep 'type' qdev property and FDrive->drive in sync */ 593 drive->drive = dev->type; 594 pick_drive_type(drive); 595 dev->type = drive->drive; 596 597 fd_revalidate(drive); 598 } 599 600 static void floppy_drive_class_init(ObjectClass *klass, void *data) 601 { 602 DeviceClass *k = DEVICE_CLASS(klass); 603 k->realize = floppy_drive_realize; 604 set_bit(DEVICE_CATEGORY_STORAGE, k->categories); 605 k->bus_type = TYPE_FLOPPY_BUS; 606 k->props = floppy_drive_properties; 607 k->desc = "virtual floppy drive"; 608 } 609 610 static const TypeInfo floppy_drive_info = { 611 .name = TYPE_FLOPPY_DRIVE, 612 .parent = TYPE_DEVICE, 613 .instance_size = sizeof(FloppyDrive), 614 .class_init = floppy_drive_class_init, 615 }; 616 617 /********************************************************/ 618 /* Intel 82078 floppy disk controller emulation */ 619 620 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); 621 static void fdctrl_to_command_phase(FDCtrl *fdctrl); 622 static int fdctrl_transfer_handler (void *opaque, int nchan, 623 int dma_pos, int dma_len); 624 static void fdctrl_raise_irq(FDCtrl *fdctrl); 625 static FDrive *get_cur_drv(FDCtrl *fdctrl); 626 627 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); 628 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); 629 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); 630 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); 631 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); 632 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); 633 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); 634 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); 635 static uint32_t fdctrl_read_data(FDCtrl *fdctrl); 636 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); 637 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); 638 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); 639 640 enum { 641 FD_DIR_WRITE = 0, 642 FD_DIR_READ = 1, 643 FD_DIR_SCANE = 2, 644 FD_DIR_SCANL = 3, 645 FD_DIR_SCANH = 4, 646 FD_DIR_VERIFY = 5, 647 }; 648 649 enum { 650 FD_STATE_MULTI = 0x01, /* multi track flag */ 651 FD_STATE_FORMAT = 0x02, /* format flag */ 652 }; 653 654 enum { 655 FD_REG_SRA = 0x00, 656 FD_REG_SRB = 0x01, 657 FD_REG_DOR = 0x02, 658 FD_REG_TDR = 0x03, 659 FD_REG_MSR = 0x04, 660 FD_REG_DSR = 0x04, 661 FD_REG_FIFO = 0x05, 662 FD_REG_DIR = 0x07, 663 FD_REG_CCR = 0x07, 664 }; 665 666 enum { 667 FD_CMD_READ_TRACK = 0x02, 668 FD_CMD_SPECIFY = 0x03, 669 FD_CMD_SENSE_DRIVE_STATUS = 0x04, 670 FD_CMD_WRITE = 0x05, 671 FD_CMD_READ = 0x06, 672 FD_CMD_RECALIBRATE = 0x07, 673 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, 674 FD_CMD_WRITE_DELETED = 0x09, 675 FD_CMD_READ_ID = 0x0a, 676 FD_CMD_READ_DELETED = 0x0c, 677 FD_CMD_FORMAT_TRACK = 0x0d, 678 FD_CMD_DUMPREG = 0x0e, 679 FD_CMD_SEEK = 0x0f, 680 FD_CMD_VERSION = 0x10, 681 FD_CMD_SCAN_EQUAL = 0x11, 682 FD_CMD_PERPENDICULAR_MODE = 0x12, 683 FD_CMD_CONFIGURE = 0x13, 684 FD_CMD_LOCK = 0x14, 685 FD_CMD_VERIFY = 0x16, 686 FD_CMD_POWERDOWN_MODE = 0x17, 687 FD_CMD_PART_ID = 0x18, 688 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, 689 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, 690 FD_CMD_SAVE = 0x2e, 691 FD_CMD_OPTION = 0x33, 692 FD_CMD_RESTORE = 0x4e, 693 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, 694 FD_CMD_RELATIVE_SEEK_OUT = 0x8f, 695 FD_CMD_FORMAT_AND_WRITE = 0xcd, 696 FD_CMD_RELATIVE_SEEK_IN = 0xcf, 697 }; 698 699 enum { 700 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ 701 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ 702 FD_CONFIG_POLL = 0x10, /* Poll enabled */ 703 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ 704 FD_CONFIG_EIS = 0x40, /* No implied seeks */ 705 }; 706 707 enum { 708 FD_SR0_DS0 = 0x01, 709 FD_SR0_DS1 = 0x02, 710 FD_SR0_HEAD = 0x04, 711 FD_SR0_EQPMT = 0x10, 712 FD_SR0_SEEK = 0x20, 713 FD_SR0_ABNTERM = 0x40, 714 FD_SR0_INVCMD = 0x80, 715 FD_SR0_RDYCHG = 0xc0, 716 }; 717 718 enum { 719 FD_SR1_MA = 0x01, /* Missing address mark */ 720 FD_SR1_NW = 0x02, /* Not writable */ 721 FD_SR1_EC = 0x80, /* End of cylinder */ 722 }; 723 724 enum { 725 FD_SR2_SNS = 0x04, /* Scan not satisfied */ 726 FD_SR2_SEH = 0x08, /* Scan equal hit */ 727 }; 728 729 enum { 730 FD_SRA_DIR = 0x01, 731 FD_SRA_nWP = 0x02, 732 FD_SRA_nINDX = 0x04, 733 FD_SRA_HDSEL = 0x08, 734 FD_SRA_nTRK0 = 0x10, 735 FD_SRA_STEP = 0x20, 736 FD_SRA_nDRV2 = 0x40, 737 FD_SRA_INTPEND = 0x80, 738 }; 739 740 enum { 741 FD_SRB_MTR0 = 0x01, 742 FD_SRB_MTR1 = 0x02, 743 FD_SRB_WGATE = 0x04, 744 FD_SRB_RDATA = 0x08, 745 FD_SRB_WDATA = 0x10, 746 FD_SRB_DR0 = 0x20, 747 }; 748 749 enum { 750 #if MAX_FD == 4 751 FD_DOR_SELMASK = 0x03, 752 #else 753 FD_DOR_SELMASK = 0x01, 754 #endif 755 FD_DOR_nRESET = 0x04, 756 FD_DOR_DMAEN = 0x08, 757 FD_DOR_MOTEN0 = 0x10, 758 FD_DOR_MOTEN1 = 0x20, 759 FD_DOR_MOTEN2 = 0x40, 760 FD_DOR_MOTEN3 = 0x80, 761 }; 762 763 enum { 764 #if MAX_FD == 4 765 FD_TDR_BOOTSEL = 0x0c, 766 #else 767 FD_TDR_BOOTSEL = 0x04, 768 #endif 769 }; 770 771 enum { 772 FD_DSR_DRATEMASK= 0x03, 773 FD_DSR_PWRDOWN = 0x40, 774 FD_DSR_SWRESET = 0x80, 775 }; 776 777 enum { 778 FD_MSR_DRV0BUSY = 0x01, 779 FD_MSR_DRV1BUSY = 0x02, 780 FD_MSR_DRV2BUSY = 0x04, 781 FD_MSR_DRV3BUSY = 0x08, 782 FD_MSR_CMDBUSY = 0x10, 783 FD_MSR_NONDMA = 0x20, 784 FD_MSR_DIO = 0x40, 785 FD_MSR_RQM = 0x80, 786 }; 787 788 enum { 789 FD_DIR_DSKCHG = 0x80, 790 }; 791 792 /* 793 * See chapter 5.0 "Controller phases" of the spec: 794 * 795 * Command phase: 796 * The host writes a command and its parameters into the FIFO. The command 797 * phase is completed when all parameters for the command have been supplied, 798 * and execution phase is entered. 799 * 800 * Execution phase: 801 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO 802 * contains the payload now, otherwise it's unused. When all bytes of the 803 * required data have been transferred, the state is switched to either result 804 * phase (if the command produces status bytes) or directly back into the 805 * command phase for the next command. 806 * 807 * Result phase: 808 * The host reads out the FIFO, which contains one or more result bytes now. 809 */ 810 enum { 811 /* Only for migration: reconstruct phase from registers like qemu 2.3 */ 812 FD_PHASE_RECONSTRUCT = 0, 813 814 FD_PHASE_COMMAND = 1, 815 FD_PHASE_EXECUTION = 2, 816 FD_PHASE_RESULT = 3, 817 }; 818 819 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) 820 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) 821 822 struct FDCtrl { 823 MemoryRegion iomem; 824 qemu_irq irq; 825 /* Controller state */ 826 QEMUTimer *result_timer; 827 int dma_chann; 828 uint8_t phase; 829 IsaDma *dma; 830 /* Controller's identification */ 831 uint8_t version; 832 /* HW */ 833 uint8_t sra; 834 uint8_t srb; 835 uint8_t dor; 836 uint8_t dor_vmstate; /* only used as temp during vmstate */ 837 uint8_t tdr; 838 uint8_t dsr; 839 uint8_t msr; 840 uint8_t cur_drv; 841 uint8_t status0; 842 uint8_t status1; 843 uint8_t status2; 844 /* Command FIFO */ 845 uint8_t *fifo; 846 int32_t fifo_size; 847 uint32_t data_pos; 848 uint32_t data_len; 849 uint8_t data_state; 850 uint8_t data_dir; 851 uint8_t eot; /* last wanted sector */ 852 /* States kept only to be returned back */ 853 /* precompensation */ 854 uint8_t precomp_trk; 855 uint8_t config; 856 uint8_t lock; 857 /* Power down config (also with status regB access mode */ 858 uint8_t pwrd; 859 /* Floppy drives */ 860 FloppyBus bus; 861 uint8_t num_floppies; 862 FDrive drives[MAX_FD]; 863 struct { 864 BlockBackend *blk; 865 FloppyDriveType type; 866 } qdev_for_drives[MAX_FD]; 867 int reset_sensei; 868 uint32_t check_media_rate; 869 FloppyDriveType fallback; /* type=auto failure fallback */ 870 /* Timers state */ 871 uint8_t timer0; 872 uint8_t timer1; 873 PortioList portio_list; 874 }; 875 876 static FloppyDriveType get_fallback_drive_type(FDrive *drv) 877 { 878 return drv->fdctrl->fallback; 879 } 880 881 #define TYPE_SYSBUS_FDC "base-sysbus-fdc" 882 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC) 883 884 typedef struct FDCtrlSysBus { 885 /*< private >*/ 886 SysBusDevice parent_obj; 887 /*< public >*/ 888 889 struct FDCtrl state; 890 } FDCtrlSysBus; 891 892 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC) 893 894 typedef struct FDCtrlISABus { 895 ISADevice parent_obj; 896 897 uint32_t iobase; 898 uint32_t irq; 899 uint32_t dma; 900 struct FDCtrl state; 901 int32_t bootindexA; 902 int32_t bootindexB; 903 } FDCtrlISABus; 904 905 static uint32_t fdctrl_read (void *opaque, uint32_t reg) 906 { 907 FDCtrl *fdctrl = opaque; 908 uint32_t retval; 909 910 reg &= 7; 911 switch (reg) { 912 case FD_REG_SRA: 913 retval = fdctrl_read_statusA(fdctrl); 914 break; 915 case FD_REG_SRB: 916 retval = fdctrl_read_statusB(fdctrl); 917 break; 918 case FD_REG_DOR: 919 retval = fdctrl_read_dor(fdctrl); 920 break; 921 case FD_REG_TDR: 922 retval = fdctrl_read_tape(fdctrl); 923 break; 924 case FD_REG_MSR: 925 retval = fdctrl_read_main_status(fdctrl); 926 break; 927 case FD_REG_FIFO: 928 retval = fdctrl_read_data(fdctrl); 929 break; 930 case FD_REG_DIR: 931 retval = fdctrl_read_dir(fdctrl); 932 break; 933 default: 934 retval = (uint32_t)(-1); 935 break; 936 } 937 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); 938 939 return retval; 940 } 941 942 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) 943 { 944 FDCtrl *fdctrl = opaque; 945 946 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); 947 948 reg &= 7; 949 switch (reg) { 950 case FD_REG_DOR: 951 fdctrl_write_dor(fdctrl, value); 952 break; 953 case FD_REG_TDR: 954 fdctrl_write_tape(fdctrl, value); 955 break; 956 case FD_REG_DSR: 957 fdctrl_write_rate(fdctrl, value); 958 break; 959 case FD_REG_FIFO: 960 fdctrl_write_data(fdctrl, value); 961 break; 962 case FD_REG_CCR: 963 fdctrl_write_ccr(fdctrl, value); 964 break; 965 default: 966 break; 967 } 968 } 969 970 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg, 971 unsigned ize) 972 { 973 return fdctrl_read(opaque, (uint32_t)reg); 974 } 975 976 static void fdctrl_write_mem (void *opaque, hwaddr reg, 977 uint64_t value, unsigned size) 978 { 979 fdctrl_write(opaque, (uint32_t)reg, value); 980 } 981 982 static const MemoryRegionOps fdctrl_mem_ops = { 983 .read = fdctrl_read_mem, 984 .write = fdctrl_write_mem, 985 .endianness = DEVICE_NATIVE_ENDIAN, 986 }; 987 988 static const MemoryRegionOps fdctrl_mem_strict_ops = { 989 .read = fdctrl_read_mem, 990 .write = fdctrl_write_mem, 991 .endianness = DEVICE_NATIVE_ENDIAN, 992 .valid = { 993 .min_access_size = 1, 994 .max_access_size = 1, 995 }, 996 }; 997 998 static bool fdrive_media_changed_needed(void *opaque) 999 { 1000 FDrive *drive = opaque; 1001 1002 return (drive->blk != NULL && drive->media_changed != 1); 1003 } 1004 1005 static const VMStateDescription vmstate_fdrive_media_changed = { 1006 .name = "fdrive/media_changed", 1007 .version_id = 1, 1008 .minimum_version_id = 1, 1009 .needed = fdrive_media_changed_needed, 1010 .fields = (VMStateField[]) { 1011 VMSTATE_UINT8(media_changed, FDrive), 1012 VMSTATE_END_OF_LIST() 1013 } 1014 }; 1015 1016 static bool fdrive_media_rate_needed(void *opaque) 1017 { 1018 FDrive *drive = opaque; 1019 1020 return drive->fdctrl->check_media_rate; 1021 } 1022 1023 static const VMStateDescription vmstate_fdrive_media_rate = { 1024 .name = "fdrive/media_rate", 1025 .version_id = 1, 1026 .minimum_version_id = 1, 1027 .needed = fdrive_media_rate_needed, 1028 .fields = (VMStateField[]) { 1029 VMSTATE_UINT8(media_rate, FDrive), 1030 VMSTATE_END_OF_LIST() 1031 } 1032 }; 1033 1034 static bool fdrive_perpendicular_needed(void *opaque) 1035 { 1036 FDrive *drive = opaque; 1037 1038 return drive->perpendicular != 0; 1039 } 1040 1041 static const VMStateDescription vmstate_fdrive_perpendicular = { 1042 .name = "fdrive/perpendicular", 1043 .version_id = 1, 1044 .minimum_version_id = 1, 1045 .needed = fdrive_perpendicular_needed, 1046 .fields = (VMStateField[]) { 1047 VMSTATE_UINT8(perpendicular, FDrive), 1048 VMSTATE_END_OF_LIST() 1049 } 1050 }; 1051 1052 static int fdrive_post_load(void *opaque, int version_id) 1053 { 1054 fd_revalidate(opaque); 1055 return 0; 1056 } 1057 1058 static const VMStateDescription vmstate_fdrive = { 1059 .name = "fdrive", 1060 .version_id = 1, 1061 .minimum_version_id = 1, 1062 .post_load = fdrive_post_load, 1063 .fields = (VMStateField[]) { 1064 VMSTATE_UINT8(head, FDrive), 1065 VMSTATE_UINT8(track, FDrive), 1066 VMSTATE_UINT8(sect, FDrive), 1067 VMSTATE_END_OF_LIST() 1068 }, 1069 .subsections = (const VMStateDescription*[]) { 1070 &vmstate_fdrive_media_changed, 1071 &vmstate_fdrive_media_rate, 1072 &vmstate_fdrive_perpendicular, 1073 NULL 1074 } 1075 }; 1076 1077 /* 1078 * Reconstructs the phase from register values according to the logic that was 1079 * implemented in qemu 2.3. This is the default value that is used if the phase 1080 * subsection is not present on migration. 1081 * 1082 * Don't change this function to reflect newer qemu versions, it is part of 1083 * the migration ABI. 1084 */ 1085 static int reconstruct_phase(FDCtrl *fdctrl) 1086 { 1087 if (fdctrl->msr & FD_MSR_NONDMA) { 1088 return FD_PHASE_EXECUTION; 1089 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) { 1090 /* qemu 2.3 disabled RQM only during DMA transfers */ 1091 return FD_PHASE_EXECUTION; 1092 } else if (fdctrl->msr & FD_MSR_DIO) { 1093 return FD_PHASE_RESULT; 1094 } else { 1095 return FD_PHASE_COMMAND; 1096 } 1097 } 1098 1099 static int fdc_pre_save(void *opaque) 1100 { 1101 FDCtrl *s = opaque; 1102 1103 s->dor_vmstate = s->dor | GET_CUR_DRV(s); 1104 1105 return 0; 1106 } 1107 1108 static int fdc_pre_load(void *opaque) 1109 { 1110 FDCtrl *s = opaque; 1111 s->phase = FD_PHASE_RECONSTRUCT; 1112 return 0; 1113 } 1114 1115 static int fdc_post_load(void *opaque, int version_id) 1116 { 1117 FDCtrl *s = opaque; 1118 1119 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); 1120 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; 1121 1122 if (s->phase == FD_PHASE_RECONSTRUCT) { 1123 s->phase = reconstruct_phase(s); 1124 } 1125 1126 return 0; 1127 } 1128 1129 static bool fdc_reset_sensei_needed(void *opaque) 1130 { 1131 FDCtrl *s = opaque; 1132 1133 return s->reset_sensei != 0; 1134 } 1135 1136 static const VMStateDescription vmstate_fdc_reset_sensei = { 1137 .name = "fdc/reset_sensei", 1138 .version_id = 1, 1139 .minimum_version_id = 1, 1140 .needed = fdc_reset_sensei_needed, 1141 .fields = (VMStateField[]) { 1142 VMSTATE_INT32(reset_sensei, FDCtrl), 1143 VMSTATE_END_OF_LIST() 1144 } 1145 }; 1146 1147 static bool fdc_result_timer_needed(void *opaque) 1148 { 1149 FDCtrl *s = opaque; 1150 1151 return timer_pending(s->result_timer); 1152 } 1153 1154 static const VMStateDescription vmstate_fdc_result_timer = { 1155 .name = "fdc/result_timer", 1156 .version_id = 1, 1157 .minimum_version_id = 1, 1158 .needed = fdc_result_timer_needed, 1159 .fields = (VMStateField[]) { 1160 VMSTATE_TIMER_PTR(result_timer, FDCtrl), 1161 VMSTATE_END_OF_LIST() 1162 } 1163 }; 1164 1165 static bool fdc_phase_needed(void *opaque) 1166 { 1167 FDCtrl *fdctrl = opaque; 1168 1169 return reconstruct_phase(fdctrl) != fdctrl->phase; 1170 } 1171 1172 static const VMStateDescription vmstate_fdc_phase = { 1173 .name = "fdc/phase", 1174 .version_id = 1, 1175 .minimum_version_id = 1, 1176 .needed = fdc_phase_needed, 1177 .fields = (VMStateField[]) { 1178 VMSTATE_UINT8(phase, FDCtrl), 1179 VMSTATE_END_OF_LIST() 1180 } 1181 }; 1182 1183 static const VMStateDescription vmstate_fdc = { 1184 .name = "fdc", 1185 .version_id = 2, 1186 .minimum_version_id = 2, 1187 .pre_save = fdc_pre_save, 1188 .pre_load = fdc_pre_load, 1189 .post_load = fdc_post_load, 1190 .fields = (VMStateField[]) { 1191 /* Controller State */ 1192 VMSTATE_UINT8(sra, FDCtrl), 1193 VMSTATE_UINT8(srb, FDCtrl), 1194 VMSTATE_UINT8(dor_vmstate, FDCtrl), 1195 VMSTATE_UINT8(tdr, FDCtrl), 1196 VMSTATE_UINT8(dsr, FDCtrl), 1197 VMSTATE_UINT8(msr, FDCtrl), 1198 VMSTATE_UINT8(status0, FDCtrl), 1199 VMSTATE_UINT8(status1, FDCtrl), 1200 VMSTATE_UINT8(status2, FDCtrl), 1201 /* Command FIFO */ 1202 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, 1203 uint8_t), 1204 VMSTATE_UINT32(data_pos, FDCtrl), 1205 VMSTATE_UINT32(data_len, FDCtrl), 1206 VMSTATE_UINT8(data_state, FDCtrl), 1207 VMSTATE_UINT8(data_dir, FDCtrl), 1208 VMSTATE_UINT8(eot, FDCtrl), 1209 /* States kept only to be returned back */ 1210 VMSTATE_UINT8(timer0, FDCtrl), 1211 VMSTATE_UINT8(timer1, FDCtrl), 1212 VMSTATE_UINT8(precomp_trk, FDCtrl), 1213 VMSTATE_UINT8(config, FDCtrl), 1214 VMSTATE_UINT8(lock, FDCtrl), 1215 VMSTATE_UINT8(pwrd, FDCtrl), 1216 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl, NULL), 1217 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, 1218 vmstate_fdrive, FDrive), 1219 VMSTATE_END_OF_LIST() 1220 }, 1221 .subsections = (const VMStateDescription*[]) { 1222 &vmstate_fdc_reset_sensei, 1223 &vmstate_fdc_result_timer, 1224 &vmstate_fdc_phase, 1225 NULL 1226 } 1227 }; 1228 1229 static void fdctrl_external_reset_sysbus(DeviceState *d) 1230 { 1231 FDCtrlSysBus *sys = SYSBUS_FDC(d); 1232 FDCtrl *s = &sys->state; 1233 1234 fdctrl_reset(s, 0); 1235 } 1236 1237 static void fdctrl_external_reset_isa(DeviceState *d) 1238 { 1239 FDCtrlISABus *isa = ISA_FDC(d); 1240 FDCtrl *s = &isa->state; 1241 1242 fdctrl_reset(s, 0); 1243 } 1244 1245 static void fdctrl_handle_tc(void *opaque, int irq, int level) 1246 { 1247 //FDCtrl *s = opaque; 1248 1249 if (level) { 1250 // XXX 1251 FLOPPY_DPRINTF("TC pulsed\n"); 1252 } 1253 } 1254 1255 /* Change IRQ state */ 1256 static void fdctrl_reset_irq(FDCtrl *fdctrl) 1257 { 1258 fdctrl->status0 = 0; 1259 if (!(fdctrl->sra & FD_SRA_INTPEND)) 1260 return; 1261 FLOPPY_DPRINTF("Reset interrupt\n"); 1262 qemu_set_irq(fdctrl->irq, 0); 1263 fdctrl->sra &= ~FD_SRA_INTPEND; 1264 } 1265 1266 static void fdctrl_raise_irq(FDCtrl *fdctrl) 1267 { 1268 if (!(fdctrl->sra & FD_SRA_INTPEND)) { 1269 qemu_set_irq(fdctrl->irq, 1); 1270 fdctrl->sra |= FD_SRA_INTPEND; 1271 } 1272 1273 fdctrl->reset_sensei = 0; 1274 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); 1275 } 1276 1277 /* Reset controller */ 1278 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) 1279 { 1280 int i; 1281 1282 FLOPPY_DPRINTF("reset controller\n"); 1283 fdctrl_reset_irq(fdctrl); 1284 /* Initialise controller */ 1285 fdctrl->sra = 0; 1286 fdctrl->srb = 0xc0; 1287 if (!fdctrl->drives[1].blk) { 1288 fdctrl->sra |= FD_SRA_nDRV2; 1289 } 1290 fdctrl->cur_drv = 0; 1291 fdctrl->dor = FD_DOR_nRESET; 1292 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; 1293 fdctrl->msr = FD_MSR_RQM; 1294 fdctrl->reset_sensei = 0; 1295 timer_del(fdctrl->result_timer); 1296 /* FIFO state */ 1297 fdctrl->data_pos = 0; 1298 fdctrl->data_len = 0; 1299 fdctrl->data_state = 0; 1300 fdctrl->data_dir = FD_DIR_WRITE; 1301 for (i = 0; i < MAX_FD; i++) 1302 fd_recalibrate(&fdctrl->drives[i]); 1303 fdctrl_to_command_phase(fdctrl); 1304 if (do_irq) { 1305 fdctrl->status0 |= FD_SR0_RDYCHG; 1306 fdctrl_raise_irq(fdctrl); 1307 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; 1308 } 1309 } 1310 1311 static inline FDrive *drv0(FDCtrl *fdctrl) 1312 { 1313 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; 1314 } 1315 1316 static inline FDrive *drv1(FDCtrl *fdctrl) 1317 { 1318 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) 1319 return &fdctrl->drives[1]; 1320 else 1321 return &fdctrl->drives[0]; 1322 } 1323 1324 #if MAX_FD == 4 1325 static inline FDrive *drv2(FDCtrl *fdctrl) 1326 { 1327 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) 1328 return &fdctrl->drives[2]; 1329 else 1330 return &fdctrl->drives[1]; 1331 } 1332 1333 static inline FDrive *drv3(FDCtrl *fdctrl) 1334 { 1335 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) 1336 return &fdctrl->drives[3]; 1337 else 1338 return &fdctrl->drives[2]; 1339 } 1340 #endif 1341 1342 static FDrive *get_drv(FDCtrl *fdctrl, int unit) 1343 { 1344 switch (unit) { 1345 case 0: return drv0(fdctrl); 1346 case 1: return drv1(fdctrl); 1347 #if MAX_FD == 4 1348 case 2: return drv2(fdctrl); 1349 case 3: return drv3(fdctrl); 1350 #endif 1351 default: return NULL; 1352 } 1353 } 1354 1355 static FDrive *get_cur_drv(FDCtrl *fdctrl) 1356 { 1357 return get_drv(fdctrl, fdctrl->cur_drv); 1358 } 1359 1360 /* Status A register : 0x00 (read-only) */ 1361 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) 1362 { 1363 uint32_t retval = fdctrl->sra; 1364 1365 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); 1366 1367 return retval; 1368 } 1369 1370 /* Status B register : 0x01 (read-only) */ 1371 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) 1372 { 1373 uint32_t retval = fdctrl->srb; 1374 1375 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); 1376 1377 return retval; 1378 } 1379 1380 /* Digital output register : 0x02 */ 1381 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) 1382 { 1383 uint32_t retval = fdctrl->dor; 1384 1385 /* Selected drive */ 1386 retval |= fdctrl->cur_drv; 1387 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); 1388 1389 return retval; 1390 } 1391 1392 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) 1393 { 1394 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); 1395 1396 /* Motors */ 1397 if (value & FD_DOR_MOTEN0) 1398 fdctrl->srb |= FD_SRB_MTR0; 1399 else 1400 fdctrl->srb &= ~FD_SRB_MTR0; 1401 if (value & FD_DOR_MOTEN1) 1402 fdctrl->srb |= FD_SRB_MTR1; 1403 else 1404 fdctrl->srb &= ~FD_SRB_MTR1; 1405 1406 /* Drive */ 1407 if (value & 1) 1408 fdctrl->srb |= FD_SRB_DR0; 1409 else 1410 fdctrl->srb &= ~FD_SRB_DR0; 1411 1412 /* Reset */ 1413 if (!(value & FD_DOR_nRESET)) { 1414 if (fdctrl->dor & FD_DOR_nRESET) { 1415 FLOPPY_DPRINTF("controller enter RESET state\n"); 1416 } 1417 } else { 1418 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1419 FLOPPY_DPRINTF("controller out of RESET state\n"); 1420 fdctrl_reset(fdctrl, 1); 1421 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1422 } 1423 } 1424 /* Selected drive */ 1425 fdctrl->cur_drv = value & FD_DOR_SELMASK; 1426 1427 fdctrl->dor = value; 1428 } 1429 1430 /* Tape drive register : 0x03 */ 1431 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) 1432 { 1433 uint32_t retval = fdctrl->tdr; 1434 1435 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); 1436 1437 return retval; 1438 } 1439 1440 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) 1441 { 1442 /* Reset mode */ 1443 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1444 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1445 return; 1446 } 1447 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); 1448 /* Disk boot selection indicator */ 1449 fdctrl->tdr = value & FD_TDR_BOOTSEL; 1450 /* Tape indicators: never allow */ 1451 } 1452 1453 /* Main status register : 0x04 (read) */ 1454 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) 1455 { 1456 uint32_t retval = fdctrl->msr; 1457 1458 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1459 fdctrl->dor |= FD_DOR_nRESET; 1460 1461 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); 1462 1463 return retval; 1464 } 1465 1466 /* Data select rate register : 0x04 (write) */ 1467 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) 1468 { 1469 /* Reset mode */ 1470 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1471 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1472 return; 1473 } 1474 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); 1475 /* Reset: autoclear */ 1476 if (value & FD_DSR_SWRESET) { 1477 fdctrl->dor &= ~FD_DOR_nRESET; 1478 fdctrl_reset(fdctrl, 1); 1479 fdctrl->dor |= FD_DOR_nRESET; 1480 } 1481 if (value & FD_DSR_PWRDOWN) { 1482 fdctrl_reset(fdctrl, 1); 1483 } 1484 fdctrl->dsr = value; 1485 } 1486 1487 /* Configuration control register: 0x07 (write) */ 1488 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) 1489 { 1490 /* Reset mode */ 1491 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1492 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1493 return; 1494 } 1495 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); 1496 1497 /* Only the rate selection bits used in AT mode, and we 1498 * store those in the DSR. 1499 */ 1500 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | 1501 (value & FD_DSR_DRATEMASK); 1502 } 1503 1504 static int fdctrl_media_changed(FDrive *drv) 1505 { 1506 return drv->media_changed; 1507 } 1508 1509 /* Digital input register : 0x07 (read-only) */ 1510 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) 1511 { 1512 uint32_t retval = 0; 1513 1514 if (fdctrl_media_changed(get_cur_drv(fdctrl))) { 1515 retval |= FD_DIR_DSKCHG; 1516 } 1517 if (retval != 0) { 1518 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); 1519 } 1520 1521 return retval; 1522 } 1523 1524 /* Clear the FIFO and update the state for receiving the next command */ 1525 static void fdctrl_to_command_phase(FDCtrl *fdctrl) 1526 { 1527 fdctrl->phase = FD_PHASE_COMMAND; 1528 fdctrl->data_dir = FD_DIR_WRITE; 1529 fdctrl->data_pos = 0; 1530 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */ 1531 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); 1532 fdctrl->msr |= FD_MSR_RQM; 1533 } 1534 1535 /* Update the state to allow the guest to read out the command status. 1536 * @fifo_len is the number of result bytes to be read out. */ 1537 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len) 1538 { 1539 fdctrl->phase = FD_PHASE_RESULT; 1540 fdctrl->data_dir = FD_DIR_READ; 1541 fdctrl->data_len = fifo_len; 1542 fdctrl->data_pos = 0; 1543 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; 1544 } 1545 1546 /* Set an error: unimplemented/unknown command */ 1547 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) 1548 { 1549 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n", 1550 fdctrl->fifo[0]); 1551 fdctrl->fifo[0] = FD_SR0_INVCMD; 1552 fdctrl_to_result_phase(fdctrl, 1); 1553 } 1554 1555 /* Seek to next sector 1556 * returns 0 when end of track reached (for DBL_SIDES on head 1) 1557 * otherwise returns 1 1558 */ 1559 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) 1560 { 1561 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", 1562 cur_drv->head, cur_drv->track, cur_drv->sect, 1563 fd_sector(cur_drv)); 1564 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an 1565 error in fact */ 1566 uint8_t new_head = cur_drv->head; 1567 uint8_t new_track = cur_drv->track; 1568 uint8_t new_sect = cur_drv->sect; 1569 1570 int ret = 1; 1571 1572 if (new_sect >= cur_drv->last_sect || 1573 new_sect == fdctrl->eot) { 1574 new_sect = 1; 1575 if (FD_MULTI_TRACK(fdctrl->data_state)) { 1576 if (new_head == 0 && 1577 (cur_drv->flags & FDISK_DBL_SIDES) != 0) { 1578 new_head = 1; 1579 } else { 1580 new_head = 0; 1581 new_track++; 1582 fdctrl->status0 |= FD_SR0_SEEK; 1583 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) { 1584 ret = 0; 1585 } 1586 } 1587 } else { 1588 fdctrl->status0 |= FD_SR0_SEEK; 1589 new_track++; 1590 ret = 0; 1591 } 1592 if (ret == 1) { 1593 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", 1594 new_head, new_track, new_sect, fd_sector(cur_drv)); 1595 } 1596 } else { 1597 new_sect++; 1598 } 1599 fd_seek(cur_drv, new_head, new_track, new_sect, 1); 1600 return ret; 1601 } 1602 1603 /* Callback for transfer end (stop or abort) */ 1604 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, 1605 uint8_t status1, uint8_t status2) 1606 { 1607 FDrive *cur_drv; 1608 cur_drv = get_cur_drv(fdctrl); 1609 1610 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD); 1611 fdctrl->status0 |= GET_CUR_DRV(fdctrl); 1612 if (cur_drv->head) { 1613 fdctrl->status0 |= FD_SR0_HEAD; 1614 } 1615 fdctrl->status0 |= status0; 1616 1617 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", 1618 status0, status1, status2, fdctrl->status0); 1619 fdctrl->fifo[0] = fdctrl->status0; 1620 fdctrl->fifo[1] = status1; 1621 fdctrl->fifo[2] = status2; 1622 fdctrl->fifo[3] = cur_drv->track; 1623 fdctrl->fifo[4] = cur_drv->head; 1624 fdctrl->fifo[5] = cur_drv->sect; 1625 fdctrl->fifo[6] = FD_SECTOR_SC; 1626 fdctrl->data_dir = FD_DIR_READ; 1627 if (!(fdctrl->msr & FD_MSR_NONDMA)) { 1628 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma); 1629 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann); 1630 } 1631 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 1632 fdctrl->msr &= ~FD_MSR_NONDMA; 1633 1634 fdctrl_to_result_phase(fdctrl, 7); 1635 fdctrl_raise_irq(fdctrl); 1636 } 1637 1638 /* Prepare a data transfer (either DMA or FIFO) */ 1639 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) 1640 { 1641 FDrive *cur_drv; 1642 uint8_t kh, kt, ks; 1643 1644 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1645 cur_drv = get_cur_drv(fdctrl); 1646 kt = fdctrl->fifo[2]; 1647 kh = fdctrl->fifo[3]; 1648 ks = fdctrl->fifo[4]; 1649 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", 1650 GET_CUR_DRV(fdctrl), kh, kt, ks, 1651 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1652 NUM_SIDES(cur_drv))); 1653 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1654 case 2: 1655 /* sect too big */ 1656 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1657 fdctrl->fifo[3] = kt; 1658 fdctrl->fifo[4] = kh; 1659 fdctrl->fifo[5] = ks; 1660 return; 1661 case 3: 1662 /* track too big */ 1663 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1664 fdctrl->fifo[3] = kt; 1665 fdctrl->fifo[4] = kh; 1666 fdctrl->fifo[5] = ks; 1667 return; 1668 case 4: 1669 /* No seek enabled */ 1670 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1671 fdctrl->fifo[3] = kt; 1672 fdctrl->fifo[4] = kh; 1673 fdctrl->fifo[5] = ks; 1674 return; 1675 case 1: 1676 fdctrl->status0 |= FD_SR0_SEEK; 1677 break; 1678 default: 1679 break; 1680 } 1681 1682 /* Check the data rate. If the programmed data rate does not match 1683 * the currently inserted medium, the operation has to fail. */ 1684 if (fdctrl->check_media_rate && 1685 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 1686 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n", 1687 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 1688 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 1689 fdctrl->fifo[3] = kt; 1690 fdctrl->fifo[4] = kh; 1691 fdctrl->fifo[5] = ks; 1692 return; 1693 } 1694 1695 /* Set the FIFO state */ 1696 fdctrl->data_dir = direction; 1697 fdctrl->data_pos = 0; 1698 assert(fdctrl->msr & FD_MSR_CMDBUSY); 1699 if (fdctrl->fifo[0] & 0x80) 1700 fdctrl->data_state |= FD_STATE_MULTI; 1701 else 1702 fdctrl->data_state &= ~FD_STATE_MULTI; 1703 if (fdctrl->fifo[5] == 0) { 1704 fdctrl->data_len = fdctrl->fifo[8]; 1705 } else { 1706 int tmp; 1707 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); 1708 tmp = (fdctrl->fifo[6] - ks + 1); 1709 if (fdctrl->fifo[0] & 0x80) 1710 tmp += fdctrl->fifo[6]; 1711 fdctrl->data_len *= tmp; 1712 } 1713 fdctrl->eot = fdctrl->fifo[6]; 1714 if (fdctrl->dor & FD_DOR_DMAEN) { 1715 IsaDmaTransferMode dma_mode; 1716 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma); 1717 bool dma_mode_ok; 1718 /* DMA transfer are enabled. Check if DMA channel is well programmed */ 1719 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann); 1720 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", 1721 dma_mode, direction, 1722 (128 << fdctrl->fifo[5]) * 1723 (cur_drv->last_sect - ks + 1), fdctrl->data_len); 1724 switch (direction) { 1725 case FD_DIR_SCANE: 1726 case FD_DIR_SCANL: 1727 case FD_DIR_SCANH: 1728 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY); 1729 break; 1730 case FD_DIR_WRITE: 1731 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE); 1732 break; 1733 case FD_DIR_READ: 1734 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ); 1735 break; 1736 case FD_DIR_VERIFY: 1737 dma_mode_ok = true; 1738 break; 1739 default: 1740 dma_mode_ok = false; 1741 break; 1742 } 1743 if (dma_mode_ok) { 1744 /* No access is allowed until DMA transfer has completed */ 1745 fdctrl->msr &= ~FD_MSR_RQM; 1746 if (direction != FD_DIR_VERIFY) { 1747 /* Now, we just have to wait for the DMA controller to 1748 * recall us... 1749 */ 1750 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann); 1751 k->schedule(fdctrl->dma); 1752 } else { 1753 /* Start transfer */ 1754 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, 1755 fdctrl->data_len); 1756 } 1757 return; 1758 } else { 1759 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode, 1760 direction); 1761 } 1762 } 1763 FLOPPY_DPRINTF("start non-DMA transfer\n"); 1764 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM; 1765 if (direction != FD_DIR_WRITE) 1766 fdctrl->msr |= FD_MSR_DIO; 1767 /* IO based transfer: calculate len */ 1768 fdctrl_raise_irq(fdctrl); 1769 } 1770 1771 /* Prepare a transfer of deleted data */ 1772 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) 1773 { 1774 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n"); 1775 1776 /* We don't handle deleted data, 1777 * so we don't return *ANYTHING* 1778 */ 1779 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1780 } 1781 1782 /* handlers for DMA transfers */ 1783 static int fdctrl_transfer_handler (void *opaque, int nchan, 1784 int dma_pos, int dma_len) 1785 { 1786 FDCtrl *fdctrl; 1787 FDrive *cur_drv; 1788 int len, start_pos, rel_pos; 1789 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; 1790 IsaDmaClass *k; 1791 1792 fdctrl = opaque; 1793 if (fdctrl->msr & FD_MSR_RQM) { 1794 FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); 1795 return 0; 1796 } 1797 k = ISADMA_GET_CLASS(fdctrl->dma); 1798 cur_drv = get_cur_drv(fdctrl); 1799 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || 1800 fdctrl->data_dir == FD_DIR_SCANH) 1801 status2 = FD_SR2_SNS; 1802 if (dma_len > fdctrl->data_len) 1803 dma_len = fdctrl->data_len; 1804 if (cur_drv->blk == NULL) { 1805 if (fdctrl->data_dir == FD_DIR_WRITE) 1806 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1807 else 1808 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1809 len = 0; 1810 goto transfer_error; 1811 } 1812 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1813 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { 1814 len = dma_len - fdctrl->data_pos; 1815 if (len + rel_pos > FD_SECTOR_LEN) 1816 len = FD_SECTOR_LEN - rel_pos; 1817 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " 1818 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, 1819 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, 1820 cur_drv->track, cur_drv->sect, fd_sector(cur_drv), 1821 fd_sector(cur_drv) * FD_SECTOR_LEN); 1822 if (fdctrl->data_dir != FD_DIR_WRITE || 1823 len < FD_SECTOR_LEN || rel_pos != 0) { 1824 /* READ & SCAN commands and realign to a sector for WRITE */ 1825 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), 1826 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) { 1827 FLOPPY_DPRINTF("Floppy: error getting sector %d\n", 1828 fd_sector(cur_drv)); 1829 /* Sure, image size is too small... */ 1830 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1831 } 1832 } 1833 switch (fdctrl->data_dir) { 1834 case FD_DIR_READ: 1835 /* READ commands */ 1836 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos, 1837 fdctrl->data_pos, len); 1838 break; 1839 case FD_DIR_WRITE: 1840 /* WRITE commands */ 1841 if (cur_drv->ro) { 1842 /* Handle readonly medium early, no need to do DMA, touch the 1843 * LED or attempt any writes. A real floppy doesn't attempt 1844 * to write to readonly media either. */ 1845 fdctrl_stop_transfer(fdctrl, 1846 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, 1847 0x00); 1848 goto transfer_error; 1849 } 1850 1851 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos, 1852 fdctrl->data_pos, len); 1853 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), 1854 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) { 1855 FLOPPY_DPRINTF("error writing sector %d\n", 1856 fd_sector(cur_drv)); 1857 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1858 goto transfer_error; 1859 } 1860 break; 1861 case FD_DIR_VERIFY: 1862 /* VERIFY commands */ 1863 break; 1864 default: 1865 /* SCAN commands */ 1866 { 1867 uint8_t tmpbuf[FD_SECTOR_LEN]; 1868 int ret; 1869 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos, 1870 len); 1871 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); 1872 if (ret == 0) { 1873 status2 = FD_SR2_SEH; 1874 goto end_transfer; 1875 } 1876 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || 1877 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { 1878 status2 = 0x00; 1879 goto end_transfer; 1880 } 1881 } 1882 break; 1883 } 1884 fdctrl->data_pos += len; 1885 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1886 if (rel_pos == 0) { 1887 /* Seek to next sector */ 1888 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) 1889 break; 1890 } 1891 } 1892 end_transfer: 1893 len = fdctrl->data_pos - start_pos; 1894 FLOPPY_DPRINTF("end transfer %d %d %d\n", 1895 fdctrl->data_pos, len, fdctrl->data_len); 1896 if (fdctrl->data_dir == FD_DIR_SCANE || 1897 fdctrl->data_dir == FD_DIR_SCANL || 1898 fdctrl->data_dir == FD_DIR_SCANH) 1899 status2 = FD_SR2_SEH; 1900 fdctrl->data_len -= len; 1901 fdctrl_stop_transfer(fdctrl, status0, status1, status2); 1902 transfer_error: 1903 1904 return len; 1905 } 1906 1907 /* Data register : 0x05 */ 1908 static uint32_t fdctrl_read_data(FDCtrl *fdctrl) 1909 { 1910 FDrive *cur_drv; 1911 uint32_t retval = 0; 1912 uint32_t pos; 1913 1914 cur_drv = get_cur_drv(fdctrl); 1915 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1916 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { 1917 FLOPPY_DPRINTF("error: controller not ready for reading\n"); 1918 return 0; 1919 } 1920 1921 /* If data_len spans multiple sectors, the current position in the FIFO 1922 * wraps around while fdctrl->data_pos is the real position in the whole 1923 * request. */ 1924 pos = fdctrl->data_pos; 1925 pos %= FD_SECTOR_LEN; 1926 1927 switch (fdctrl->phase) { 1928 case FD_PHASE_EXECUTION: 1929 assert(fdctrl->msr & FD_MSR_NONDMA); 1930 if (pos == 0) { 1931 if (fdctrl->data_pos != 0) 1932 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1933 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1934 fd_sector(cur_drv)); 1935 return 0; 1936 } 1937 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo, 1938 BDRV_SECTOR_SIZE) 1939 < 0) { 1940 FLOPPY_DPRINTF("error getting sector %d\n", 1941 fd_sector(cur_drv)); 1942 /* Sure, image size is too small... */ 1943 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1944 } 1945 } 1946 1947 if (++fdctrl->data_pos == fdctrl->data_len) { 1948 fdctrl->msr &= ~FD_MSR_RQM; 1949 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1950 } 1951 break; 1952 1953 case FD_PHASE_RESULT: 1954 assert(!(fdctrl->msr & FD_MSR_NONDMA)); 1955 if (++fdctrl->data_pos == fdctrl->data_len) { 1956 fdctrl->msr &= ~FD_MSR_RQM; 1957 fdctrl_to_command_phase(fdctrl); 1958 fdctrl_reset_irq(fdctrl); 1959 } 1960 break; 1961 1962 case FD_PHASE_COMMAND: 1963 default: 1964 abort(); 1965 } 1966 1967 retval = fdctrl->fifo[pos]; 1968 FLOPPY_DPRINTF("data register: 0x%02x\n", retval); 1969 1970 return retval; 1971 } 1972 1973 static void fdctrl_format_sector(FDCtrl *fdctrl) 1974 { 1975 FDrive *cur_drv; 1976 uint8_t kh, kt, ks; 1977 1978 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1979 cur_drv = get_cur_drv(fdctrl); 1980 kt = fdctrl->fifo[6]; 1981 kh = fdctrl->fifo[7]; 1982 ks = fdctrl->fifo[8]; 1983 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", 1984 GET_CUR_DRV(fdctrl), kh, kt, ks, 1985 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1986 NUM_SIDES(cur_drv))); 1987 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1988 case 2: 1989 /* sect too big */ 1990 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1991 fdctrl->fifo[3] = kt; 1992 fdctrl->fifo[4] = kh; 1993 fdctrl->fifo[5] = ks; 1994 return; 1995 case 3: 1996 /* track too big */ 1997 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1998 fdctrl->fifo[3] = kt; 1999 fdctrl->fifo[4] = kh; 2000 fdctrl->fifo[5] = ks; 2001 return; 2002 case 4: 2003 /* No seek enabled */ 2004 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 2005 fdctrl->fifo[3] = kt; 2006 fdctrl->fifo[4] = kh; 2007 fdctrl->fifo[5] = ks; 2008 return; 2009 case 1: 2010 fdctrl->status0 |= FD_SR0_SEEK; 2011 break; 2012 default: 2013 break; 2014 } 2015 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 2016 if (cur_drv->blk == NULL || 2017 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo, 2018 BDRV_SECTOR_SIZE, 0) < 0) { 2019 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv)); 2020 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 2021 } else { 2022 if (cur_drv->sect == cur_drv->last_sect) { 2023 fdctrl->data_state &= ~FD_STATE_FORMAT; 2024 /* Last sector done */ 2025 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2026 } else { 2027 /* More to do */ 2028 fdctrl->data_pos = 0; 2029 fdctrl->data_len = 4; 2030 } 2031 } 2032 } 2033 2034 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) 2035 { 2036 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; 2037 fdctrl->fifo[0] = fdctrl->lock << 4; 2038 fdctrl_to_result_phase(fdctrl, 1); 2039 } 2040 2041 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) 2042 { 2043 FDrive *cur_drv = get_cur_drv(fdctrl); 2044 2045 /* Drives position */ 2046 fdctrl->fifo[0] = drv0(fdctrl)->track; 2047 fdctrl->fifo[1] = drv1(fdctrl)->track; 2048 #if MAX_FD == 4 2049 fdctrl->fifo[2] = drv2(fdctrl)->track; 2050 fdctrl->fifo[3] = drv3(fdctrl)->track; 2051 #else 2052 fdctrl->fifo[2] = 0; 2053 fdctrl->fifo[3] = 0; 2054 #endif 2055 /* timers */ 2056 fdctrl->fifo[4] = fdctrl->timer0; 2057 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); 2058 fdctrl->fifo[6] = cur_drv->last_sect; 2059 fdctrl->fifo[7] = (fdctrl->lock << 7) | 2060 (cur_drv->perpendicular << 2); 2061 fdctrl->fifo[8] = fdctrl->config; 2062 fdctrl->fifo[9] = fdctrl->precomp_trk; 2063 fdctrl_to_result_phase(fdctrl, 10); 2064 } 2065 2066 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) 2067 { 2068 /* Controller's version */ 2069 fdctrl->fifo[0] = fdctrl->version; 2070 fdctrl_to_result_phase(fdctrl, 1); 2071 } 2072 2073 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) 2074 { 2075 fdctrl->fifo[0] = 0x41; /* Stepping 1 */ 2076 fdctrl_to_result_phase(fdctrl, 1); 2077 } 2078 2079 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) 2080 { 2081 FDrive *cur_drv = get_cur_drv(fdctrl); 2082 2083 /* Drives position */ 2084 drv0(fdctrl)->track = fdctrl->fifo[3]; 2085 drv1(fdctrl)->track = fdctrl->fifo[4]; 2086 #if MAX_FD == 4 2087 drv2(fdctrl)->track = fdctrl->fifo[5]; 2088 drv3(fdctrl)->track = fdctrl->fifo[6]; 2089 #endif 2090 /* timers */ 2091 fdctrl->timer0 = fdctrl->fifo[7]; 2092 fdctrl->timer1 = fdctrl->fifo[8]; 2093 cur_drv->last_sect = fdctrl->fifo[9]; 2094 fdctrl->lock = fdctrl->fifo[10] >> 7; 2095 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; 2096 fdctrl->config = fdctrl->fifo[11]; 2097 fdctrl->precomp_trk = fdctrl->fifo[12]; 2098 fdctrl->pwrd = fdctrl->fifo[13]; 2099 fdctrl_to_command_phase(fdctrl); 2100 } 2101 2102 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) 2103 { 2104 FDrive *cur_drv = get_cur_drv(fdctrl); 2105 2106 fdctrl->fifo[0] = 0; 2107 fdctrl->fifo[1] = 0; 2108 /* Drives position */ 2109 fdctrl->fifo[2] = drv0(fdctrl)->track; 2110 fdctrl->fifo[3] = drv1(fdctrl)->track; 2111 #if MAX_FD == 4 2112 fdctrl->fifo[4] = drv2(fdctrl)->track; 2113 fdctrl->fifo[5] = drv3(fdctrl)->track; 2114 #else 2115 fdctrl->fifo[4] = 0; 2116 fdctrl->fifo[5] = 0; 2117 #endif 2118 /* timers */ 2119 fdctrl->fifo[6] = fdctrl->timer0; 2120 fdctrl->fifo[7] = fdctrl->timer1; 2121 fdctrl->fifo[8] = cur_drv->last_sect; 2122 fdctrl->fifo[9] = (fdctrl->lock << 7) | 2123 (cur_drv->perpendicular << 2); 2124 fdctrl->fifo[10] = fdctrl->config; 2125 fdctrl->fifo[11] = fdctrl->precomp_trk; 2126 fdctrl->fifo[12] = fdctrl->pwrd; 2127 fdctrl->fifo[13] = 0; 2128 fdctrl->fifo[14] = 0; 2129 fdctrl_to_result_phase(fdctrl, 15); 2130 } 2131 2132 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) 2133 { 2134 FDrive *cur_drv = get_cur_drv(fdctrl); 2135 2136 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 2137 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 2138 (NANOSECONDS_PER_SECOND / 50)); 2139 } 2140 2141 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) 2142 { 2143 FDrive *cur_drv; 2144 2145 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2146 cur_drv = get_cur_drv(fdctrl); 2147 fdctrl->data_state |= FD_STATE_FORMAT; 2148 if (fdctrl->fifo[0] & 0x80) 2149 fdctrl->data_state |= FD_STATE_MULTI; 2150 else 2151 fdctrl->data_state &= ~FD_STATE_MULTI; 2152 cur_drv->bps = 2153 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; 2154 #if 0 2155 cur_drv->last_sect = 2156 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : 2157 fdctrl->fifo[3] / 2; 2158 #else 2159 cur_drv->last_sect = fdctrl->fifo[3]; 2160 #endif 2161 /* TODO: implement format using DMA expected by the Bochs BIOS 2162 * and Linux fdformat (read 3 bytes per sector via DMA and fill 2163 * the sector with the specified fill byte 2164 */ 2165 fdctrl->data_state &= ~FD_STATE_FORMAT; 2166 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2167 } 2168 2169 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) 2170 { 2171 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; 2172 fdctrl->timer1 = fdctrl->fifo[2] >> 1; 2173 if (fdctrl->fifo[2] & 1) 2174 fdctrl->dor &= ~FD_DOR_DMAEN; 2175 else 2176 fdctrl->dor |= FD_DOR_DMAEN; 2177 /* No result back */ 2178 fdctrl_to_command_phase(fdctrl); 2179 } 2180 2181 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) 2182 { 2183 FDrive *cur_drv; 2184 2185 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2186 cur_drv = get_cur_drv(fdctrl); 2187 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 2188 /* 1 Byte status back */ 2189 fdctrl->fifo[0] = (cur_drv->ro << 6) | 2190 (cur_drv->track == 0 ? 0x10 : 0x00) | 2191 (cur_drv->head << 2) | 2192 GET_CUR_DRV(fdctrl) | 2193 0x28; 2194 fdctrl_to_result_phase(fdctrl, 1); 2195 } 2196 2197 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) 2198 { 2199 FDrive *cur_drv; 2200 2201 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2202 cur_drv = get_cur_drv(fdctrl); 2203 fd_recalibrate(cur_drv); 2204 fdctrl_to_command_phase(fdctrl); 2205 /* Raise Interrupt */ 2206 fdctrl->status0 |= FD_SR0_SEEK; 2207 fdctrl_raise_irq(fdctrl); 2208 } 2209 2210 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) 2211 { 2212 FDrive *cur_drv = get_cur_drv(fdctrl); 2213 2214 if (fdctrl->reset_sensei > 0) { 2215 fdctrl->fifo[0] = 2216 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; 2217 fdctrl->reset_sensei--; 2218 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) { 2219 fdctrl->fifo[0] = FD_SR0_INVCMD; 2220 fdctrl_to_result_phase(fdctrl, 1); 2221 return; 2222 } else { 2223 fdctrl->fifo[0] = 2224 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0)) 2225 | GET_CUR_DRV(fdctrl); 2226 } 2227 2228 fdctrl->fifo[1] = cur_drv->track; 2229 fdctrl_to_result_phase(fdctrl, 2); 2230 fdctrl_reset_irq(fdctrl); 2231 fdctrl->status0 = FD_SR0_RDYCHG; 2232 } 2233 2234 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) 2235 { 2236 FDrive *cur_drv; 2237 2238 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2239 cur_drv = get_cur_drv(fdctrl); 2240 fdctrl_to_command_phase(fdctrl); 2241 /* The seek command just sends step pulses to the drive and doesn't care if 2242 * there is a medium inserted of if it's banging the head against the drive. 2243 */ 2244 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1); 2245 /* Raise Interrupt */ 2246 fdctrl->status0 |= FD_SR0_SEEK; 2247 fdctrl_raise_irq(fdctrl); 2248 } 2249 2250 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) 2251 { 2252 FDrive *cur_drv = get_cur_drv(fdctrl); 2253 2254 if (fdctrl->fifo[1] & 0x80) 2255 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; 2256 /* No result back */ 2257 fdctrl_to_command_phase(fdctrl); 2258 } 2259 2260 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) 2261 { 2262 fdctrl->config = fdctrl->fifo[2]; 2263 fdctrl->precomp_trk = fdctrl->fifo[3]; 2264 /* No result back */ 2265 fdctrl_to_command_phase(fdctrl); 2266 } 2267 2268 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) 2269 { 2270 fdctrl->pwrd = fdctrl->fifo[1]; 2271 fdctrl->fifo[0] = fdctrl->fifo[1]; 2272 fdctrl_to_result_phase(fdctrl, 1); 2273 } 2274 2275 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) 2276 { 2277 /* No result back */ 2278 fdctrl_to_command_phase(fdctrl); 2279 } 2280 2281 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) 2282 { 2283 FDrive *cur_drv = get_cur_drv(fdctrl); 2284 uint32_t pos; 2285 2286 pos = fdctrl->data_pos - 1; 2287 pos %= FD_SECTOR_LEN; 2288 if (fdctrl->fifo[pos] & 0x80) { 2289 /* Command parameters done */ 2290 if (fdctrl->fifo[pos] & 0x40) { 2291 fdctrl->fifo[0] = fdctrl->fifo[1]; 2292 fdctrl->fifo[2] = 0; 2293 fdctrl->fifo[3] = 0; 2294 fdctrl_to_result_phase(fdctrl, 4); 2295 } else { 2296 fdctrl_to_command_phase(fdctrl); 2297 } 2298 } else if (fdctrl->data_len > 7) { 2299 /* ERROR */ 2300 fdctrl->fifo[0] = 0x80 | 2301 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); 2302 fdctrl_to_result_phase(fdctrl, 1); 2303 } 2304 } 2305 2306 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) 2307 { 2308 FDrive *cur_drv; 2309 2310 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2311 cur_drv = get_cur_drv(fdctrl); 2312 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { 2313 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1, 2314 cur_drv->sect, 1); 2315 } else { 2316 fd_seek(cur_drv, cur_drv->head, 2317 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1); 2318 } 2319 fdctrl_to_command_phase(fdctrl); 2320 /* Raise Interrupt */ 2321 fdctrl->status0 |= FD_SR0_SEEK; 2322 fdctrl_raise_irq(fdctrl); 2323 } 2324 2325 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) 2326 { 2327 FDrive *cur_drv; 2328 2329 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 2330 cur_drv = get_cur_drv(fdctrl); 2331 if (fdctrl->fifo[2] > cur_drv->track) { 2332 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1); 2333 } else { 2334 fd_seek(cur_drv, cur_drv->head, 2335 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1); 2336 } 2337 fdctrl_to_command_phase(fdctrl); 2338 /* Raise Interrupt */ 2339 fdctrl->status0 |= FD_SR0_SEEK; 2340 fdctrl_raise_irq(fdctrl); 2341 } 2342 2343 /* 2344 * Handlers for the execution phase of each command 2345 */ 2346 typedef struct FDCtrlCommand { 2347 uint8_t value; 2348 uint8_t mask; 2349 const char* name; 2350 int parameters; 2351 void (*handler)(FDCtrl *fdctrl, int direction); 2352 int direction; 2353 } FDCtrlCommand; 2354 2355 static const FDCtrlCommand handlers[] = { 2356 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, 2357 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, 2358 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, 2359 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, 2360 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, 2361 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, 2362 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, 2363 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ 2364 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ 2365 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, 2366 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, 2367 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY }, 2368 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, 2369 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, 2370 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, 2371 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, 2372 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, 2373 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, 2374 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, 2375 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, 2376 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, 2377 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, 2378 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, 2379 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, 2380 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, 2381 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, 2382 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, 2383 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, 2384 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, 2385 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, 2386 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ 2387 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ 2388 }; 2389 /* Associate command to an index in the 'handlers' array */ 2390 static uint8_t command_to_handler[256]; 2391 2392 static const FDCtrlCommand *get_command(uint8_t cmd) 2393 { 2394 int idx; 2395 2396 idx = command_to_handler[cmd]; 2397 FLOPPY_DPRINTF("%s command\n", handlers[idx].name); 2398 return &handlers[idx]; 2399 } 2400 2401 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) 2402 { 2403 FDrive *cur_drv; 2404 const FDCtrlCommand *cmd; 2405 uint32_t pos; 2406 2407 /* Reset mode */ 2408 if (!(fdctrl->dor & FD_DOR_nRESET)) { 2409 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 2410 return; 2411 } 2412 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { 2413 FLOPPY_DPRINTF("error: controller not ready for writing\n"); 2414 return; 2415 } 2416 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 2417 2418 FLOPPY_DPRINTF("%s: %02x\n", __func__, value); 2419 2420 /* If data_len spans multiple sectors, the current position in the FIFO 2421 * wraps around while fdctrl->data_pos is the real position in the whole 2422 * request. */ 2423 pos = fdctrl->data_pos++; 2424 pos %= FD_SECTOR_LEN; 2425 fdctrl->fifo[pos] = value; 2426 2427 if (fdctrl->data_pos == fdctrl->data_len) { 2428 fdctrl->msr &= ~FD_MSR_RQM; 2429 } 2430 2431 switch (fdctrl->phase) { 2432 case FD_PHASE_EXECUTION: 2433 /* For DMA requests, RQM should be cleared during execution phase, so 2434 * we would have errored out above. */ 2435 assert(fdctrl->msr & FD_MSR_NONDMA); 2436 2437 /* FIFO data write */ 2438 if (pos == FD_SECTOR_LEN - 1 || 2439 fdctrl->data_pos == fdctrl->data_len) { 2440 cur_drv = get_cur_drv(fdctrl); 2441 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo, 2442 BDRV_SECTOR_SIZE, 0) < 0) { 2443 FLOPPY_DPRINTF("error writing sector %d\n", 2444 fd_sector(cur_drv)); 2445 break; 2446 } 2447 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 2448 FLOPPY_DPRINTF("error seeking to next sector %d\n", 2449 fd_sector(cur_drv)); 2450 break; 2451 } 2452 } 2453 2454 /* Switch to result phase when done with the transfer */ 2455 if (fdctrl->data_pos == fdctrl->data_len) { 2456 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2457 } 2458 break; 2459 2460 case FD_PHASE_COMMAND: 2461 assert(!(fdctrl->msr & FD_MSR_NONDMA)); 2462 assert(fdctrl->data_pos < FD_SECTOR_LEN); 2463 2464 if (pos == 0) { 2465 /* The first byte specifies the command. Now we start reading 2466 * as many parameters as this command requires. */ 2467 cmd = get_command(value); 2468 fdctrl->data_len = cmd->parameters + 1; 2469 if (cmd->parameters) { 2470 fdctrl->msr |= FD_MSR_RQM; 2471 } 2472 fdctrl->msr |= FD_MSR_CMDBUSY; 2473 } 2474 2475 if (fdctrl->data_pos == fdctrl->data_len) { 2476 /* We have all parameters now, execute the command */ 2477 fdctrl->phase = FD_PHASE_EXECUTION; 2478 2479 if (fdctrl->data_state & FD_STATE_FORMAT) { 2480 fdctrl_format_sector(fdctrl); 2481 break; 2482 } 2483 2484 cmd = get_command(fdctrl->fifo[0]); 2485 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name); 2486 cmd->handler(fdctrl, cmd->direction); 2487 } 2488 break; 2489 2490 case FD_PHASE_RESULT: 2491 default: 2492 abort(); 2493 } 2494 } 2495 2496 static void fdctrl_result_timer(void *opaque) 2497 { 2498 FDCtrl *fdctrl = opaque; 2499 FDrive *cur_drv = get_cur_drv(fdctrl); 2500 2501 /* Pretend we are spinning. 2502 * This is needed for Coherent, which uses READ ID to check for 2503 * sector interleaving. 2504 */ 2505 if (cur_drv->last_sect != 0) { 2506 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; 2507 } 2508 /* READ_ID can't automatically succeed! */ 2509 if (fdctrl->check_media_rate && 2510 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 2511 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n", 2512 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 2513 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 2514 } else { 2515 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2516 } 2517 } 2518 2519 /* Init functions */ 2520 static void fdctrl_connect_drives(FDCtrl *fdctrl, DeviceState *fdc_dev, 2521 Error **errp) 2522 { 2523 unsigned int i; 2524 FDrive *drive; 2525 DeviceState *dev; 2526 BlockBackend *blk; 2527 Error *local_err = NULL; 2528 2529 for (i = 0; i < MAX_FD; i++) { 2530 drive = &fdctrl->drives[i]; 2531 drive->fdctrl = fdctrl; 2532 2533 /* If the drive is not present, we skip creating the qdev device, but 2534 * still have to initialise the controller. */ 2535 blk = fdctrl->qdev_for_drives[i].blk; 2536 if (!blk) { 2537 fd_init(drive); 2538 fd_revalidate(drive); 2539 continue; 2540 } 2541 2542 dev = qdev_create(&fdctrl->bus.bus, "floppy"); 2543 qdev_prop_set_uint32(dev, "unit", i); 2544 qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type); 2545 2546 blk_ref(blk); 2547 blk_detach_dev(blk, fdc_dev); 2548 fdctrl->qdev_for_drives[i].blk = NULL; 2549 qdev_prop_set_drive(dev, "drive", blk, &local_err); 2550 blk_unref(blk); 2551 2552 if (local_err) { 2553 error_propagate(errp, local_err); 2554 return; 2555 } 2556 2557 object_property_set_bool(OBJECT(dev), true, "realized", &local_err); 2558 if (local_err) { 2559 error_propagate(errp, local_err); 2560 return; 2561 } 2562 } 2563 } 2564 2565 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds) 2566 { 2567 DeviceState *dev; 2568 ISADevice *isadev; 2569 2570 isadev = isa_try_create(bus, TYPE_ISA_FDC); 2571 if (!isadev) { 2572 return NULL; 2573 } 2574 dev = DEVICE(isadev); 2575 2576 if (fds[0]) { 2577 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), 2578 &error_fatal); 2579 } 2580 if (fds[1]) { 2581 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), 2582 &error_fatal); 2583 } 2584 qdev_init_nofail(dev); 2585 2586 return isadev; 2587 } 2588 2589 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, 2590 hwaddr mmio_base, DriveInfo **fds) 2591 { 2592 FDCtrl *fdctrl; 2593 DeviceState *dev; 2594 SysBusDevice *sbd; 2595 FDCtrlSysBus *sys; 2596 2597 dev = qdev_create(NULL, "sysbus-fdc"); 2598 sys = SYSBUS_FDC(dev); 2599 fdctrl = &sys->state; 2600 fdctrl->dma_chann = dma_chann; /* FIXME */ 2601 if (fds[0]) { 2602 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), 2603 &error_fatal); 2604 } 2605 if (fds[1]) { 2606 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), 2607 &error_fatal); 2608 } 2609 qdev_init_nofail(dev); 2610 sbd = SYS_BUS_DEVICE(dev); 2611 sysbus_connect_irq(sbd, 0, irq); 2612 sysbus_mmio_map(sbd, 0, mmio_base); 2613 } 2614 2615 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, 2616 DriveInfo **fds, qemu_irq *fdc_tc) 2617 { 2618 DeviceState *dev; 2619 FDCtrlSysBus *sys; 2620 2621 dev = qdev_create(NULL, "SUNW,fdtwo"); 2622 if (fds[0]) { 2623 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]), 2624 &error_fatal); 2625 } 2626 qdev_init_nofail(dev); 2627 sys = SYSBUS_FDC(dev); 2628 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); 2629 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base); 2630 *fdc_tc = qdev_get_gpio_in(dev, 0); 2631 } 2632 2633 static void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl, 2634 Error **errp) 2635 { 2636 int i, j; 2637 static int command_tables_inited = 0; 2638 2639 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) { 2640 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'"); 2641 } 2642 2643 /* Fill 'command_to_handler' lookup table */ 2644 if (!command_tables_inited) { 2645 command_tables_inited = 1; 2646 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { 2647 for (j = 0; j < sizeof(command_to_handler); j++) { 2648 if ((j & handlers[i].mask) == handlers[i].value) { 2649 command_to_handler[j] = i; 2650 } 2651 } 2652 } 2653 } 2654 2655 FLOPPY_DPRINTF("init controller\n"); 2656 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); 2657 fdctrl->fifo_size = 512; 2658 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2659 fdctrl_result_timer, fdctrl); 2660 2661 fdctrl->version = 0x90; /* Intel 82078 controller */ 2662 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ 2663 fdctrl->num_floppies = MAX_FD; 2664 2665 if (fdctrl->dma_chann != -1) { 2666 IsaDmaClass *k; 2667 assert(fdctrl->dma); 2668 k = ISADMA_GET_CLASS(fdctrl->dma); 2669 k->register_channel(fdctrl->dma, fdctrl->dma_chann, 2670 &fdctrl_transfer_handler, fdctrl); 2671 } 2672 2673 floppy_bus_create(fdctrl, &fdctrl->bus, dev); 2674 fdctrl_connect_drives(fdctrl, dev, errp); 2675 } 2676 2677 static const MemoryRegionPortio fdc_portio_list[] = { 2678 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, 2679 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, 2680 PORTIO_END_OF_LIST(), 2681 }; 2682 2683 static void isabus_fdc_realize(DeviceState *dev, Error **errp) 2684 { 2685 ISADevice *isadev = ISA_DEVICE(dev); 2686 FDCtrlISABus *isa = ISA_FDC(dev); 2687 FDCtrl *fdctrl = &isa->state; 2688 Error *err = NULL; 2689 2690 isa_register_portio_list(isadev, &fdctrl->portio_list, 2691 isa->iobase, fdc_portio_list, fdctrl, 2692 "fdc"); 2693 2694 isa_init_irq(isadev, &fdctrl->irq, isa->irq); 2695 fdctrl->dma_chann = isa->dma; 2696 if (fdctrl->dma_chann != -1) { 2697 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma); 2698 if (!fdctrl->dma) { 2699 error_setg(errp, "ISA controller does not support DMA"); 2700 return; 2701 } 2702 } 2703 2704 qdev_set_legacy_instance_id(dev, isa->iobase, 2); 2705 fdctrl_realize_common(dev, fdctrl, &err); 2706 if (err != NULL) { 2707 error_propagate(errp, err); 2708 return; 2709 } 2710 } 2711 2712 static void sysbus_fdc_initfn(Object *obj) 2713 { 2714 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2715 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2716 FDCtrl *fdctrl = &sys->state; 2717 2718 fdctrl->dma_chann = -1; 2719 2720 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl, 2721 "fdc", 0x08); 2722 sysbus_init_mmio(sbd, &fdctrl->iomem); 2723 } 2724 2725 static void sun4m_fdc_initfn(Object *obj) 2726 { 2727 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2728 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2729 FDCtrl *fdctrl = &sys->state; 2730 2731 fdctrl->dma_chann = -1; 2732 2733 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops, 2734 fdctrl, "fdctrl", 0x08); 2735 sysbus_init_mmio(sbd, &fdctrl->iomem); 2736 } 2737 2738 static void sysbus_fdc_common_initfn(Object *obj) 2739 { 2740 DeviceState *dev = DEVICE(obj); 2741 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 2742 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2743 FDCtrl *fdctrl = &sys->state; 2744 2745 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */ 2746 2747 sysbus_init_irq(sbd, &fdctrl->irq); 2748 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1); 2749 } 2750 2751 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp) 2752 { 2753 FDCtrlSysBus *sys = SYSBUS_FDC(dev); 2754 FDCtrl *fdctrl = &sys->state; 2755 2756 fdctrl_realize_common(dev, fdctrl, errp); 2757 } 2758 2759 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i) 2760 { 2761 FDCtrlISABus *isa = ISA_FDC(fdc); 2762 2763 return isa->state.drives[i].drive; 2764 } 2765 2766 void isa_fdc_get_drive_max_chs(FloppyDriveType type, 2767 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs) 2768 { 2769 const FDFormat *fdf; 2770 2771 *maxc = *maxh = *maxs = 0; 2772 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) { 2773 if (fdf->drive != type) { 2774 continue; 2775 } 2776 if (*maxc < fdf->max_track) { 2777 *maxc = fdf->max_track; 2778 } 2779 if (*maxh < fdf->max_head) { 2780 *maxh = fdf->max_head; 2781 } 2782 if (*maxs < fdf->last_sect) { 2783 *maxs = fdf->last_sect; 2784 } 2785 } 2786 (*maxc)--; 2787 } 2788 2789 static const VMStateDescription vmstate_isa_fdc ={ 2790 .name = "fdc", 2791 .version_id = 2, 2792 .minimum_version_id = 2, 2793 .fields = (VMStateField[]) { 2794 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl), 2795 VMSTATE_END_OF_LIST() 2796 } 2797 }; 2798 2799 static Property isa_fdc_properties[] = { 2800 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0), 2801 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6), 2802 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2), 2803 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.qdev_for_drives[0].blk), 2804 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.qdev_for_drives[1].blk), 2805 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate, 2806 0, true), 2807 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlISABus, state.qdev_for_drives[0].type, 2808 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2809 FloppyDriveType), 2810 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlISABus, state.qdev_for_drives[1].type, 2811 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2812 FloppyDriveType), 2813 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback, 2814 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type, 2815 FloppyDriveType), 2816 DEFINE_PROP_END_OF_LIST(), 2817 }; 2818 2819 static void isabus_fdc_class_init(ObjectClass *klass, void *data) 2820 { 2821 DeviceClass *dc = DEVICE_CLASS(klass); 2822 2823 dc->realize = isabus_fdc_realize; 2824 dc->fw_name = "fdc"; 2825 dc->reset = fdctrl_external_reset_isa; 2826 dc->vmsd = &vmstate_isa_fdc; 2827 dc->props = isa_fdc_properties; 2828 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2829 } 2830 2831 static void isabus_fdc_instance_init(Object *obj) 2832 { 2833 FDCtrlISABus *isa = ISA_FDC(obj); 2834 2835 device_add_bootindex_property(obj, &isa->bootindexA, 2836 "bootindexA", "/floppy@0", 2837 DEVICE(obj), NULL); 2838 device_add_bootindex_property(obj, &isa->bootindexB, 2839 "bootindexB", "/floppy@1", 2840 DEVICE(obj), NULL); 2841 } 2842 2843 static const TypeInfo isa_fdc_info = { 2844 .name = TYPE_ISA_FDC, 2845 .parent = TYPE_ISA_DEVICE, 2846 .instance_size = sizeof(FDCtrlISABus), 2847 .class_init = isabus_fdc_class_init, 2848 .instance_init = isabus_fdc_instance_init, 2849 }; 2850 2851 static const VMStateDescription vmstate_sysbus_fdc ={ 2852 .name = "fdc", 2853 .version_id = 2, 2854 .minimum_version_id = 2, 2855 .fields = (VMStateField[]) { 2856 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl), 2857 VMSTATE_END_OF_LIST() 2858 } 2859 }; 2860 2861 static Property sysbus_fdc_properties[] = { 2862 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.qdev_for_drives[0].blk), 2863 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.qdev_for_drives[1].blk), 2864 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlSysBus, state.qdev_for_drives[0].type, 2865 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2866 FloppyDriveType), 2867 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlSysBus, state.qdev_for_drives[1].type, 2868 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2869 FloppyDriveType), 2870 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback, 2871 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type, 2872 FloppyDriveType), 2873 DEFINE_PROP_END_OF_LIST(), 2874 }; 2875 2876 static void sysbus_fdc_class_init(ObjectClass *klass, void *data) 2877 { 2878 DeviceClass *dc = DEVICE_CLASS(klass); 2879 2880 dc->props = sysbus_fdc_properties; 2881 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2882 } 2883 2884 static const TypeInfo sysbus_fdc_info = { 2885 .name = "sysbus-fdc", 2886 .parent = TYPE_SYSBUS_FDC, 2887 .instance_init = sysbus_fdc_initfn, 2888 .class_init = sysbus_fdc_class_init, 2889 }; 2890 2891 static Property sun4m_fdc_properties[] = { 2892 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.qdev_for_drives[0].blk), 2893 DEFINE_PROP_SIGNED("fdtype", FDCtrlSysBus, state.qdev_for_drives[0].type, 2894 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, 2895 FloppyDriveType), 2896 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback, 2897 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type, 2898 FloppyDriveType), 2899 DEFINE_PROP_END_OF_LIST(), 2900 }; 2901 2902 static void sun4m_fdc_class_init(ObjectClass *klass, void *data) 2903 { 2904 DeviceClass *dc = DEVICE_CLASS(klass); 2905 2906 dc->props = sun4m_fdc_properties; 2907 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2908 } 2909 2910 static const TypeInfo sun4m_fdc_info = { 2911 .name = "SUNW,fdtwo", 2912 .parent = TYPE_SYSBUS_FDC, 2913 .instance_init = sun4m_fdc_initfn, 2914 .class_init = sun4m_fdc_class_init, 2915 }; 2916 2917 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data) 2918 { 2919 DeviceClass *dc = DEVICE_CLASS(klass); 2920 2921 dc->realize = sysbus_fdc_common_realize; 2922 dc->reset = fdctrl_external_reset_sysbus; 2923 dc->vmsd = &vmstate_sysbus_fdc; 2924 } 2925 2926 static const TypeInfo sysbus_fdc_type_info = { 2927 .name = TYPE_SYSBUS_FDC, 2928 .parent = TYPE_SYS_BUS_DEVICE, 2929 .instance_size = sizeof(FDCtrlSysBus), 2930 .instance_init = sysbus_fdc_common_initfn, 2931 .abstract = true, 2932 .class_init = sysbus_fdc_common_class_init, 2933 }; 2934 2935 static void fdc_register_types(void) 2936 { 2937 type_register_static(&isa_fdc_info); 2938 type_register_static(&sysbus_fdc_type_info); 2939 type_register_static(&sysbus_fdc_info); 2940 type_register_static(&sun4m_fdc_info); 2941 type_register_static(&floppy_bus_info); 2942 type_register_static(&floppy_drive_info); 2943 } 2944 2945 type_init(fdc_register_types) 2946