1 /* 2 * Arm PrimeCell PL041 Advanced Audio Codec Interface 3 * 4 * Copyright (c) 2011 5 * Written by Mathieu Sonet - www.elasticsheep.com 6 * 7 * This code is licensed under the GPL. 8 * 9 * ***************************************************************** 10 * 11 * This driver emulates the ARM AACI interface 12 * connected to a LM4549 codec. 13 * 14 * Limitations: 15 * - Supports only a playback on one channel (Versatile/Vexpress) 16 * - Supports only one TX FIFO in compact-mode or non-compact mode. 17 * - Supports playback of 12, 16, 18 and 20 bits samples. 18 * - Record is not supported. 19 * - The PL041 is hardwired to a LM4549 codec. 20 * 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/irq.h" 25 #include "hw/sysbus.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 29 #include "pl041.h" 30 #include "lm4549.h" 31 #include "migration/vmstate.h" 32 33 #if 0 34 #define PL041_DEBUG_LEVEL 1 35 #endif 36 37 #if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 1) 38 #define DBG_L1(fmt, ...) \ 39 do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0) 40 #else 41 #define DBG_L1(fmt, ...) \ 42 do { } while (0) 43 #endif 44 45 #if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 2) 46 #define DBG_L2(fmt, ...) \ 47 do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0) 48 #else 49 #define DBG_L2(fmt, ...) \ 50 do { } while (0) 51 #endif 52 53 54 #define MAX_FIFO_DEPTH (1024) 55 #define DEFAULT_FIFO_DEPTH (8) 56 57 #define SLOT1_RW (1 << 19) 58 59 /* This FIFO only stores 20-bit samples on 32-bit words. 60 So its level is independent of the selected mode */ 61 typedef struct { 62 uint32_t level; 63 uint32_t data[MAX_FIFO_DEPTH]; 64 } pl041_fifo; 65 66 typedef struct { 67 pl041_fifo tx_fifo; 68 uint8_t tx_enabled; 69 uint8_t tx_compact_mode; 70 uint8_t tx_sample_size; 71 72 pl041_fifo rx_fifo; 73 uint8_t rx_enabled; 74 uint8_t rx_compact_mode; 75 uint8_t rx_sample_size; 76 } pl041_channel; 77 78 #define TYPE_PL041 "pl041" 79 #define PL041(obj) OBJECT_CHECK(PL041State, (obj), TYPE_PL041) 80 81 typedef struct PL041State { 82 SysBusDevice parent_obj; 83 84 MemoryRegion iomem; 85 qemu_irq irq; 86 87 uint32_t fifo_depth; /* FIFO depth in non-compact mode */ 88 89 pl041_regfile regs; 90 pl041_channel fifo1; 91 lm4549_state codec; 92 } PL041State; 93 94 95 static const unsigned char pl041_default_id[8] = { 96 0x41, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 97 }; 98 99 #if defined(PL041_DEBUG_LEVEL) 100 #define REGISTER(name, offset) #name, 101 static const char *pl041_regs_name[] = { 102 #include "pl041.hx" 103 }; 104 #undef REGISTER 105 #endif 106 107 108 #if defined(PL041_DEBUG_LEVEL) 109 static const char *get_reg_name(hwaddr offset) 110 { 111 if (offset <= PL041_dr1_7) { 112 return pl041_regs_name[offset >> 2]; 113 } 114 115 return "unknown"; 116 } 117 #endif 118 119 static uint8_t pl041_compute_periphid3(PL041State *s) 120 { 121 uint8_t id3 = 1; /* One channel */ 122 123 /* Add the fifo depth information */ 124 switch (s->fifo_depth) { 125 case 8: 126 id3 |= 0 << 3; 127 break; 128 case 32: 129 id3 |= 1 << 3; 130 break; 131 case 64: 132 id3 |= 2 << 3; 133 break; 134 case 128: 135 id3 |= 3 << 3; 136 break; 137 case 256: 138 id3 |= 4 << 3; 139 break; 140 case 512: 141 id3 |= 5 << 3; 142 break; 143 case 1024: 144 id3 |= 6 << 3; 145 break; 146 case 2048: 147 id3 |= 7 << 3; 148 break; 149 } 150 151 return id3; 152 } 153 154 static void pl041_reset(PL041State *s) 155 { 156 DBG_L1("pl041_reset\n"); 157 158 memset(&s->regs, 0x00, sizeof(pl041_regfile)); 159 160 s->regs.slfr = SL1TXEMPTY | SL2TXEMPTY | SL12TXEMPTY; 161 s->regs.sr1 = TXFE | RXFE | TXHE; 162 s->regs.isr1 = 0; 163 164 memset(&s->fifo1, 0x00, sizeof(s->fifo1)); 165 } 166 167 168 static void pl041_fifo1_write(PL041State *s, uint32_t value) 169 { 170 pl041_channel *channel = &s->fifo1; 171 pl041_fifo *fifo = &s->fifo1.tx_fifo; 172 173 /* Push the value in the FIFO */ 174 if (channel->tx_compact_mode == 0) { 175 /* Non-compact mode */ 176 177 if (fifo->level < s->fifo_depth) { 178 /* Pad the value with 0 to obtain a 20-bit sample */ 179 switch (channel->tx_sample_size) { 180 case 12: 181 value = (value << 8) & 0xFFFFF; 182 break; 183 case 16: 184 value = (value << 4) & 0xFFFFF; 185 break; 186 case 18: 187 value = (value << 2) & 0xFFFFF; 188 break; 189 case 20: 190 default: 191 break; 192 } 193 194 /* Store the sample in the FIFO */ 195 fifo->data[fifo->level++] = value; 196 } 197 #if defined(PL041_DEBUG_LEVEL) 198 else { 199 DBG_L1("fifo1 write: overrun\n"); 200 } 201 #endif 202 } else { 203 /* Compact mode */ 204 205 if ((fifo->level + 2) < s->fifo_depth) { 206 uint32_t i = 0; 207 uint32_t sample = 0; 208 209 for (i = 0; i < 2; i++) { 210 sample = value & 0xFFFF; 211 value = value >> 16; 212 213 /* Pad each sample with 0 to obtain a 20-bit sample */ 214 switch (channel->tx_sample_size) { 215 case 12: 216 sample = sample << 8; 217 break; 218 case 16: 219 default: 220 sample = sample << 4; 221 break; 222 } 223 224 /* Store the sample in the FIFO */ 225 fifo->data[fifo->level++] = sample; 226 } 227 } 228 #if defined(PL041_DEBUG_LEVEL) 229 else { 230 DBG_L1("fifo1 write: overrun\n"); 231 } 232 #endif 233 } 234 235 /* Update the status register */ 236 if (fifo->level > 0) { 237 s->regs.sr1 &= ~(TXUNDERRUN | TXFE); 238 } 239 240 if (fifo->level >= (s->fifo_depth / 2)) { 241 s->regs.sr1 &= ~TXHE; 242 } 243 244 if (fifo->level >= s->fifo_depth) { 245 s->regs.sr1 |= TXFF; 246 } 247 248 DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1); 249 } 250 251 static void pl041_fifo1_transmit(PL041State *s) 252 { 253 pl041_channel *channel = &s->fifo1; 254 pl041_fifo *fifo = &s->fifo1.tx_fifo; 255 uint32_t slots = s->regs.txcr1 & TXSLOT_MASK; 256 uint32_t written_samples; 257 258 /* Check if FIFO1 transmit is enabled */ 259 if ((channel->tx_enabled) && (slots & (TXSLOT3 | TXSLOT4))) { 260 if (fifo->level >= (s->fifo_depth / 2)) { 261 int i; 262 263 DBG_L1("Transfer FIFO level = %i\n", fifo->level); 264 265 /* Try to transfer the whole FIFO */ 266 for (i = 0; i < (fifo->level / 2); i++) { 267 uint32_t left = fifo->data[i * 2]; 268 uint32_t right = fifo->data[i * 2 + 1]; 269 270 /* Transmit two 20-bit samples to the codec */ 271 if (lm4549_write_samples(&s->codec, left, right) == 0) { 272 DBG_L1("Codec buffer full\n"); 273 break; 274 } 275 } 276 277 written_samples = i * 2; 278 if (written_samples > 0) { 279 /* Update the FIFO level */ 280 fifo->level -= written_samples; 281 282 /* Move back the pending samples to the start of the FIFO */ 283 for (i = 0; i < fifo->level; i++) { 284 fifo->data[i] = fifo->data[written_samples + i]; 285 } 286 287 /* Update the status register */ 288 s->regs.sr1 &= ~TXFF; 289 290 if (fifo->level <= (s->fifo_depth / 2)) { 291 s->regs.sr1 |= TXHE; 292 } 293 294 if (fifo->level == 0) { 295 s->regs.sr1 |= TXFE | TXUNDERRUN; 296 DBG_L1("Empty FIFO\n"); 297 } 298 } 299 } 300 } 301 } 302 303 static void pl041_isr1_update(PL041State *s) 304 { 305 /* Update ISR1 */ 306 if (s->regs.sr1 & TXUNDERRUN) { 307 s->regs.isr1 |= URINTR; 308 } else { 309 s->regs.isr1 &= ~URINTR; 310 } 311 312 if (s->regs.sr1 & TXHE) { 313 s->regs.isr1 |= TXINTR; 314 } else { 315 s->regs.isr1 &= ~TXINTR; 316 } 317 318 if (!(s->regs.sr1 & TXBUSY) && (s->regs.sr1 & TXFE)) { 319 s->regs.isr1 |= TXCINTR; 320 } else { 321 s->regs.isr1 &= ~TXCINTR; 322 } 323 324 /* Update the irq state */ 325 qemu_set_irq(s->irq, ((s->regs.isr1 & s->regs.ie1) > 0) ? 1 : 0); 326 DBG_L2("Set interrupt sr1 = 0x%08x isr1 = 0x%08x masked = 0x%08x\n", 327 s->regs.sr1, s->regs.isr1, s->regs.isr1 & s->regs.ie1); 328 } 329 330 static void pl041_request_data(void *opaque) 331 { 332 PL041State *s = (PL041State *)opaque; 333 334 /* Trigger pending transfers */ 335 pl041_fifo1_transmit(s); 336 pl041_isr1_update(s); 337 } 338 339 static uint64_t pl041_read(void *opaque, hwaddr offset, 340 unsigned size) 341 { 342 PL041State *s = (PL041State *)opaque; 343 int value; 344 345 if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) { 346 if (offset == PL041_periphid3) { 347 value = pl041_compute_periphid3(s); 348 } else { 349 value = pl041_default_id[(offset - PL041_periphid0) >> 2]; 350 } 351 352 DBG_L1("pl041_read [0x%08x] => 0x%08x\n", offset, value); 353 return value; 354 } else if (offset <= PL041_dr4_7) { 355 value = *((uint32_t *)&s->regs + (offset >> 2)); 356 } else { 357 DBG_L1("pl041_read: Reserved offset %x\n", (int)offset); 358 return 0; 359 } 360 361 switch (offset) { 362 case PL041_allints: 363 value = s->regs.isr1 & 0x7F; 364 break; 365 } 366 367 DBG_L1("pl041_read [0x%08x] %s => 0x%08x\n", offset, 368 get_reg_name(offset), value); 369 370 return value; 371 } 372 373 static void pl041_write(void *opaque, hwaddr offset, 374 uint64_t value, unsigned size) 375 { 376 PL041State *s = (PL041State *)opaque; 377 uint16_t control, data; 378 uint32_t result; 379 380 DBG_L1("pl041_write [0x%08x] %s <= 0x%08x\n", offset, 381 get_reg_name(offset), (unsigned int)value); 382 383 /* Write the register */ 384 if (offset <= PL041_dr4_7) { 385 *((uint32_t *)&s->regs + (offset >> 2)) = value; 386 } else { 387 DBG_L1("pl041_write: Reserved offset %x\n", (int)offset); 388 return; 389 } 390 391 /* Execute the actions */ 392 switch (offset) { 393 case PL041_txcr1: 394 { 395 pl041_channel *channel = &s->fifo1; 396 397 uint32_t txen = s->regs.txcr1 & TXEN; 398 uint32_t tsize = (s->regs.txcr1 & TSIZE_MASK) >> TSIZE_MASK_BIT; 399 uint32_t compact_mode = (s->regs.txcr1 & TXCOMPACT) ? 1 : 0; 400 #if defined(PL041_DEBUG_LEVEL) 401 uint32_t slots = (s->regs.txcr1 & TXSLOT_MASK) >> TXSLOT_MASK_BIT; 402 uint32_t txfen = (s->regs.txcr1 & TXFEN) > 0 ? 1 : 0; 403 #endif 404 405 DBG_L1("=> txen = %i slots = 0x%01x tsize = %i compact = %i " 406 "txfen = %i\n", txen, slots, tsize, compact_mode, txfen); 407 408 channel->tx_enabled = txen; 409 channel->tx_compact_mode = compact_mode; 410 411 switch (tsize) { 412 case 0: 413 channel->tx_sample_size = 16; 414 break; 415 case 1: 416 channel->tx_sample_size = 18; 417 break; 418 case 2: 419 channel->tx_sample_size = 20; 420 break; 421 case 3: 422 channel->tx_sample_size = 12; 423 break; 424 } 425 426 DBG_L1("TX enabled = %i\n", channel->tx_enabled); 427 DBG_L1("TX compact mode = %i\n", channel->tx_compact_mode); 428 DBG_L1("TX sample width = %i\n", channel->tx_sample_size); 429 430 /* Check if compact mode is allowed with selected tsize */ 431 if (channel->tx_compact_mode == 1) { 432 if ((channel->tx_sample_size == 18) || 433 (channel->tx_sample_size == 20)) { 434 channel->tx_compact_mode = 0; 435 DBG_L1("Compact mode not allowed with 18/20-bit sample size\n"); 436 } 437 } 438 439 break; 440 } 441 case PL041_sl1tx: 442 s->regs.slfr &= ~SL1TXEMPTY; 443 444 control = (s->regs.sl1tx >> 12) & 0x7F; 445 data = (s->regs.sl2tx >> 4) & 0xFFFF; 446 447 if ((s->regs.sl1tx & SLOT1_RW) == 0) { 448 /* Write operation */ 449 lm4549_write(&s->codec, control, data); 450 } else { 451 /* Read operation */ 452 result = lm4549_read(&s->codec, control); 453 454 /* Store the returned value */ 455 s->regs.sl1rx = s->regs.sl1tx & ~SLOT1_RW; 456 s->regs.sl2rx = result << 4; 457 458 s->regs.slfr &= ~(SL1RXBUSY | SL2RXBUSY); 459 s->regs.slfr |= SL1RXVALID | SL2RXVALID; 460 } 461 break; 462 463 case PL041_sl2tx: 464 s->regs.sl2tx = value; 465 s->regs.slfr &= ~SL2TXEMPTY; 466 break; 467 468 case PL041_intclr: 469 DBG_L1("=> Clear interrupt intclr = 0x%08x isr1 = 0x%08x\n", 470 s->regs.intclr, s->regs.isr1); 471 472 if (s->regs.intclr & TXUEC1) { 473 s->regs.sr1 &= ~TXUNDERRUN; 474 } 475 break; 476 477 case PL041_maincr: 478 { 479 #if defined(PL041_DEBUG_LEVEL) 480 char debug[] = " AACIFE SL1RXEN SL1TXEN"; 481 if (!(value & AACIFE)) { 482 debug[0] = '!'; 483 } 484 if (!(value & SL1RXEN)) { 485 debug[8] = '!'; 486 } 487 if (!(value & SL1TXEN)) { 488 debug[17] = '!'; 489 } 490 DBG_L1("%s\n", debug); 491 #endif 492 493 if ((s->regs.maincr & AACIFE) == 0) { 494 pl041_reset(s); 495 } 496 break; 497 } 498 499 case PL041_dr1_0: 500 case PL041_dr1_1: 501 case PL041_dr1_2: 502 case PL041_dr1_3: 503 pl041_fifo1_write(s, value); 504 break; 505 } 506 507 /* Transmit the FIFO content */ 508 pl041_fifo1_transmit(s); 509 510 /* Update the ISR1 register */ 511 pl041_isr1_update(s); 512 } 513 514 static void pl041_device_reset(DeviceState *d) 515 { 516 PL041State *s = PL041(d); 517 518 pl041_reset(s); 519 } 520 521 static const MemoryRegionOps pl041_ops = { 522 .read = pl041_read, 523 .write = pl041_write, 524 .endianness = DEVICE_NATIVE_ENDIAN, 525 }; 526 527 static void pl041_init(Object *obj) 528 { 529 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 530 PL041State *s = PL041(dev); 531 532 DBG_L1("pl041_init 0x%08x\n", (uint32_t)s); 533 534 /* Connect the device to the sysbus */ 535 memory_region_init_io(&s->iomem, obj, &pl041_ops, s, "pl041", 0x1000); 536 sysbus_init_mmio(dev, &s->iomem); 537 sysbus_init_irq(dev, &s->irq); 538 } 539 540 static void pl041_realize(DeviceState *dev, Error **errp) 541 { 542 PL041State *s = PL041(dev); 543 544 /* Check the device properties */ 545 switch (s->fifo_depth) { 546 case 8: 547 case 32: 548 case 64: 549 case 128: 550 case 256: 551 case 512: 552 case 1024: 553 case 2048: 554 break; 555 case 16: 556 default: 557 /* NC FIFO depth of 16 is not allowed because its id bits in 558 AACIPERIPHID3 overlap with the id for the default NC FIFO depth */ 559 qemu_log_mask(LOG_UNIMP, 560 "pl041: unsupported non-compact fifo depth [%i]\n", 561 s->fifo_depth); 562 } 563 564 /* Init the codec */ 565 lm4549_init(&s->codec, &pl041_request_data, (void *)s); 566 } 567 568 static const VMStateDescription vmstate_pl041_regfile = { 569 .name = "pl041_regfile", 570 .version_id = 1, 571 .minimum_version_id = 1, 572 .fields = (VMStateField[]) { 573 #define REGISTER(name, offset) VMSTATE_UINT32(name, pl041_regfile), 574 #include "pl041.hx" 575 #undef REGISTER 576 VMSTATE_END_OF_LIST() 577 } 578 }; 579 580 static const VMStateDescription vmstate_pl041_fifo = { 581 .name = "pl041_fifo", 582 .version_id = 1, 583 .minimum_version_id = 1, 584 .fields = (VMStateField[]) { 585 VMSTATE_UINT32(level, pl041_fifo), 586 VMSTATE_UINT32_ARRAY(data, pl041_fifo, MAX_FIFO_DEPTH), 587 VMSTATE_END_OF_LIST() 588 } 589 }; 590 591 static const VMStateDescription vmstate_pl041_channel = { 592 .name = "pl041_channel", 593 .version_id = 1, 594 .minimum_version_id = 1, 595 .fields = (VMStateField[]) { 596 VMSTATE_STRUCT(tx_fifo, pl041_channel, 0, 597 vmstate_pl041_fifo, pl041_fifo), 598 VMSTATE_UINT8(tx_enabled, pl041_channel), 599 VMSTATE_UINT8(tx_compact_mode, pl041_channel), 600 VMSTATE_UINT8(tx_sample_size, pl041_channel), 601 VMSTATE_STRUCT(rx_fifo, pl041_channel, 0, 602 vmstate_pl041_fifo, pl041_fifo), 603 VMSTATE_UINT8(rx_enabled, pl041_channel), 604 VMSTATE_UINT8(rx_compact_mode, pl041_channel), 605 VMSTATE_UINT8(rx_sample_size, pl041_channel), 606 VMSTATE_END_OF_LIST() 607 } 608 }; 609 610 static const VMStateDescription vmstate_pl041 = { 611 .name = "pl041", 612 .version_id = 1, 613 .minimum_version_id = 1, 614 .fields = (VMStateField[]) { 615 VMSTATE_UINT32(fifo_depth, PL041State), 616 VMSTATE_STRUCT(regs, PL041State, 0, 617 vmstate_pl041_regfile, pl041_regfile), 618 VMSTATE_STRUCT(fifo1, PL041State, 0, 619 vmstate_pl041_channel, pl041_channel), 620 VMSTATE_STRUCT(codec, PL041State, 0, 621 vmstate_lm4549_state, lm4549_state), 622 VMSTATE_END_OF_LIST() 623 } 624 }; 625 626 static Property pl041_device_properties[] = { 627 /* Non-compact FIFO depth property */ 628 DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth, 629 DEFAULT_FIFO_DEPTH), 630 DEFINE_PROP_END_OF_LIST(), 631 }; 632 633 static void pl041_device_class_init(ObjectClass *klass, void *data) 634 { 635 DeviceClass *dc = DEVICE_CLASS(klass); 636 637 dc->realize = pl041_realize; 638 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 639 dc->reset = pl041_device_reset; 640 dc->vmsd = &vmstate_pl041; 641 dc->props = pl041_device_properties; 642 } 643 644 static const TypeInfo pl041_device_info = { 645 .name = TYPE_PL041, 646 .parent = TYPE_SYS_BUS_DEVICE, 647 .instance_size = sizeof(PL041State), 648 .instance_init = pl041_init, 649 .class_init = pl041_device_class_init, 650 }; 651 652 static void pl041_register_types(void) 653 { 654 type_register_static(&pl041_device_info); 655 } 656 657 type_init(pl041_register_types) 658