1 /* 2 * Arm PrimeCell PL041 Advanced Audio Codec Interface 3 * 4 * Copyright (c) 2011 5 * Written by Mathieu Sonet - www.elasticsheep.com 6 * 7 * This code is licensed under the GPL. 8 * 9 * ***************************************************************** 10 * 11 * This driver emulates the ARM AACI interface 12 * connected to a LM4549 codec. 13 * 14 * Limitations: 15 * - Supports only a playback on one channel (Versatile/Vexpress) 16 * - Supports only one TX FIFO in compact-mode or non-compact mode. 17 * - Supports playback of 12, 16, 18 and 20 bits samples. 18 * - Record is not supported. 19 * - The PL041 is hardwired to a LM4549 codec. 20 * 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/irq.h" 25 #include "hw/sysbus.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 29 #include "pl041.h" 30 #include "lm4549.h" 31 32 #if 0 33 #define PL041_DEBUG_LEVEL 1 34 #endif 35 36 #if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 1) 37 #define DBG_L1(fmt, ...) \ 38 do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0) 39 #else 40 #define DBG_L1(fmt, ...) \ 41 do { } while (0) 42 #endif 43 44 #if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 2) 45 #define DBG_L2(fmt, ...) \ 46 do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0) 47 #else 48 #define DBG_L2(fmt, ...) \ 49 do { } while (0) 50 #endif 51 52 53 #define MAX_FIFO_DEPTH (1024) 54 #define DEFAULT_FIFO_DEPTH (8) 55 56 #define SLOT1_RW (1 << 19) 57 58 /* This FIFO only stores 20-bit samples on 32-bit words. 59 So its level is independent of the selected mode */ 60 typedef struct { 61 uint32_t level; 62 uint32_t data[MAX_FIFO_DEPTH]; 63 } pl041_fifo; 64 65 typedef struct { 66 pl041_fifo tx_fifo; 67 uint8_t tx_enabled; 68 uint8_t tx_compact_mode; 69 uint8_t tx_sample_size; 70 71 pl041_fifo rx_fifo; 72 uint8_t rx_enabled; 73 uint8_t rx_compact_mode; 74 uint8_t rx_sample_size; 75 } pl041_channel; 76 77 #define TYPE_PL041 "pl041" 78 #define PL041(obj) OBJECT_CHECK(PL041State, (obj), TYPE_PL041) 79 80 typedef struct PL041State { 81 SysBusDevice parent_obj; 82 83 MemoryRegion iomem; 84 qemu_irq irq; 85 86 uint32_t fifo_depth; /* FIFO depth in non-compact mode */ 87 88 pl041_regfile regs; 89 pl041_channel fifo1; 90 lm4549_state codec; 91 } PL041State; 92 93 94 static const unsigned char pl041_default_id[8] = { 95 0x41, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 96 }; 97 98 #if defined(PL041_DEBUG_LEVEL) 99 #define REGISTER(name, offset) #name, 100 static const char *pl041_regs_name[] = { 101 #include "pl041.hx" 102 }; 103 #undef REGISTER 104 #endif 105 106 107 #if defined(PL041_DEBUG_LEVEL) 108 static const char *get_reg_name(hwaddr offset) 109 { 110 if (offset <= PL041_dr1_7) { 111 return pl041_regs_name[offset >> 2]; 112 } 113 114 return "unknown"; 115 } 116 #endif 117 118 static uint8_t pl041_compute_periphid3(PL041State *s) 119 { 120 uint8_t id3 = 1; /* One channel */ 121 122 /* Add the fifo depth information */ 123 switch (s->fifo_depth) { 124 case 8: 125 id3 |= 0 << 3; 126 break; 127 case 32: 128 id3 |= 1 << 3; 129 break; 130 case 64: 131 id3 |= 2 << 3; 132 break; 133 case 128: 134 id3 |= 3 << 3; 135 break; 136 case 256: 137 id3 |= 4 << 3; 138 break; 139 case 512: 140 id3 |= 5 << 3; 141 break; 142 case 1024: 143 id3 |= 6 << 3; 144 break; 145 case 2048: 146 id3 |= 7 << 3; 147 break; 148 } 149 150 return id3; 151 } 152 153 static void pl041_reset(PL041State *s) 154 { 155 DBG_L1("pl041_reset\n"); 156 157 memset(&s->regs, 0x00, sizeof(pl041_regfile)); 158 159 s->regs.slfr = SL1TXEMPTY | SL2TXEMPTY | SL12TXEMPTY; 160 s->regs.sr1 = TXFE | RXFE | TXHE; 161 s->regs.isr1 = 0; 162 163 memset(&s->fifo1, 0x00, sizeof(s->fifo1)); 164 } 165 166 167 static void pl041_fifo1_write(PL041State *s, uint32_t value) 168 { 169 pl041_channel *channel = &s->fifo1; 170 pl041_fifo *fifo = &s->fifo1.tx_fifo; 171 172 /* Push the value in the FIFO */ 173 if (channel->tx_compact_mode == 0) { 174 /* Non-compact mode */ 175 176 if (fifo->level < s->fifo_depth) { 177 /* Pad the value with 0 to obtain a 20-bit sample */ 178 switch (channel->tx_sample_size) { 179 case 12: 180 value = (value << 8) & 0xFFFFF; 181 break; 182 case 16: 183 value = (value << 4) & 0xFFFFF; 184 break; 185 case 18: 186 value = (value << 2) & 0xFFFFF; 187 break; 188 case 20: 189 default: 190 break; 191 } 192 193 /* Store the sample in the FIFO */ 194 fifo->data[fifo->level++] = value; 195 } 196 #if defined(PL041_DEBUG_LEVEL) 197 else { 198 DBG_L1("fifo1 write: overrun\n"); 199 } 200 #endif 201 } else { 202 /* Compact mode */ 203 204 if ((fifo->level + 2) < s->fifo_depth) { 205 uint32_t i = 0; 206 uint32_t sample = 0; 207 208 for (i = 0; i < 2; i++) { 209 sample = value & 0xFFFF; 210 value = value >> 16; 211 212 /* Pad each sample with 0 to obtain a 20-bit sample */ 213 switch (channel->tx_sample_size) { 214 case 12: 215 sample = sample << 8; 216 break; 217 case 16: 218 default: 219 sample = sample << 4; 220 break; 221 } 222 223 /* Store the sample in the FIFO */ 224 fifo->data[fifo->level++] = sample; 225 } 226 } 227 #if defined(PL041_DEBUG_LEVEL) 228 else { 229 DBG_L1("fifo1 write: overrun\n"); 230 } 231 #endif 232 } 233 234 /* Update the status register */ 235 if (fifo->level > 0) { 236 s->regs.sr1 &= ~(TXUNDERRUN | TXFE); 237 } 238 239 if (fifo->level >= (s->fifo_depth / 2)) { 240 s->regs.sr1 &= ~TXHE; 241 } 242 243 if (fifo->level >= s->fifo_depth) { 244 s->regs.sr1 |= TXFF; 245 } 246 247 DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1); 248 } 249 250 static void pl041_fifo1_transmit(PL041State *s) 251 { 252 pl041_channel *channel = &s->fifo1; 253 pl041_fifo *fifo = &s->fifo1.tx_fifo; 254 uint32_t slots = s->regs.txcr1 & TXSLOT_MASK; 255 uint32_t written_samples; 256 257 /* Check if FIFO1 transmit is enabled */ 258 if ((channel->tx_enabled) && (slots & (TXSLOT3 | TXSLOT4))) { 259 if (fifo->level >= (s->fifo_depth / 2)) { 260 int i; 261 262 DBG_L1("Transfer FIFO level = %i\n", fifo->level); 263 264 /* Try to transfer the whole FIFO */ 265 for (i = 0; i < (fifo->level / 2); i++) { 266 uint32_t left = fifo->data[i * 2]; 267 uint32_t right = fifo->data[i * 2 + 1]; 268 269 /* Transmit two 20-bit samples to the codec */ 270 if (lm4549_write_samples(&s->codec, left, right) == 0) { 271 DBG_L1("Codec buffer full\n"); 272 break; 273 } 274 } 275 276 written_samples = i * 2; 277 if (written_samples > 0) { 278 /* Update the FIFO level */ 279 fifo->level -= written_samples; 280 281 /* Move back the pending samples to the start of the FIFO */ 282 for (i = 0; i < fifo->level; i++) { 283 fifo->data[i] = fifo->data[written_samples + i]; 284 } 285 286 /* Update the status register */ 287 s->regs.sr1 &= ~TXFF; 288 289 if (fifo->level <= (s->fifo_depth / 2)) { 290 s->regs.sr1 |= TXHE; 291 } 292 293 if (fifo->level == 0) { 294 s->regs.sr1 |= TXFE | TXUNDERRUN; 295 DBG_L1("Empty FIFO\n"); 296 } 297 } 298 } 299 } 300 } 301 302 static void pl041_isr1_update(PL041State *s) 303 { 304 /* Update ISR1 */ 305 if (s->regs.sr1 & TXUNDERRUN) { 306 s->regs.isr1 |= URINTR; 307 } else { 308 s->regs.isr1 &= ~URINTR; 309 } 310 311 if (s->regs.sr1 & TXHE) { 312 s->regs.isr1 |= TXINTR; 313 } else { 314 s->regs.isr1 &= ~TXINTR; 315 } 316 317 if (!(s->regs.sr1 & TXBUSY) && (s->regs.sr1 & TXFE)) { 318 s->regs.isr1 |= TXCINTR; 319 } else { 320 s->regs.isr1 &= ~TXCINTR; 321 } 322 323 /* Update the irq state */ 324 qemu_set_irq(s->irq, ((s->regs.isr1 & s->regs.ie1) > 0) ? 1 : 0); 325 DBG_L2("Set interrupt sr1 = 0x%08x isr1 = 0x%08x masked = 0x%08x\n", 326 s->regs.sr1, s->regs.isr1, s->regs.isr1 & s->regs.ie1); 327 } 328 329 static void pl041_request_data(void *opaque) 330 { 331 PL041State *s = (PL041State *)opaque; 332 333 /* Trigger pending transfers */ 334 pl041_fifo1_transmit(s); 335 pl041_isr1_update(s); 336 } 337 338 static uint64_t pl041_read(void *opaque, hwaddr offset, 339 unsigned size) 340 { 341 PL041State *s = (PL041State *)opaque; 342 int value; 343 344 if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) { 345 if (offset == PL041_periphid3) { 346 value = pl041_compute_periphid3(s); 347 } else { 348 value = pl041_default_id[(offset - PL041_periphid0) >> 2]; 349 } 350 351 DBG_L1("pl041_read [0x%08x] => 0x%08x\n", offset, value); 352 return value; 353 } else if (offset <= PL041_dr4_7) { 354 value = *((uint32_t *)&s->regs + (offset >> 2)); 355 } else { 356 DBG_L1("pl041_read: Reserved offset %x\n", (int)offset); 357 return 0; 358 } 359 360 switch (offset) { 361 case PL041_allints: 362 value = s->regs.isr1 & 0x7F; 363 break; 364 } 365 366 DBG_L1("pl041_read [0x%08x] %s => 0x%08x\n", offset, 367 get_reg_name(offset), value); 368 369 return value; 370 } 371 372 static void pl041_write(void *opaque, hwaddr offset, 373 uint64_t value, unsigned size) 374 { 375 PL041State *s = (PL041State *)opaque; 376 uint16_t control, data; 377 uint32_t result; 378 379 DBG_L1("pl041_write [0x%08x] %s <= 0x%08x\n", offset, 380 get_reg_name(offset), (unsigned int)value); 381 382 /* Write the register */ 383 if (offset <= PL041_dr4_7) { 384 *((uint32_t *)&s->regs + (offset >> 2)) = value; 385 } else { 386 DBG_L1("pl041_write: Reserved offset %x\n", (int)offset); 387 return; 388 } 389 390 /* Execute the actions */ 391 switch (offset) { 392 case PL041_txcr1: 393 { 394 pl041_channel *channel = &s->fifo1; 395 396 uint32_t txen = s->regs.txcr1 & TXEN; 397 uint32_t tsize = (s->regs.txcr1 & TSIZE_MASK) >> TSIZE_MASK_BIT; 398 uint32_t compact_mode = (s->regs.txcr1 & TXCOMPACT) ? 1 : 0; 399 #if defined(PL041_DEBUG_LEVEL) 400 uint32_t slots = (s->regs.txcr1 & TXSLOT_MASK) >> TXSLOT_MASK_BIT; 401 uint32_t txfen = (s->regs.txcr1 & TXFEN) > 0 ? 1 : 0; 402 #endif 403 404 DBG_L1("=> txen = %i slots = 0x%01x tsize = %i compact = %i " 405 "txfen = %i\n", txen, slots, tsize, compact_mode, txfen); 406 407 channel->tx_enabled = txen; 408 channel->tx_compact_mode = compact_mode; 409 410 switch (tsize) { 411 case 0: 412 channel->tx_sample_size = 16; 413 break; 414 case 1: 415 channel->tx_sample_size = 18; 416 break; 417 case 2: 418 channel->tx_sample_size = 20; 419 break; 420 case 3: 421 channel->tx_sample_size = 12; 422 break; 423 } 424 425 DBG_L1("TX enabled = %i\n", channel->tx_enabled); 426 DBG_L1("TX compact mode = %i\n", channel->tx_compact_mode); 427 DBG_L1("TX sample width = %i\n", channel->tx_sample_size); 428 429 /* Check if compact mode is allowed with selected tsize */ 430 if (channel->tx_compact_mode == 1) { 431 if ((channel->tx_sample_size == 18) || 432 (channel->tx_sample_size == 20)) { 433 channel->tx_compact_mode = 0; 434 DBG_L1("Compact mode not allowed with 18/20-bit sample size\n"); 435 } 436 } 437 438 break; 439 } 440 case PL041_sl1tx: 441 s->regs.slfr &= ~SL1TXEMPTY; 442 443 control = (s->regs.sl1tx >> 12) & 0x7F; 444 data = (s->regs.sl2tx >> 4) & 0xFFFF; 445 446 if ((s->regs.sl1tx & SLOT1_RW) == 0) { 447 /* Write operation */ 448 lm4549_write(&s->codec, control, data); 449 } else { 450 /* Read operation */ 451 result = lm4549_read(&s->codec, control); 452 453 /* Store the returned value */ 454 s->regs.sl1rx = s->regs.sl1tx & ~SLOT1_RW; 455 s->regs.sl2rx = result << 4; 456 457 s->regs.slfr &= ~(SL1RXBUSY | SL2RXBUSY); 458 s->regs.slfr |= SL1RXVALID | SL2RXVALID; 459 } 460 break; 461 462 case PL041_sl2tx: 463 s->regs.sl2tx = value; 464 s->regs.slfr &= ~SL2TXEMPTY; 465 break; 466 467 case PL041_intclr: 468 DBG_L1("=> Clear interrupt intclr = 0x%08x isr1 = 0x%08x\n", 469 s->regs.intclr, s->regs.isr1); 470 471 if (s->regs.intclr & TXUEC1) { 472 s->regs.sr1 &= ~TXUNDERRUN; 473 } 474 break; 475 476 case PL041_maincr: 477 { 478 #if defined(PL041_DEBUG_LEVEL) 479 char debug[] = " AACIFE SL1RXEN SL1TXEN"; 480 if (!(value & AACIFE)) { 481 debug[0] = '!'; 482 } 483 if (!(value & SL1RXEN)) { 484 debug[8] = '!'; 485 } 486 if (!(value & SL1TXEN)) { 487 debug[17] = '!'; 488 } 489 DBG_L1("%s\n", debug); 490 #endif 491 492 if ((s->regs.maincr & AACIFE) == 0) { 493 pl041_reset(s); 494 } 495 break; 496 } 497 498 case PL041_dr1_0: 499 case PL041_dr1_1: 500 case PL041_dr1_2: 501 case PL041_dr1_3: 502 pl041_fifo1_write(s, value); 503 break; 504 } 505 506 /* Transmit the FIFO content */ 507 pl041_fifo1_transmit(s); 508 509 /* Update the ISR1 register */ 510 pl041_isr1_update(s); 511 } 512 513 static void pl041_device_reset(DeviceState *d) 514 { 515 PL041State *s = PL041(d); 516 517 pl041_reset(s); 518 } 519 520 static const MemoryRegionOps pl041_ops = { 521 .read = pl041_read, 522 .write = pl041_write, 523 .endianness = DEVICE_NATIVE_ENDIAN, 524 }; 525 526 static void pl041_init(Object *obj) 527 { 528 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 529 PL041State *s = PL041(dev); 530 531 DBG_L1("pl041_init 0x%08x\n", (uint32_t)s); 532 533 /* Connect the device to the sysbus */ 534 memory_region_init_io(&s->iomem, obj, &pl041_ops, s, "pl041", 0x1000); 535 sysbus_init_mmio(dev, &s->iomem); 536 sysbus_init_irq(dev, &s->irq); 537 } 538 539 static void pl041_realize(DeviceState *dev, Error **errp) 540 { 541 PL041State *s = PL041(dev); 542 543 /* Check the device properties */ 544 switch (s->fifo_depth) { 545 case 8: 546 case 32: 547 case 64: 548 case 128: 549 case 256: 550 case 512: 551 case 1024: 552 case 2048: 553 break; 554 case 16: 555 default: 556 /* NC FIFO depth of 16 is not allowed because its id bits in 557 AACIPERIPHID3 overlap with the id for the default NC FIFO depth */ 558 qemu_log_mask(LOG_UNIMP, 559 "pl041: unsupported non-compact fifo depth [%i]\n", 560 s->fifo_depth); 561 } 562 563 /* Init the codec */ 564 lm4549_init(&s->codec, &pl041_request_data, (void *)s); 565 } 566 567 static const VMStateDescription vmstate_pl041_regfile = { 568 .name = "pl041_regfile", 569 .version_id = 1, 570 .minimum_version_id = 1, 571 .fields = (VMStateField[]) { 572 #define REGISTER(name, offset) VMSTATE_UINT32(name, pl041_regfile), 573 #include "pl041.hx" 574 #undef REGISTER 575 VMSTATE_END_OF_LIST() 576 } 577 }; 578 579 static const VMStateDescription vmstate_pl041_fifo = { 580 .name = "pl041_fifo", 581 .version_id = 1, 582 .minimum_version_id = 1, 583 .fields = (VMStateField[]) { 584 VMSTATE_UINT32(level, pl041_fifo), 585 VMSTATE_UINT32_ARRAY(data, pl041_fifo, MAX_FIFO_DEPTH), 586 VMSTATE_END_OF_LIST() 587 } 588 }; 589 590 static const VMStateDescription vmstate_pl041_channel = { 591 .name = "pl041_channel", 592 .version_id = 1, 593 .minimum_version_id = 1, 594 .fields = (VMStateField[]) { 595 VMSTATE_STRUCT(tx_fifo, pl041_channel, 0, 596 vmstate_pl041_fifo, pl041_fifo), 597 VMSTATE_UINT8(tx_enabled, pl041_channel), 598 VMSTATE_UINT8(tx_compact_mode, pl041_channel), 599 VMSTATE_UINT8(tx_sample_size, pl041_channel), 600 VMSTATE_STRUCT(rx_fifo, pl041_channel, 0, 601 vmstate_pl041_fifo, pl041_fifo), 602 VMSTATE_UINT8(rx_enabled, pl041_channel), 603 VMSTATE_UINT8(rx_compact_mode, pl041_channel), 604 VMSTATE_UINT8(rx_sample_size, pl041_channel), 605 VMSTATE_END_OF_LIST() 606 } 607 }; 608 609 static const VMStateDescription vmstate_pl041 = { 610 .name = "pl041", 611 .version_id = 1, 612 .minimum_version_id = 1, 613 .fields = (VMStateField[]) { 614 VMSTATE_UINT32(fifo_depth, PL041State), 615 VMSTATE_STRUCT(regs, PL041State, 0, 616 vmstate_pl041_regfile, pl041_regfile), 617 VMSTATE_STRUCT(fifo1, PL041State, 0, 618 vmstate_pl041_channel, pl041_channel), 619 VMSTATE_STRUCT(codec, PL041State, 0, 620 vmstate_lm4549_state, lm4549_state), 621 VMSTATE_END_OF_LIST() 622 } 623 }; 624 625 static Property pl041_device_properties[] = { 626 /* Non-compact FIFO depth property */ 627 DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth, 628 DEFAULT_FIFO_DEPTH), 629 DEFINE_PROP_END_OF_LIST(), 630 }; 631 632 static void pl041_device_class_init(ObjectClass *klass, void *data) 633 { 634 DeviceClass *dc = DEVICE_CLASS(klass); 635 636 dc->realize = pl041_realize; 637 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 638 dc->reset = pl041_device_reset; 639 dc->vmsd = &vmstate_pl041; 640 dc->props = pl041_device_properties; 641 } 642 643 static const TypeInfo pl041_device_info = { 644 .name = TYPE_PL041, 645 .parent = TYPE_SYS_BUS_DEVICE, 646 .instance_size = sizeof(PL041State), 647 .instance_init = pl041_init, 648 .class_init = pl041_device_class_init, 649 }; 650 651 static void pl041_register_types(void) 652 { 653 type_register_static(&pl041_device_info); 654 } 655 656 type_init(pl041_register_types) 657