1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Gerd Hoffmann <kraxel@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/pci/pci.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/pci/msi.h" 24 #include "qemu/timer.h" 25 #include "qemu/bitops.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "hw/audio/soundhw.h" 29 #include "intel-hda.h" 30 #include "migration/vmstate.h" 31 #include "intel-hda-defs.h" 32 #include "sysemu/dma.h" 33 #include "qapi/error.h" 34 35 /* --------------------------------------------------------------------- */ 36 /* hda bus */ 37 38 static Property hda_props[] = { 39 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), 40 DEFINE_PROP_END_OF_LIST() 41 }; 42 43 static const TypeInfo hda_codec_bus_info = { 44 .name = TYPE_HDA_BUS, 45 .parent = TYPE_BUS, 46 .instance_size = sizeof(HDACodecBus), 47 }; 48 49 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, 50 hda_codec_response_func response, 51 hda_codec_xfer_func xfer) 52 { 53 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL); 54 bus->response = response; 55 bus->xfer = xfer; 56 } 57 58 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp) 59 { 60 HDACodecBus *bus = HDA_BUS(qdev->parent_bus); 61 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 62 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 63 64 if (dev->cad == -1) { 65 dev->cad = bus->next_cad; 66 } 67 if (dev->cad >= 15) { 68 error_setg(errp, "HDA audio codec address is full"); 69 return; 70 } 71 bus->next_cad = dev->cad + 1; 72 if (cdc->init(dev) != 0) { 73 error_setg(errp, "HDA audio init failed"); 74 } 75 } 76 77 static void hda_codec_dev_unrealize(DeviceState *qdev, Error **errp) 78 { 79 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 80 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 81 82 if (cdc->exit) { 83 cdc->exit(dev); 84 } 85 } 86 87 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) 88 { 89 BusChild *kid; 90 HDACodecDevice *cdev; 91 92 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { 93 DeviceState *qdev = kid->child; 94 cdev = HDA_CODEC_DEVICE(qdev); 95 if (cdev->cad == cad) { 96 return cdev; 97 } 98 } 99 return NULL; 100 } 101 102 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) 103 { 104 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 105 bus->response(dev, solicited, response); 106 } 107 108 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 109 uint8_t *buf, uint32_t len) 110 { 111 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 112 return bus->xfer(dev, stnr, output, buf, len); 113 } 114 115 /* --------------------------------------------------------------------- */ 116 /* intel hda emulation */ 117 118 typedef struct IntelHDAStream IntelHDAStream; 119 typedef struct IntelHDAState IntelHDAState; 120 typedef struct IntelHDAReg IntelHDAReg; 121 122 typedef struct bpl { 123 uint64_t addr; 124 uint32_t len; 125 uint32_t flags; 126 } bpl; 127 128 struct IntelHDAStream { 129 /* registers */ 130 uint32_t ctl; 131 uint32_t lpib; 132 uint32_t cbl; 133 uint32_t lvi; 134 uint32_t fmt; 135 uint32_t bdlp_lbase; 136 uint32_t bdlp_ubase; 137 138 /* state */ 139 bpl *bpl; 140 uint32_t bentries; 141 uint32_t bsize, be, bp; 142 }; 143 144 struct IntelHDAState { 145 PCIDevice pci; 146 const char *name; 147 HDACodecBus codecs; 148 149 /* registers */ 150 uint32_t g_ctl; 151 uint32_t wake_en; 152 uint32_t state_sts; 153 uint32_t int_ctl; 154 uint32_t int_sts; 155 uint32_t wall_clk; 156 157 uint32_t corb_lbase; 158 uint32_t corb_ubase; 159 uint32_t corb_rp; 160 uint32_t corb_wp; 161 uint32_t corb_ctl; 162 uint32_t corb_sts; 163 uint32_t corb_size; 164 165 uint32_t rirb_lbase; 166 uint32_t rirb_ubase; 167 uint32_t rirb_wp; 168 uint32_t rirb_cnt; 169 uint32_t rirb_ctl; 170 uint32_t rirb_sts; 171 uint32_t rirb_size; 172 173 uint32_t dp_lbase; 174 uint32_t dp_ubase; 175 176 uint32_t icw; 177 uint32_t irr; 178 uint32_t ics; 179 180 /* streams */ 181 IntelHDAStream st[8]; 182 183 /* state */ 184 MemoryRegion container; 185 MemoryRegion mmio; 186 MemoryRegion alias; 187 uint32_t rirb_count; 188 int64_t wall_base_ns; 189 190 /* debug logging */ 191 const IntelHDAReg *last_reg; 192 uint32_t last_val; 193 uint32_t last_write; 194 uint32_t last_sec; 195 uint32_t repeat_count; 196 197 /* properties */ 198 uint32_t debug; 199 OnOffAuto msi; 200 bool old_msi_addr; 201 }; 202 203 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic" 204 205 #define INTEL_HDA(obj) \ 206 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC) 207 208 struct IntelHDAReg { 209 const char *name; /* register name */ 210 uint32_t size; /* size in bytes */ 211 uint32_t reset; /* reset value */ 212 uint32_t wmask; /* write mask */ 213 uint32_t wclear; /* write 1 to clear bits */ 214 uint32_t offset; /* location in IntelHDAState */ 215 uint32_t shift; /* byte access entries for dwords */ 216 uint32_t stream; 217 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); 218 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); 219 }; 220 221 static void intel_hda_reset(DeviceState *dev); 222 223 /* --------------------------------------------------------------------- */ 224 225 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) 226 { 227 return ((uint64_t)ubase << 32) | lbase; 228 } 229 230 static void intel_hda_update_int_sts(IntelHDAState *d) 231 { 232 uint32_t sts = 0; 233 uint32_t i; 234 235 /* update controller status */ 236 if (d->rirb_sts & ICH6_RBSTS_IRQ) { 237 sts |= (1 << 30); 238 } 239 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { 240 sts |= (1 << 30); 241 } 242 if (d->state_sts & d->wake_en) { 243 sts |= (1 << 30); 244 } 245 246 /* update stream status */ 247 for (i = 0; i < 8; i++) { 248 /* buffer completion interrupt */ 249 if (d->st[i].ctl & (1 << 26)) { 250 sts |= (1 << i); 251 } 252 } 253 254 /* update global status */ 255 if (sts & d->int_ctl) { 256 sts |= (1U << 31); 257 } 258 259 d->int_sts = sts; 260 } 261 262 static void intel_hda_update_irq(IntelHDAState *d) 263 { 264 bool msi = msi_enabled(&d->pci); 265 int level; 266 267 intel_hda_update_int_sts(d); 268 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { 269 level = 1; 270 } else { 271 level = 0; 272 } 273 dprint(d, 2, "%s: level %d [%s]\n", __func__, 274 level, msi ? "msi" : "intx"); 275 if (msi) { 276 if (level) { 277 msi_notify(&d->pci, 0); 278 } 279 } else { 280 pci_set_irq(&d->pci, level); 281 } 282 } 283 284 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) 285 { 286 uint32_t cad, nid, data; 287 HDACodecDevice *codec; 288 HDACodecDeviceClass *cdc; 289 290 cad = (verb >> 28) & 0x0f; 291 if (verb & (1 << 27)) { 292 /* indirect node addressing, not specified in HDA 1.0 */ 293 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__); 294 return -1; 295 } 296 nid = (verb >> 20) & 0x7f; 297 data = verb & 0xfffff; 298 299 codec = hda_codec_find(&d->codecs, cad); 300 if (codec == NULL) { 301 dprint(d, 1, "%s: addressed non-existing codec\n", __func__); 302 return -1; 303 } 304 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec); 305 cdc->command(codec, nid, data); 306 return 0; 307 } 308 309 static void intel_hda_corb_run(IntelHDAState *d) 310 { 311 hwaddr addr; 312 uint32_t rp, verb; 313 314 if (d->ics & ICH6_IRS_BUSY) { 315 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw); 316 intel_hda_send_command(d, d->icw); 317 return; 318 } 319 320 for (;;) { 321 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { 322 dprint(d, 2, "%s: !run\n", __func__); 323 return; 324 } 325 if ((d->corb_rp & 0xff) == d->corb_wp) { 326 dprint(d, 2, "%s: corb ring empty\n", __func__); 327 return; 328 } 329 if (d->rirb_count == d->rirb_cnt) { 330 dprint(d, 2, "%s: rirb count reached\n", __func__); 331 return; 332 } 333 334 rp = (d->corb_rp + 1) & 0xff; 335 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); 336 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp); 337 d->corb_rp = rp; 338 339 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); 340 intel_hda_send_command(d, verb); 341 } 342 } 343 344 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) 345 { 346 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 347 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 348 hwaddr addr; 349 uint32_t wp, ex; 350 351 if (d->ics & ICH6_IRS_BUSY) { 352 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", 353 __func__, response, dev->cad); 354 d->irr = response; 355 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); 356 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); 357 return; 358 } 359 360 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { 361 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__); 362 return; 363 } 364 365 ex = (solicited ? 0 : (1 << 4)) | dev->cad; 366 wp = (d->rirb_wp + 1) & 0xff; 367 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); 368 stl_le_pci_dma(&d->pci, addr + 8*wp, response); 369 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex); 370 d->rirb_wp = wp; 371 372 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", 373 __func__, wp, response, ex); 374 375 d->rirb_count++; 376 if (d->rirb_count == d->rirb_cnt) { 377 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count); 378 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 379 d->rirb_sts |= ICH6_RBSTS_IRQ; 380 intel_hda_update_irq(d); 381 } 382 } else if ((d->corb_rp & 0xff) == d->corb_wp) { 383 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__, 384 d->rirb_count, d->rirb_cnt); 385 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 386 d->rirb_sts |= ICH6_RBSTS_IRQ; 387 intel_hda_update_irq(d); 388 } 389 } 390 } 391 392 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 393 uint8_t *buf, uint32_t len) 394 { 395 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 396 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 397 hwaddr addr; 398 uint32_t s, copy, left; 399 IntelHDAStream *st; 400 bool irq = false; 401 402 st = output ? d->st + 4 : d->st; 403 for (s = 0; s < 4; s++) { 404 if (stnr == ((st[s].ctl >> 20) & 0x0f)) { 405 st = st + s; 406 break; 407 } 408 } 409 if (s == 4) { 410 return false; 411 } 412 if (st->bpl == NULL) { 413 return false; 414 } 415 416 left = len; 417 s = st->bentries; 418 while (left > 0 && s-- > 0) { 419 copy = left; 420 if (copy > st->bsize - st->lpib) 421 copy = st->bsize - st->lpib; 422 if (copy > st->bpl[st->be].len - st->bp) 423 copy = st->bpl[st->be].len - st->bp; 424 425 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", 426 st->be, st->bp, st->bpl[st->be].len, copy); 427 428 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output); 429 st->lpib += copy; 430 st->bp += copy; 431 buf += copy; 432 left -= copy; 433 434 if (st->bpl[st->be].len == st->bp) { 435 /* bpl entry filled */ 436 if (st->bpl[st->be].flags & 0x01) { 437 irq = true; 438 } 439 st->bp = 0; 440 st->be++; 441 if (st->be == st->bentries) { 442 /* bpl wrap around */ 443 st->be = 0; 444 st->lpib = 0; 445 } 446 } 447 } 448 if (d->dp_lbase & 0x01) { 449 s = st - d->st; 450 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); 451 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib); 452 } 453 dprint(d, 3, "dma: --\n"); 454 455 if (irq) { 456 st->ctl |= (1 << 26); /* buffer completion interrupt */ 457 intel_hda_update_irq(d); 458 } 459 return true; 460 } 461 462 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) 463 { 464 hwaddr addr; 465 uint8_t buf[16]; 466 uint32_t i; 467 468 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); 469 st->bentries = st->lvi +1; 470 g_free(st->bpl); 471 st->bpl = g_malloc(sizeof(bpl) * st->bentries); 472 for (i = 0; i < st->bentries; i++, addr += 16) { 473 pci_dma_read(&d->pci, addr, buf, 16); 474 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); 475 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); 476 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); 477 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", 478 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); 479 } 480 481 st->bsize = st->cbl; 482 st->lpib = 0; 483 st->be = 0; 484 st->bp = 0; 485 } 486 487 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) 488 { 489 BusChild *kid; 490 HDACodecDevice *cdev; 491 492 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 493 DeviceState *qdev = kid->child; 494 HDACodecDeviceClass *cdc; 495 496 cdev = HDA_CODEC_DEVICE(qdev); 497 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev); 498 if (cdc->stream) { 499 cdc->stream(cdev, stream, running, output); 500 } 501 } 502 } 503 504 /* --------------------------------------------------------------------- */ 505 506 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 507 { 508 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { 509 intel_hda_reset(DEVICE(d)); 510 } 511 } 512 513 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 514 { 515 intel_hda_update_irq(d); 516 } 517 518 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 519 { 520 intel_hda_update_irq(d); 521 } 522 523 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 524 { 525 intel_hda_update_irq(d); 526 } 527 528 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) 529 { 530 int64_t ns; 531 532 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; 533 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ 534 } 535 536 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 537 { 538 intel_hda_corb_run(d); 539 } 540 541 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 542 { 543 intel_hda_corb_run(d); 544 } 545 546 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 547 { 548 if (d->rirb_wp & ICH6_RIRBWP_RST) { 549 d->rirb_wp = 0; 550 } 551 } 552 553 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 554 { 555 intel_hda_update_irq(d); 556 557 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { 558 /* cleared ICH6_RBSTS_IRQ */ 559 d->rirb_count = 0; 560 intel_hda_corb_run(d); 561 } 562 } 563 564 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 565 { 566 if (d->ics & ICH6_IRS_BUSY) { 567 intel_hda_corb_run(d); 568 } 569 } 570 571 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 572 { 573 bool output = reg->stream >= 4; 574 IntelHDAStream *st = d->st + reg->stream; 575 576 if (st->ctl & 0x01) { 577 /* reset */ 578 dprint(d, 1, "st #%d: reset\n", reg->stream); 579 st->ctl = SD_STS_FIFO_READY << 24; 580 } 581 if ((st->ctl & 0x02) != (old & 0x02)) { 582 uint32_t stnr = (st->ctl >> 20) & 0x0f; 583 /* run bit flipped */ 584 if (st->ctl & 0x02) { 585 /* start */ 586 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", 587 reg->stream, stnr, st->cbl); 588 intel_hda_parse_bdl(d, st); 589 intel_hda_notify_codecs(d, stnr, true, output); 590 } else { 591 /* stop */ 592 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); 593 intel_hda_notify_codecs(d, stnr, false, output); 594 } 595 } 596 intel_hda_update_irq(d); 597 } 598 599 /* --------------------------------------------------------------------- */ 600 601 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) 602 603 static const struct IntelHDAReg regtab[] = { 604 /* global */ 605 [ ICH6_REG_GCAP ] = { 606 .name = "GCAP", 607 .size = 2, 608 .reset = 0x4401, 609 }, 610 [ ICH6_REG_VMIN ] = { 611 .name = "VMIN", 612 .size = 1, 613 }, 614 [ ICH6_REG_VMAJ ] = { 615 .name = "VMAJ", 616 .size = 1, 617 .reset = 1, 618 }, 619 [ ICH6_REG_OUTPAY ] = { 620 .name = "OUTPAY", 621 .size = 2, 622 .reset = 0x3c, 623 }, 624 [ ICH6_REG_INPAY ] = { 625 .name = "INPAY", 626 .size = 2, 627 .reset = 0x1d, 628 }, 629 [ ICH6_REG_GCTL ] = { 630 .name = "GCTL", 631 .size = 4, 632 .wmask = 0x0103, 633 .offset = offsetof(IntelHDAState, g_ctl), 634 .whandler = intel_hda_set_g_ctl, 635 }, 636 [ ICH6_REG_WAKEEN ] = { 637 .name = "WAKEEN", 638 .size = 2, 639 .wmask = 0x7fff, 640 .offset = offsetof(IntelHDAState, wake_en), 641 .whandler = intel_hda_set_wake_en, 642 }, 643 [ ICH6_REG_STATESTS ] = { 644 .name = "STATESTS", 645 .size = 2, 646 .wmask = 0x7fff, 647 .wclear = 0x7fff, 648 .offset = offsetof(IntelHDAState, state_sts), 649 .whandler = intel_hda_set_state_sts, 650 }, 651 652 /* interrupts */ 653 [ ICH6_REG_INTCTL ] = { 654 .name = "INTCTL", 655 .size = 4, 656 .wmask = 0xc00000ff, 657 .offset = offsetof(IntelHDAState, int_ctl), 658 .whandler = intel_hda_set_int_ctl, 659 }, 660 [ ICH6_REG_INTSTS ] = { 661 .name = "INTSTS", 662 .size = 4, 663 .wmask = 0xc00000ff, 664 .wclear = 0xc00000ff, 665 .offset = offsetof(IntelHDAState, int_sts), 666 }, 667 668 /* misc */ 669 [ ICH6_REG_WALLCLK ] = { 670 .name = "WALLCLK", 671 .size = 4, 672 .offset = offsetof(IntelHDAState, wall_clk), 673 .rhandler = intel_hda_get_wall_clk, 674 }, 675 676 /* dma engine */ 677 [ ICH6_REG_CORBLBASE ] = { 678 .name = "CORBLBASE", 679 .size = 4, 680 .wmask = 0xffffff80, 681 .offset = offsetof(IntelHDAState, corb_lbase), 682 }, 683 [ ICH6_REG_CORBUBASE ] = { 684 .name = "CORBUBASE", 685 .size = 4, 686 .wmask = 0xffffffff, 687 .offset = offsetof(IntelHDAState, corb_ubase), 688 }, 689 [ ICH6_REG_CORBWP ] = { 690 .name = "CORBWP", 691 .size = 2, 692 .wmask = 0xff, 693 .offset = offsetof(IntelHDAState, corb_wp), 694 .whandler = intel_hda_set_corb_wp, 695 }, 696 [ ICH6_REG_CORBRP ] = { 697 .name = "CORBRP", 698 .size = 2, 699 .wmask = 0x80ff, 700 .offset = offsetof(IntelHDAState, corb_rp), 701 }, 702 [ ICH6_REG_CORBCTL ] = { 703 .name = "CORBCTL", 704 .size = 1, 705 .wmask = 0x03, 706 .offset = offsetof(IntelHDAState, corb_ctl), 707 .whandler = intel_hda_set_corb_ctl, 708 }, 709 [ ICH6_REG_CORBSTS ] = { 710 .name = "CORBSTS", 711 .size = 1, 712 .wmask = 0x01, 713 .wclear = 0x01, 714 .offset = offsetof(IntelHDAState, corb_sts), 715 }, 716 [ ICH6_REG_CORBSIZE ] = { 717 .name = "CORBSIZE", 718 .size = 1, 719 .reset = 0x42, 720 .offset = offsetof(IntelHDAState, corb_size), 721 }, 722 [ ICH6_REG_RIRBLBASE ] = { 723 .name = "RIRBLBASE", 724 .size = 4, 725 .wmask = 0xffffff80, 726 .offset = offsetof(IntelHDAState, rirb_lbase), 727 }, 728 [ ICH6_REG_RIRBUBASE ] = { 729 .name = "RIRBUBASE", 730 .size = 4, 731 .wmask = 0xffffffff, 732 .offset = offsetof(IntelHDAState, rirb_ubase), 733 }, 734 [ ICH6_REG_RIRBWP ] = { 735 .name = "RIRBWP", 736 .size = 2, 737 .wmask = 0x8000, 738 .offset = offsetof(IntelHDAState, rirb_wp), 739 .whandler = intel_hda_set_rirb_wp, 740 }, 741 [ ICH6_REG_RINTCNT ] = { 742 .name = "RINTCNT", 743 .size = 2, 744 .wmask = 0xff, 745 .offset = offsetof(IntelHDAState, rirb_cnt), 746 }, 747 [ ICH6_REG_RIRBCTL ] = { 748 .name = "RIRBCTL", 749 .size = 1, 750 .wmask = 0x07, 751 .offset = offsetof(IntelHDAState, rirb_ctl), 752 }, 753 [ ICH6_REG_RIRBSTS ] = { 754 .name = "RIRBSTS", 755 .size = 1, 756 .wmask = 0x05, 757 .wclear = 0x05, 758 .offset = offsetof(IntelHDAState, rirb_sts), 759 .whandler = intel_hda_set_rirb_sts, 760 }, 761 [ ICH6_REG_RIRBSIZE ] = { 762 .name = "RIRBSIZE", 763 .size = 1, 764 .reset = 0x42, 765 .offset = offsetof(IntelHDAState, rirb_size), 766 }, 767 768 [ ICH6_REG_DPLBASE ] = { 769 .name = "DPLBASE", 770 .size = 4, 771 .wmask = 0xffffff81, 772 .offset = offsetof(IntelHDAState, dp_lbase), 773 }, 774 [ ICH6_REG_DPUBASE ] = { 775 .name = "DPUBASE", 776 .size = 4, 777 .wmask = 0xffffffff, 778 .offset = offsetof(IntelHDAState, dp_ubase), 779 }, 780 781 [ ICH6_REG_IC ] = { 782 .name = "ICW", 783 .size = 4, 784 .wmask = 0xffffffff, 785 .offset = offsetof(IntelHDAState, icw), 786 }, 787 [ ICH6_REG_IR ] = { 788 .name = "IRR", 789 .size = 4, 790 .offset = offsetof(IntelHDAState, irr), 791 }, 792 [ ICH6_REG_IRS ] = { 793 .name = "ICS", 794 .size = 2, 795 .wmask = 0x0003, 796 .wclear = 0x0002, 797 .offset = offsetof(IntelHDAState, ics), 798 .whandler = intel_hda_set_ics, 799 }, 800 801 #define HDA_STREAM(_t, _i) \ 802 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ 803 .stream = _i, \ 804 .name = _t stringify(_i) " CTL", \ 805 .size = 4, \ 806 .wmask = 0x1cff001f, \ 807 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 808 .whandler = intel_hda_set_st_ctl, \ 809 }, \ 810 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ 811 .stream = _i, \ 812 .name = _t stringify(_i) " CTL(stnr)", \ 813 .size = 1, \ 814 .shift = 16, \ 815 .wmask = 0x00ff0000, \ 816 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 817 .whandler = intel_hda_set_st_ctl, \ 818 }, \ 819 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ 820 .stream = _i, \ 821 .name = _t stringify(_i) " CTL(sts)", \ 822 .size = 1, \ 823 .shift = 24, \ 824 .wmask = 0x1c000000, \ 825 .wclear = 0x1c000000, \ 826 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 827 .whandler = intel_hda_set_st_ctl, \ 828 .reset = SD_STS_FIFO_READY << 24 \ 829 }, \ 830 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ 831 .stream = _i, \ 832 .name = _t stringify(_i) " LPIB", \ 833 .size = 4, \ 834 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 835 }, \ 836 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ 837 .stream = _i, \ 838 .name = _t stringify(_i) " CBL", \ 839 .size = 4, \ 840 .wmask = 0xffffffff, \ 841 .offset = offsetof(IntelHDAState, st[_i].cbl), \ 842 }, \ 843 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ 844 .stream = _i, \ 845 .name = _t stringify(_i) " LVI", \ 846 .size = 2, \ 847 .wmask = 0x00ff, \ 848 .offset = offsetof(IntelHDAState, st[_i].lvi), \ 849 }, \ 850 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ 851 .stream = _i, \ 852 .name = _t stringify(_i) " FIFOS", \ 853 .size = 2, \ 854 .reset = HDA_BUFFER_SIZE, \ 855 }, \ 856 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ 857 .stream = _i, \ 858 .name = _t stringify(_i) " FMT", \ 859 .size = 2, \ 860 .wmask = 0x7f7f, \ 861 .offset = offsetof(IntelHDAState, st[_i].fmt), \ 862 }, \ 863 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ 864 .stream = _i, \ 865 .name = _t stringify(_i) " BDLPL", \ 866 .size = 4, \ 867 .wmask = 0xffffff80, \ 868 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ 869 }, \ 870 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ 871 .stream = _i, \ 872 .name = _t stringify(_i) " BDLPU", \ 873 .size = 4, \ 874 .wmask = 0xffffffff, \ 875 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ 876 }, \ 877 878 HDA_STREAM("IN", 0) 879 HDA_STREAM("IN", 1) 880 HDA_STREAM("IN", 2) 881 HDA_STREAM("IN", 3) 882 883 HDA_STREAM("OUT", 4) 884 HDA_STREAM("OUT", 5) 885 HDA_STREAM("OUT", 6) 886 HDA_STREAM("OUT", 7) 887 888 }; 889 890 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) 891 { 892 const IntelHDAReg *reg; 893 894 if (addr >= ARRAY_SIZE(regtab)) { 895 goto noreg; 896 } 897 reg = regtab+addr; 898 if (reg->name == NULL) { 899 goto noreg; 900 } 901 return reg; 902 903 noreg: 904 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); 905 return NULL; 906 } 907 908 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) 909 { 910 uint8_t *addr = (void*)d; 911 912 addr += reg->offset; 913 return (uint32_t*)addr; 914 } 915 916 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, 917 uint32_t wmask) 918 { 919 uint32_t *addr; 920 uint32_t old; 921 922 if (!reg) { 923 return; 924 } 925 if (!reg->wmask) { 926 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n", 927 reg->name); 928 return; 929 } 930 931 if (d->debug) { 932 time_t now = time(NULL); 933 if (d->last_write && d->last_reg == reg && d->last_val == val) { 934 d->repeat_count++; 935 if (d->last_sec != now) { 936 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 937 d->last_sec = now; 938 d->repeat_count = 0; 939 } 940 } else { 941 if (d->repeat_count) { 942 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 943 } 944 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); 945 d->last_write = 1; 946 d->last_reg = reg; 947 d->last_val = val; 948 d->last_sec = now; 949 d->repeat_count = 0; 950 } 951 } 952 assert(reg->offset != 0); 953 954 addr = intel_hda_reg_addr(d, reg); 955 old = *addr; 956 957 if (reg->shift) { 958 val <<= reg->shift; 959 wmask <<= reg->shift; 960 } 961 wmask &= reg->wmask; 962 *addr &= ~wmask; 963 *addr |= wmask & val; 964 *addr &= ~(val & reg->wclear); 965 966 if (reg->whandler) { 967 reg->whandler(d, reg, old); 968 } 969 } 970 971 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, 972 uint32_t rmask) 973 { 974 uint32_t *addr, ret; 975 976 if (!reg) { 977 return 0; 978 } 979 980 if (reg->rhandler) { 981 reg->rhandler(d, reg); 982 } 983 984 if (reg->offset == 0) { 985 /* constant read-only register */ 986 ret = reg->reset; 987 } else { 988 addr = intel_hda_reg_addr(d, reg); 989 ret = *addr; 990 if (reg->shift) { 991 ret >>= reg->shift; 992 } 993 ret &= rmask; 994 } 995 if (d->debug) { 996 time_t now = time(NULL); 997 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { 998 d->repeat_count++; 999 if (d->last_sec != now) { 1000 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1001 d->last_sec = now; 1002 d->repeat_count = 0; 1003 } 1004 } else { 1005 if (d->repeat_count) { 1006 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1007 } 1008 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); 1009 d->last_write = 0; 1010 d->last_reg = reg; 1011 d->last_val = ret; 1012 d->last_sec = now; 1013 d->repeat_count = 0; 1014 } 1015 } 1016 return ret; 1017 } 1018 1019 static void intel_hda_regs_reset(IntelHDAState *d) 1020 { 1021 uint32_t *addr; 1022 int i; 1023 1024 for (i = 0; i < ARRAY_SIZE(regtab); i++) { 1025 if (regtab[i].name == NULL) { 1026 continue; 1027 } 1028 if (regtab[i].offset == 0) { 1029 continue; 1030 } 1031 addr = intel_hda_reg_addr(d, regtab + i); 1032 *addr = regtab[i].reset; 1033 } 1034 } 1035 1036 /* --------------------------------------------------------------------- */ 1037 1038 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val, 1039 unsigned size) 1040 { 1041 IntelHDAState *d = opaque; 1042 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1043 1044 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8)); 1045 } 1046 1047 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size) 1048 { 1049 IntelHDAState *d = opaque; 1050 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1051 1052 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8)); 1053 } 1054 1055 static const MemoryRegionOps intel_hda_mmio_ops = { 1056 .read = intel_hda_mmio_read, 1057 .write = intel_hda_mmio_write, 1058 .impl = { 1059 .min_access_size = 1, 1060 .max_access_size = 4, 1061 }, 1062 .endianness = DEVICE_NATIVE_ENDIAN, 1063 }; 1064 1065 /* --------------------------------------------------------------------- */ 1066 1067 static void intel_hda_reset(DeviceState *dev) 1068 { 1069 BusChild *kid; 1070 IntelHDAState *d = INTEL_HDA(dev); 1071 HDACodecDevice *cdev; 1072 1073 intel_hda_regs_reset(d); 1074 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1075 1076 /* reset codecs */ 1077 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 1078 DeviceState *qdev = kid->child; 1079 cdev = HDA_CODEC_DEVICE(qdev); 1080 device_legacy_reset(DEVICE(cdev)); 1081 d->state_sts |= (1 << cdev->cad); 1082 } 1083 intel_hda_update_irq(d); 1084 } 1085 1086 static void intel_hda_realize(PCIDevice *pci, Error **errp) 1087 { 1088 IntelHDAState *d = INTEL_HDA(pci); 1089 uint8_t *conf = d->pci.config; 1090 Error *err = NULL; 1091 int ret; 1092 1093 d->name = object_get_typename(OBJECT(d)); 1094 1095 pci_config_set_interrupt_pin(conf, 1); 1096 1097 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ 1098 conf[0x40] = 0x01; 1099 1100 if (d->msi != ON_OFF_AUTO_OFF) { 1101 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1102 1, true, false, &err); 1103 /* Any error other than -ENOTSUP(board's MSI support is broken) 1104 * is a programming error */ 1105 assert(!ret || ret == -ENOTSUP); 1106 if (ret && d->msi == ON_OFF_AUTO_ON) { 1107 /* Can't satisfy user's explicit msi=on request, fail */ 1108 error_append_hint(&err, "You have to use msi=auto (default) or " 1109 "msi=off with this machine type.\n"); 1110 error_propagate(errp, err); 1111 return; 1112 } 1113 assert(!err || d->msi == ON_OFF_AUTO_AUTO); 1114 /* With msi=auto, we fall back to MSI off silently */ 1115 error_free(err); 1116 } 1117 1118 memory_region_init(&d->container, OBJECT(d), 1119 "intel-hda-container", 0x4000); 1120 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, 1121 "intel-hda", 0x2000); 1122 memory_region_add_subregion(&d->container, 0x0000, &d->mmio); 1123 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias", 1124 &d->mmio, 0, 0x2000); 1125 memory_region_add_subregion(&d->container, 0x2000, &d->alias); 1126 pci_register_bar(&d->pci, 0, 0, &d->container); 1127 1128 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), 1129 intel_hda_response, intel_hda_xfer); 1130 } 1131 1132 static void intel_hda_exit(PCIDevice *pci) 1133 { 1134 IntelHDAState *d = INTEL_HDA(pci); 1135 1136 msi_uninit(&d->pci); 1137 } 1138 1139 static int intel_hda_post_load(void *opaque, int version) 1140 { 1141 IntelHDAState* d = opaque; 1142 int i; 1143 1144 dprint(d, 1, "%s\n", __func__); 1145 for (i = 0; i < ARRAY_SIZE(d->st); i++) { 1146 if (d->st[i].ctl & 0x02) { 1147 intel_hda_parse_bdl(d, &d->st[i]); 1148 } 1149 } 1150 intel_hda_update_irq(d); 1151 return 0; 1152 } 1153 1154 static const VMStateDescription vmstate_intel_hda_stream = { 1155 .name = "intel-hda-stream", 1156 .version_id = 1, 1157 .fields = (VMStateField[]) { 1158 VMSTATE_UINT32(ctl, IntelHDAStream), 1159 VMSTATE_UINT32(lpib, IntelHDAStream), 1160 VMSTATE_UINT32(cbl, IntelHDAStream), 1161 VMSTATE_UINT32(lvi, IntelHDAStream), 1162 VMSTATE_UINT32(fmt, IntelHDAStream), 1163 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), 1164 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), 1165 VMSTATE_END_OF_LIST() 1166 } 1167 }; 1168 1169 static const VMStateDescription vmstate_intel_hda = { 1170 .name = "intel-hda", 1171 .version_id = 1, 1172 .post_load = intel_hda_post_load, 1173 .fields = (VMStateField[]) { 1174 VMSTATE_PCI_DEVICE(pci, IntelHDAState), 1175 1176 /* registers */ 1177 VMSTATE_UINT32(g_ctl, IntelHDAState), 1178 VMSTATE_UINT32(wake_en, IntelHDAState), 1179 VMSTATE_UINT32(state_sts, IntelHDAState), 1180 VMSTATE_UINT32(int_ctl, IntelHDAState), 1181 VMSTATE_UINT32(int_sts, IntelHDAState), 1182 VMSTATE_UINT32(wall_clk, IntelHDAState), 1183 VMSTATE_UINT32(corb_lbase, IntelHDAState), 1184 VMSTATE_UINT32(corb_ubase, IntelHDAState), 1185 VMSTATE_UINT32(corb_rp, IntelHDAState), 1186 VMSTATE_UINT32(corb_wp, IntelHDAState), 1187 VMSTATE_UINT32(corb_ctl, IntelHDAState), 1188 VMSTATE_UINT32(corb_sts, IntelHDAState), 1189 VMSTATE_UINT32(corb_size, IntelHDAState), 1190 VMSTATE_UINT32(rirb_lbase, IntelHDAState), 1191 VMSTATE_UINT32(rirb_ubase, IntelHDAState), 1192 VMSTATE_UINT32(rirb_wp, IntelHDAState), 1193 VMSTATE_UINT32(rirb_cnt, IntelHDAState), 1194 VMSTATE_UINT32(rirb_ctl, IntelHDAState), 1195 VMSTATE_UINT32(rirb_sts, IntelHDAState), 1196 VMSTATE_UINT32(rirb_size, IntelHDAState), 1197 VMSTATE_UINT32(dp_lbase, IntelHDAState), 1198 VMSTATE_UINT32(dp_ubase, IntelHDAState), 1199 VMSTATE_UINT32(icw, IntelHDAState), 1200 VMSTATE_UINT32(irr, IntelHDAState), 1201 VMSTATE_UINT32(ics, IntelHDAState), 1202 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, 1203 vmstate_intel_hda_stream, 1204 IntelHDAStream), 1205 1206 /* additional state info */ 1207 VMSTATE_UINT32(rirb_count, IntelHDAState), 1208 VMSTATE_INT64(wall_base_ns, IntelHDAState), 1209 1210 VMSTATE_END_OF_LIST() 1211 } 1212 }; 1213 1214 static Property intel_hda_properties[] = { 1215 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), 1216 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO), 1217 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false), 1218 DEFINE_PROP_END_OF_LIST(), 1219 }; 1220 1221 static void intel_hda_class_init(ObjectClass *klass, void *data) 1222 { 1223 DeviceClass *dc = DEVICE_CLASS(klass); 1224 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1225 1226 k->realize = intel_hda_realize; 1227 k->exit = intel_hda_exit; 1228 k->vendor_id = PCI_VENDOR_ID_INTEL; 1229 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; 1230 dc->reset = intel_hda_reset; 1231 dc->vmsd = &vmstate_intel_hda; 1232 device_class_set_props(dc, intel_hda_properties); 1233 } 1234 1235 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) 1236 { 1237 DeviceClass *dc = DEVICE_CLASS(klass); 1238 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1239 1240 k->device_id = 0x2668; 1241 k->revision = 1; 1242 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1243 dc->desc = "Intel HD Audio Controller (ich6)"; 1244 } 1245 1246 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data) 1247 { 1248 DeviceClass *dc = DEVICE_CLASS(klass); 1249 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1250 1251 k->device_id = 0x293e; 1252 k->revision = 3; 1253 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1254 dc->desc = "Intel HD Audio Controller (ich9)"; 1255 } 1256 1257 static const TypeInfo intel_hda_info = { 1258 .name = TYPE_INTEL_HDA_GENERIC, 1259 .parent = TYPE_PCI_DEVICE, 1260 .instance_size = sizeof(IntelHDAState), 1261 .class_init = intel_hda_class_init, 1262 .abstract = true, 1263 .interfaces = (InterfaceInfo[]) { 1264 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1265 { }, 1266 }, 1267 }; 1268 1269 static const TypeInfo intel_hda_info_ich6 = { 1270 .name = "intel-hda", 1271 .parent = TYPE_INTEL_HDA_GENERIC, 1272 .class_init = intel_hda_class_init_ich6, 1273 }; 1274 1275 static const TypeInfo intel_hda_info_ich9 = { 1276 .name = "ich9-intel-hda", 1277 .parent = TYPE_INTEL_HDA_GENERIC, 1278 .class_init = intel_hda_class_init_ich9, 1279 }; 1280 1281 static void hda_codec_device_class_init(ObjectClass *klass, void *data) 1282 { 1283 DeviceClass *k = DEVICE_CLASS(klass); 1284 k->realize = hda_codec_dev_realize; 1285 k->unrealize = hda_codec_dev_unrealize; 1286 set_bit(DEVICE_CATEGORY_SOUND, k->categories); 1287 k->bus_type = TYPE_HDA_BUS; 1288 device_class_set_props(k, hda_props); 1289 } 1290 1291 static const TypeInfo hda_codec_device_type_info = { 1292 .name = TYPE_HDA_CODEC_DEVICE, 1293 .parent = TYPE_DEVICE, 1294 .instance_size = sizeof(HDACodecDevice), 1295 .abstract = true, 1296 .class_size = sizeof(HDACodecDeviceClass), 1297 .class_init = hda_codec_device_class_init, 1298 }; 1299 1300 /* 1301 * create intel hda controller with codec attached to it, 1302 * so '-soundhw hda' works. 1303 */ 1304 static int intel_hda_and_codec_init(PCIBus *bus) 1305 { 1306 DeviceState *controller; 1307 BusState *hdabus; 1308 DeviceState *codec; 1309 1310 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); 1311 hdabus = QLIST_FIRST(&controller->child_bus); 1312 codec = qdev_create(hdabus, "hda-duplex"); 1313 qdev_init_nofail(codec); 1314 return 0; 1315 } 1316 1317 static void intel_hda_register_types(void) 1318 { 1319 type_register_static(&hda_codec_bus_info); 1320 type_register_static(&intel_hda_info); 1321 type_register_static(&intel_hda_info_ich6); 1322 type_register_static(&intel_hda_info_ich9); 1323 type_register_static(&hda_codec_device_type_info); 1324 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init); 1325 } 1326 1327 type_init(intel_hda_register_types) 1328