1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Gerd Hoffmann <kraxel@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "hw/hw.h" 21 #include "hw/pci/pci.h" 22 #include "hw/pci/msi.h" 23 #include "qemu/timer.h" 24 #include "hw/audio/audio.h" 25 #include "intel-hda.h" 26 #include "intel-hda-defs.h" 27 #include "sysemu/dma.h" 28 29 /* --------------------------------------------------------------------- */ 30 /* hda bus */ 31 32 static Property hda_props[] = { 33 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), 34 DEFINE_PROP_END_OF_LIST() 35 }; 36 37 static const TypeInfo hda_codec_bus_info = { 38 .name = TYPE_HDA_BUS, 39 .parent = TYPE_BUS, 40 .instance_size = sizeof(HDACodecBus), 41 }; 42 43 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, 44 hda_codec_response_func response, 45 hda_codec_xfer_func xfer) 46 { 47 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL); 48 bus->response = response; 49 bus->xfer = xfer; 50 } 51 52 static int hda_codec_dev_init(DeviceState *qdev) 53 { 54 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus); 55 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); 56 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 57 58 if (dev->cad == -1) { 59 dev->cad = bus->next_cad; 60 } 61 if (dev->cad >= 15) { 62 return -1; 63 } 64 bus->next_cad = dev->cad + 1; 65 return cdc->init(dev); 66 } 67 68 static int hda_codec_dev_exit(DeviceState *qdev) 69 { 70 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); 71 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 72 73 if (cdc->exit) { 74 cdc->exit(dev); 75 } 76 return 0; 77 } 78 79 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) 80 { 81 BusChild *kid; 82 HDACodecDevice *cdev; 83 84 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { 85 DeviceState *qdev = kid->child; 86 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); 87 if (cdev->cad == cad) { 88 return cdev; 89 } 90 } 91 return NULL; 92 } 93 94 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) 95 { 96 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); 97 bus->response(dev, solicited, response); 98 } 99 100 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 101 uint8_t *buf, uint32_t len) 102 { 103 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); 104 return bus->xfer(dev, stnr, output, buf, len); 105 } 106 107 /* --------------------------------------------------------------------- */ 108 /* intel hda emulation */ 109 110 typedef struct IntelHDAStream IntelHDAStream; 111 typedef struct IntelHDAState IntelHDAState; 112 typedef struct IntelHDAReg IntelHDAReg; 113 114 typedef struct bpl { 115 uint64_t addr; 116 uint32_t len; 117 uint32_t flags; 118 } bpl; 119 120 struct IntelHDAStream { 121 /* registers */ 122 uint32_t ctl; 123 uint32_t lpib; 124 uint32_t cbl; 125 uint32_t lvi; 126 uint32_t fmt; 127 uint32_t bdlp_lbase; 128 uint32_t bdlp_ubase; 129 130 /* state */ 131 bpl *bpl; 132 uint32_t bentries; 133 uint32_t bsize, be, bp; 134 }; 135 136 struct IntelHDAState { 137 PCIDevice pci; 138 const char *name; 139 HDACodecBus codecs; 140 141 /* registers */ 142 uint32_t g_ctl; 143 uint32_t wake_en; 144 uint32_t state_sts; 145 uint32_t int_ctl; 146 uint32_t int_sts; 147 uint32_t wall_clk; 148 149 uint32_t corb_lbase; 150 uint32_t corb_ubase; 151 uint32_t corb_rp; 152 uint32_t corb_wp; 153 uint32_t corb_ctl; 154 uint32_t corb_sts; 155 uint32_t corb_size; 156 157 uint32_t rirb_lbase; 158 uint32_t rirb_ubase; 159 uint32_t rirb_wp; 160 uint32_t rirb_cnt; 161 uint32_t rirb_ctl; 162 uint32_t rirb_sts; 163 uint32_t rirb_size; 164 165 uint32_t dp_lbase; 166 uint32_t dp_ubase; 167 168 uint32_t icw; 169 uint32_t irr; 170 uint32_t ics; 171 172 /* streams */ 173 IntelHDAStream st[8]; 174 175 /* state */ 176 MemoryRegion mmio; 177 uint32_t rirb_count; 178 int64_t wall_base_ns; 179 180 /* debug logging */ 181 const IntelHDAReg *last_reg; 182 uint32_t last_val; 183 uint32_t last_write; 184 uint32_t last_sec; 185 uint32_t repeat_count; 186 187 /* properties */ 188 uint32_t debug; 189 uint32_t msi; 190 bool old_msi_addr; 191 }; 192 193 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic" 194 195 #define INTEL_HDA(obj) \ 196 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC) 197 198 struct IntelHDAReg { 199 const char *name; /* register name */ 200 uint32_t size; /* size in bytes */ 201 uint32_t reset; /* reset value */ 202 uint32_t wmask; /* write mask */ 203 uint32_t wclear; /* write 1 to clear bits */ 204 uint32_t offset; /* location in IntelHDAState */ 205 uint32_t shift; /* byte access entries for dwords */ 206 uint32_t stream; 207 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); 208 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); 209 }; 210 211 static void intel_hda_reset(DeviceState *dev); 212 213 /* --------------------------------------------------------------------- */ 214 215 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) 216 { 217 hwaddr addr; 218 219 addr = ((uint64_t)ubase << 32) | lbase; 220 return addr; 221 } 222 223 static void intel_hda_update_int_sts(IntelHDAState *d) 224 { 225 uint32_t sts = 0; 226 uint32_t i; 227 228 /* update controller status */ 229 if (d->rirb_sts & ICH6_RBSTS_IRQ) { 230 sts |= (1 << 30); 231 } 232 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { 233 sts |= (1 << 30); 234 } 235 if (d->state_sts & d->wake_en) { 236 sts |= (1 << 30); 237 } 238 239 /* update stream status */ 240 for (i = 0; i < 8; i++) { 241 /* buffer completion interrupt */ 242 if (d->st[i].ctl & (1 << 26)) { 243 sts |= (1 << i); 244 } 245 } 246 247 /* update global status */ 248 if (sts & d->int_ctl) { 249 sts |= (1U << 31); 250 } 251 252 d->int_sts = sts; 253 } 254 255 static void intel_hda_update_irq(IntelHDAState *d) 256 { 257 int msi = d->msi && msi_enabled(&d->pci); 258 int level; 259 260 intel_hda_update_int_sts(d); 261 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { 262 level = 1; 263 } else { 264 level = 0; 265 } 266 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__, 267 level, msi ? "msi" : "intx"); 268 if (msi) { 269 if (level) { 270 msi_notify(&d->pci, 0); 271 } 272 } else { 273 pci_set_irq(&d->pci, level); 274 } 275 } 276 277 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) 278 { 279 uint32_t cad, nid, data; 280 HDACodecDevice *codec; 281 HDACodecDeviceClass *cdc; 282 283 cad = (verb >> 28) & 0x0f; 284 if (verb & (1 << 27)) { 285 /* indirect node addressing, not specified in HDA 1.0 */ 286 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__); 287 return -1; 288 } 289 nid = (verb >> 20) & 0x7f; 290 data = verb & 0xfffff; 291 292 codec = hda_codec_find(&d->codecs, cad); 293 if (codec == NULL) { 294 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__); 295 return -1; 296 } 297 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec); 298 cdc->command(codec, nid, data); 299 return 0; 300 } 301 302 static void intel_hda_corb_run(IntelHDAState *d) 303 { 304 hwaddr addr; 305 uint32_t rp, verb; 306 307 if (d->ics & ICH6_IRS_BUSY) { 308 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw); 309 intel_hda_send_command(d, d->icw); 310 return; 311 } 312 313 for (;;) { 314 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { 315 dprint(d, 2, "%s: !run\n", __FUNCTION__); 316 return; 317 } 318 if ((d->corb_rp & 0xff) == d->corb_wp) { 319 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__); 320 return; 321 } 322 if (d->rirb_count == d->rirb_cnt) { 323 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__); 324 return; 325 } 326 327 rp = (d->corb_rp + 1) & 0xff; 328 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); 329 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp); 330 d->corb_rp = rp; 331 332 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb); 333 intel_hda_send_command(d, verb); 334 } 335 } 336 337 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) 338 { 339 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); 340 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 341 hwaddr addr; 342 uint32_t wp, ex; 343 344 if (d->ics & ICH6_IRS_BUSY) { 345 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", 346 __FUNCTION__, response, dev->cad); 347 d->irr = response; 348 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); 349 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); 350 return; 351 } 352 353 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { 354 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__); 355 return; 356 } 357 358 ex = (solicited ? 0 : (1 << 4)) | dev->cad; 359 wp = (d->rirb_wp + 1) & 0xff; 360 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); 361 stl_le_pci_dma(&d->pci, addr + 8*wp, response); 362 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex); 363 d->rirb_wp = wp; 364 365 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", 366 __FUNCTION__, wp, response, ex); 367 368 d->rirb_count++; 369 if (d->rirb_count == d->rirb_cnt) { 370 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count); 371 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 372 d->rirb_sts |= ICH6_RBSTS_IRQ; 373 intel_hda_update_irq(d); 374 } 375 } else if ((d->corb_rp & 0xff) == d->corb_wp) { 376 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__, 377 d->rirb_count, d->rirb_cnt); 378 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 379 d->rirb_sts |= ICH6_RBSTS_IRQ; 380 intel_hda_update_irq(d); 381 } 382 } 383 } 384 385 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 386 uint8_t *buf, uint32_t len) 387 { 388 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); 389 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 390 hwaddr addr; 391 uint32_t s, copy, left; 392 IntelHDAStream *st; 393 bool irq = false; 394 395 st = output ? d->st + 4 : d->st; 396 for (s = 0; s < 4; s++) { 397 if (stnr == ((st[s].ctl >> 20) & 0x0f)) { 398 st = st + s; 399 break; 400 } 401 } 402 if (s == 4) { 403 return false; 404 } 405 if (st->bpl == NULL) { 406 return false; 407 } 408 if (st->ctl & (1 << 26)) { 409 /* 410 * Wait with the next DMA xfer until the guest 411 * has acked the buffer completion interrupt 412 */ 413 return false; 414 } 415 416 left = len; 417 while (left > 0) { 418 copy = left; 419 if (copy > st->bsize - st->lpib) 420 copy = st->bsize - st->lpib; 421 if (copy > st->bpl[st->be].len - st->bp) 422 copy = st->bpl[st->be].len - st->bp; 423 424 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", 425 st->be, st->bp, st->bpl[st->be].len, copy); 426 427 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output); 428 st->lpib += copy; 429 st->bp += copy; 430 buf += copy; 431 left -= copy; 432 433 if (st->bpl[st->be].len == st->bp) { 434 /* bpl entry filled */ 435 if (st->bpl[st->be].flags & 0x01) { 436 irq = true; 437 } 438 st->bp = 0; 439 st->be++; 440 if (st->be == st->bentries) { 441 /* bpl wrap around */ 442 st->be = 0; 443 st->lpib = 0; 444 } 445 } 446 } 447 if (d->dp_lbase & 0x01) { 448 s = st - d->st; 449 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); 450 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib); 451 } 452 dprint(d, 3, "dma: --\n"); 453 454 if (irq) { 455 st->ctl |= (1 << 26); /* buffer completion interrupt */ 456 intel_hda_update_irq(d); 457 } 458 return true; 459 } 460 461 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) 462 { 463 hwaddr addr; 464 uint8_t buf[16]; 465 uint32_t i; 466 467 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); 468 st->bentries = st->lvi +1; 469 g_free(st->bpl); 470 st->bpl = g_malloc(sizeof(bpl) * st->bentries); 471 for (i = 0; i < st->bentries; i++, addr += 16) { 472 pci_dma_read(&d->pci, addr, buf, 16); 473 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); 474 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); 475 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); 476 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", 477 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); 478 } 479 480 st->bsize = st->cbl; 481 st->lpib = 0; 482 st->be = 0; 483 st->bp = 0; 484 } 485 486 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) 487 { 488 BusChild *kid; 489 HDACodecDevice *cdev; 490 491 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 492 DeviceState *qdev = kid->child; 493 HDACodecDeviceClass *cdc; 494 495 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); 496 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev); 497 if (cdc->stream) { 498 cdc->stream(cdev, stream, running, output); 499 } 500 } 501 } 502 503 /* --------------------------------------------------------------------- */ 504 505 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 506 { 507 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { 508 intel_hda_reset(DEVICE(d)); 509 } 510 } 511 512 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 513 { 514 intel_hda_update_irq(d); 515 } 516 517 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 518 { 519 intel_hda_update_irq(d); 520 } 521 522 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 523 { 524 intel_hda_update_irq(d); 525 } 526 527 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) 528 { 529 int64_t ns; 530 531 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; 532 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ 533 } 534 535 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 536 { 537 intel_hda_corb_run(d); 538 } 539 540 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 541 { 542 intel_hda_corb_run(d); 543 } 544 545 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 546 { 547 if (d->rirb_wp & ICH6_RIRBWP_RST) { 548 d->rirb_wp = 0; 549 } 550 } 551 552 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 553 { 554 intel_hda_update_irq(d); 555 556 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { 557 /* cleared ICH6_RBSTS_IRQ */ 558 d->rirb_count = 0; 559 intel_hda_corb_run(d); 560 } 561 } 562 563 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 564 { 565 if (d->ics & ICH6_IRS_BUSY) { 566 intel_hda_corb_run(d); 567 } 568 } 569 570 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 571 { 572 bool output = reg->stream >= 4; 573 IntelHDAStream *st = d->st + reg->stream; 574 575 if (st->ctl & 0x01) { 576 /* reset */ 577 dprint(d, 1, "st #%d: reset\n", reg->stream); 578 st->ctl = SD_STS_FIFO_READY << 24; 579 } 580 if ((st->ctl & 0x02) != (old & 0x02)) { 581 uint32_t stnr = (st->ctl >> 20) & 0x0f; 582 /* run bit flipped */ 583 if (st->ctl & 0x02) { 584 /* start */ 585 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", 586 reg->stream, stnr, st->cbl); 587 intel_hda_parse_bdl(d, st); 588 intel_hda_notify_codecs(d, stnr, true, output); 589 } else { 590 /* stop */ 591 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); 592 intel_hda_notify_codecs(d, stnr, false, output); 593 } 594 } 595 intel_hda_update_irq(d); 596 } 597 598 /* --------------------------------------------------------------------- */ 599 600 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) 601 602 static const struct IntelHDAReg regtab[] = { 603 /* global */ 604 [ ICH6_REG_GCAP ] = { 605 .name = "GCAP", 606 .size = 2, 607 .reset = 0x4401, 608 }, 609 [ ICH6_REG_VMIN ] = { 610 .name = "VMIN", 611 .size = 1, 612 }, 613 [ ICH6_REG_VMAJ ] = { 614 .name = "VMAJ", 615 .size = 1, 616 .reset = 1, 617 }, 618 [ ICH6_REG_OUTPAY ] = { 619 .name = "OUTPAY", 620 .size = 2, 621 .reset = 0x3c, 622 }, 623 [ ICH6_REG_INPAY ] = { 624 .name = "INPAY", 625 .size = 2, 626 .reset = 0x1d, 627 }, 628 [ ICH6_REG_GCTL ] = { 629 .name = "GCTL", 630 .size = 4, 631 .wmask = 0x0103, 632 .offset = offsetof(IntelHDAState, g_ctl), 633 .whandler = intel_hda_set_g_ctl, 634 }, 635 [ ICH6_REG_WAKEEN ] = { 636 .name = "WAKEEN", 637 .size = 2, 638 .wmask = 0x7fff, 639 .offset = offsetof(IntelHDAState, wake_en), 640 .whandler = intel_hda_set_wake_en, 641 }, 642 [ ICH6_REG_STATESTS ] = { 643 .name = "STATESTS", 644 .size = 2, 645 .wmask = 0x7fff, 646 .wclear = 0x7fff, 647 .offset = offsetof(IntelHDAState, state_sts), 648 .whandler = intel_hda_set_state_sts, 649 }, 650 651 /* interrupts */ 652 [ ICH6_REG_INTCTL ] = { 653 .name = "INTCTL", 654 .size = 4, 655 .wmask = 0xc00000ff, 656 .offset = offsetof(IntelHDAState, int_ctl), 657 .whandler = intel_hda_set_int_ctl, 658 }, 659 [ ICH6_REG_INTSTS ] = { 660 .name = "INTSTS", 661 .size = 4, 662 .wmask = 0xc00000ff, 663 .wclear = 0xc00000ff, 664 .offset = offsetof(IntelHDAState, int_sts), 665 }, 666 667 /* misc */ 668 [ ICH6_REG_WALLCLK ] = { 669 .name = "WALLCLK", 670 .size = 4, 671 .offset = offsetof(IntelHDAState, wall_clk), 672 .rhandler = intel_hda_get_wall_clk, 673 }, 674 [ ICH6_REG_WALLCLK + 0x2000 ] = { 675 .name = "WALLCLK(alias)", 676 .size = 4, 677 .offset = offsetof(IntelHDAState, wall_clk), 678 .rhandler = intel_hda_get_wall_clk, 679 }, 680 681 /* dma engine */ 682 [ ICH6_REG_CORBLBASE ] = { 683 .name = "CORBLBASE", 684 .size = 4, 685 .wmask = 0xffffff80, 686 .offset = offsetof(IntelHDAState, corb_lbase), 687 }, 688 [ ICH6_REG_CORBUBASE ] = { 689 .name = "CORBUBASE", 690 .size = 4, 691 .wmask = 0xffffffff, 692 .offset = offsetof(IntelHDAState, corb_ubase), 693 }, 694 [ ICH6_REG_CORBWP ] = { 695 .name = "CORBWP", 696 .size = 2, 697 .wmask = 0xff, 698 .offset = offsetof(IntelHDAState, corb_wp), 699 .whandler = intel_hda_set_corb_wp, 700 }, 701 [ ICH6_REG_CORBRP ] = { 702 .name = "CORBRP", 703 .size = 2, 704 .wmask = 0x80ff, 705 .offset = offsetof(IntelHDAState, corb_rp), 706 }, 707 [ ICH6_REG_CORBCTL ] = { 708 .name = "CORBCTL", 709 .size = 1, 710 .wmask = 0x03, 711 .offset = offsetof(IntelHDAState, corb_ctl), 712 .whandler = intel_hda_set_corb_ctl, 713 }, 714 [ ICH6_REG_CORBSTS ] = { 715 .name = "CORBSTS", 716 .size = 1, 717 .wmask = 0x01, 718 .wclear = 0x01, 719 .offset = offsetof(IntelHDAState, corb_sts), 720 }, 721 [ ICH6_REG_CORBSIZE ] = { 722 .name = "CORBSIZE", 723 .size = 1, 724 .reset = 0x42, 725 .offset = offsetof(IntelHDAState, corb_size), 726 }, 727 [ ICH6_REG_RIRBLBASE ] = { 728 .name = "RIRBLBASE", 729 .size = 4, 730 .wmask = 0xffffff80, 731 .offset = offsetof(IntelHDAState, rirb_lbase), 732 }, 733 [ ICH6_REG_RIRBUBASE ] = { 734 .name = "RIRBUBASE", 735 .size = 4, 736 .wmask = 0xffffffff, 737 .offset = offsetof(IntelHDAState, rirb_ubase), 738 }, 739 [ ICH6_REG_RIRBWP ] = { 740 .name = "RIRBWP", 741 .size = 2, 742 .wmask = 0x8000, 743 .offset = offsetof(IntelHDAState, rirb_wp), 744 .whandler = intel_hda_set_rirb_wp, 745 }, 746 [ ICH6_REG_RINTCNT ] = { 747 .name = "RINTCNT", 748 .size = 2, 749 .wmask = 0xff, 750 .offset = offsetof(IntelHDAState, rirb_cnt), 751 }, 752 [ ICH6_REG_RIRBCTL ] = { 753 .name = "RIRBCTL", 754 .size = 1, 755 .wmask = 0x07, 756 .offset = offsetof(IntelHDAState, rirb_ctl), 757 }, 758 [ ICH6_REG_RIRBSTS ] = { 759 .name = "RIRBSTS", 760 .size = 1, 761 .wmask = 0x05, 762 .wclear = 0x05, 763 .offset = offsetof(IntelHDAState, rirb_sts), 764 .whandler = intel_hda_set_rirb_sts, 765 }, 766 [ ICH6_REG_RIRBSIZE ] = { 767 .name = "RIRBSIZE", 768 .size = 1, 769 .reset = 0x42, 770 .offset = offsetof(IntelHDAState, rirb_size), 771 }, 772 773 [ ICH6_REG_DPLBASE ] = { 774 .name = "DPLBASE", 775 .size = 4, 776 .wmask = 0xffffff81, 777 .offset = offsetof(IntelHDAState, dp_lbase), 778 }, 779 [ ICH6_REG_DPUBASE ] = { 780 .name = "DPUBASE", 781 .size = 4, 782 .wmask = 0xffffffff, 783 .offset = offsetof(IntelHDAState, dp_ubase), 784 }, 785 786 [ ICH6_REG_IC ] = { 787 .name = "ICW", 788 .size = 4, 789 .wmask = 0xffffffff, 790 .offset = offsetof(IntelHDAState, icw), 791 }, 792 [ ICH6_REG_IR ] = { 793 .name = "IRR", 794 .size = 4, 795 .offset = offsetof(IntelHDAState, irr), 796 }, 797 [ ICH6_REG_IRS ] = { 798 .name = "ICS", 799 .size = 2, 800 .wmask = 0x0003, 801 .wclear = 0x0002, 802 .offset = offsetof(IntelHDAState, ics), 803 .whandler = intel_hda_set_ics, 804 }, 805 806 #define HDA_STREAM(_t, _i) \ 807 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ 808 .stream = _i, \ 809 .name = _t stringify(_i) " CTL", \ 810 .size = 4, \ 811 .wmask = 0x1cff001f, \ 812 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 813 .whandler = intel_hda_set_st_ctl, \ 814 }, \ 815 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ 816 .stream = _i, \ 817 .name = _t stringify(_i) " CTL(stnr)", \ 818 .size = 1, \ 819 .shift = 16, \ 820 .wmask = 0x00ff0000, \ 821 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 822 .whandler = intel_hda_set_st_ctl, \ 823 }, \ 824 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ 825 .stream = _i, \ 826 .name = _t stringify(_i) " CTL(sts)", \ 827 .size = 1, \ 828 .shift = 24, \ 829 .wmask = 0x1c000000, \ 830 .wclear = 0x1c000000, \ 831 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 832 .whandler = intel_hda_set_st_ctl, \ 833 .reset = SD_STS_FIFO_READY << 24 \ 834 }, \ 835 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ 836 .stream = _i, \ 837 .name = _t stringify(_i) " LPIB", \ 838 .size = 4, \ 839 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 840 }, \ 841 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \ 842 .stream = _i, \ 843 .name = _t stringify(_i) " LPIB(alias)", \ 844 .size = 4, \ 845 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 846 }, \ 847 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ 848 .stream = _i, \ 849 .name = _t stringify(_i) " CBL", \ 850 .size = 4, \ 851 .wmask = 0xffffffff, \ 852 .offset = offsetof(IntelHDAState, st[_i].cbl), \ 853 }, \ 854 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ 855 .stream = _i, \ 856 .name = _t stringify(_i) " LVI", \ 857 .size = 2, \ 858 .wmask = 0x00ff, \ 859 .offset = offsetof(IntelHDAState, st[_i].lvi), \ 860 }, \ 861 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ 862 .stream = _i, \ 863 .name = _t stringify(_i) " FIFOS", \ 864 .size = 2, \ 865 .reset = HDA_BUFFER_SIZE, \ 866 }, \ 867 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ 868 .stream = _i, \ 869 .name = _t stringify(_i) " FMT", \ 870 .size = 2, \ 871 .wmask = 0x7f7f, \ 872 .offset = offsetof(IntelHDAState, st[_i].fmt), \ 873 }, \ 874 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ 875 .stream = _i, \ 876 .name = _t stringify(_i) " BDLPL", \ 877 .size = 4, \ 878 .wmask = 0xffffff80, \ 879 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ 880 }, \ 881 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ 882 .stream = _i, \ 883 .name = _t stringify(_i) " BDLPU", \ 884 .size = 4, \ 885 .wmask = 0xffffffff, \ 886 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ 887 }, \ 888 889 HDA_STREAM("IN", 0) 890 HDA_STREAM("IN", 1) 891 HDA_STREAM("IN", 2) 892 HDA_STREAM("IN", 3) 893 894 HDA_STREAM("OUT", 4) 895 HDA_STREAM("OUT", 5) 896 HDA_STREAM("OUT", 6) 897 HDA_STREAM("OUT", 7) 898 899 }; 900 901 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) 902 { 903 const IntelHDAReg *reg; 904 905 if (addr >= ARRAY_SIZE(regtab)) { 906 goto noreg; 907 } 908 reg = regtab+addr; 909 if (reg->name == NULL) { 910 goto noreg; 911 } 912 return reg; 913 914 noreg: 915 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); 916 return NULL; 917 } 918 919 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) 920 { 921 uint8_t *addr = (void*)d; 922 923 addr += reg->offset; 924 return (uint32_t*)addr; 925 } 926 927 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, 928 uint32_t wmask) 929 { 930 uint32_t *addr; 931 uint32_t old; 932 933 if (!reg) { 934 return; 935 } 936 937 if (d->debug) { 938 time_t now = time(NULL); 939 if (d->last_write && d->last_reg == reg && d->last_val == val) { 940 d->repeat_count++; 941 if (d->last_sec != now) { 942 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 943 d->last_sec = now; 944 d->repeat_count = 0; 945 } 946 } else { 947 if (d->repeat_count) { 948 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 949 } 950 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); 951 d->last_write = 1; 952 d->last_reg = reg; 953 d->last_val = val; 954 d->last_sec = now; 955 d->repeat_count = 0; 956 } 957 } 958 assert(reg->offset != 0); 959 960 addr = intel_hda_reg_addr(d, reg); 961 old = *addr; 962 963 if (reg->shift) { 964 val <<= reg->shift; 965 wmask <<= reg->shift; 966 } 967 wmask &= reg->wmask; 968 *addr &= ~wmask; 969 *addr |= wmask & val; 970 *addr &= ~(val & reg->wclear); 971 972 if (reg->whandler) { 973 reg->whandler(d, reg, old); 974 } 975 } 976 977 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, 978 uint32_t rmask) 979 { 980 uint32_t *addr, ret; 981 982 if (!reg) { 983 return 0; 984 } 985 986 if (reg->rhandler) { 987 reg->rhandler(d, reg); 988 } 989 990 if (reg->offset == 0) { 991 /* constant read-only register */ 992 ret = reg->reset; 993 } else { 994 addr = intel_hda_reg_addr(d, reg); 995 ret = *addr; 996 if (reg->shift) { 997 ret >>= reg->shift; 998 } 999 ret &= rmask; 1000 } 1001 if (d->debug) { 1002 time_t now = time(NULL); 1003 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { 1004 d->repeat_count++; 1005 if (d->last_sec != now) { 1006 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1007 d->last_sec = now; 1008 d->repeat_count = 0; 1009 } 1010 } else { 1011 if (d->repeat_count) { 1012 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1013 } 1014 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); 1015 d->last_write = 0; 1016 d->last_reg = reg; 1017 d->last_val = ret; 1018 d->last_sec = now; 1019 d->repeat_count = 0; 1020 } 1021 } 1022 return ret; 1023 } 1024 1025 static void intel_hda_regs_reset(IntelHDAState *d) 1026 { 1027 uint32_t *addr; 1028 int i; 1029 1030 for (i = 0; i < ARRAY_SIZE(regtab); i++) { 1031 if (regtab[i].name == NULL) { 1032 continue; 1033 } 1034 if (regtab[i].offset == 0) { 1035 continue; 1036 } 1037 addr = intel_hda_reg_addr(d, regtab + i); 1038 *addr = regtab[i].reset; 1039 } 1040 } 1041 1042 /* --------------------------------------------------------------------- */ 1043 1044 static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) 1045 { 1046 IntelHDAState *d = opaque; 1047 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1048 1049 intel_hda_reg_write(d, reg, val, 0xff); 1050 } 1051 1052 static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val) 1053 { 1054 IntelHDAState *d = opaque; 1055 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1056 1057 intel_hda_reg_write(d, reg, val, 0xffff); 1058 } 1059 1060 static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val) 1061 { 1062 IntelHDAState *d = opaque; 1063 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1064 1065 intel_hda_reg_write(d, reg, val, 0xffffffff); 1066 } 1067 1068 static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr) 1069 { 1070 IntelHDAState *d = opaque; 1071 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1072 1073 return intel_hda_reg_read(d, reg, 0xff); 1074 } 1075 1076 static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr) 1077 { 1078 IntelHDAState *d = opaque; 1079 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1080 1081 return intel_hda_reg_read(d, reg, 0xffff); 1082 } 1083 1084 static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr) 1085 { 1086 IntelHDAState *d = opaque; 1087 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1088 1089 return intel_hda_reg_read(d, reg, 0xffffffff); 1090 } 1091 1092 static const MemoryRegionOps intel_hda_mmio_ops = { 1093 .old_mmio = { 1094 .read = { 1095 intel_hda_mmio_readb, 1096 intel_hda_mmio_readw, 1097 intel_hda_mmio_readl, 1098 }, 1099 .write = { 1100 intel_hda_mmio_writeb, 1101 intel_hda_mmio_writew, 1102 intel_hda_mmio_writel, 1103 }, 1104 }, 1105 .endianness = DEVICE_NATIVE_ENDIAN, 1106 }; 1107 1108 /* --------------------------------------------------------------------- */ 1109 1110 static void intel_hda_reset(DeviceState *dev) 1111 { 1112 BusChild *kid; 1113 IntelHDAState *d = INTEL_HDA(dev); 1114 HDACodecDevice *cdev; 1115 1116 intel_hda_regs_reset(d); 1117 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1118 1119 /* reset codecs */ 1120 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 1121 DeviceState *qdev = kid->child; 1122 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); 1123 device_reset(DEVICE(cdev)); 1124 d->state_sts |= (1 << cdev->cad); 1125 } 1126 intel_hda_update_irq(d); 1127 } 1128 1129 static int intel_hda_init(PCIDevice *pci) 1130 { 1131 IntelHDAState *d = INTEL_HDA(pci); 1132 uint8_t *conf = d->pci.config; 1133 1134 d->name = object_get_typename(OBJECT(d)); 1135 1136 pci_config_set_interrupt_pin(conf, 1); 1137 1138 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ 1139 conf[0x40] = 0x01; 1140 1141 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, 1142 "intel-hda", 0x4000); 1143 pci_register_bar(&d->pci, 0, 0, &d->mmio); 1144 if (d->msi) { 1145 msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1, true, false); 1146 } 1147 1148 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), 1149 intel_hda_response, intel_hda_xfer); 1150 1151 return 0; 1152 } 1153 1154 static void intel_hda_exit(PCIDevice *pci) 1155 { 1156 IntelHDAState *d = INTEL_HDA(pci); 1157 1158 msi_uninit(&d->pci); 1159 } 1160 1161 static int intel_hda_post_load(void *opaque, int version) 1162 { 1163 IntelHDAState* d = opaque; 1164 int i; 1165 1166 dprint(d, 1, "%s\n", __FUNCTION__); 1167 for (i = 0; i < ARRAY_SIZE(d->st); i++) { 1168 if (d->st[i].ctl & 0x02) { 1169 intel_hda_parse_bdl(d, &d->st[i]); 1170 } 1171 } 1172 intel_hda_update_irq(d); 1173 return 0; 1174 } 1175 1176 static const VMStateDescription vmstate_intel_hda_stream = { 1177 .name = "intel-hda-stream", 1178 .version_id = 1, 1179 .fields = (VMStateField[]) { 1180 VMSTATE_UINT32(ctl, IntelHDAStream), 1181 VMSTATE_UINT32(lpib, IntelHDAStream), 1182 VMSTATE_UINT32(cbl, IntelHDAStream), 1183 VMSTATE_UINT32(lvi, IntelHDAStream), 1184 VMSTATE_UINT32(fmt, IntelHDAStream), 1185 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), 1186 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), 1187 VMSTATE_END_OF_LIST() 1188 } 1189 }; 1190 1191 static const VMStateDescription vmstate_intel_hda = { 1192 .name = "intel-hda", 1193 .version_id = 1, 1194 .post_load = intel_hda_post_load, 1195 .fields = (VMStateField[]) { 1196 VMSTATE_PCI_DEVICE(pci, IntelHDAState), 1197 1198 /* registers */ 1199 VMSTATE_UINT32(g_ctl, IntelHDAState), 1200 VMSTATE_UINT32(wake_en, IntelHDAState), 1201 VMSTATE_UINT32(state_sts, IntelHDAState), 1202 VMSTATE_UINT32(int_ctl, IntelHDAState), 1203 VMSTATE_UINT32(int_sts, IntelHDAState), 1204 VMSTATE_UINT32(wall_clk, IntelHDAState), 1205 VMSTATE_UINT32(corb_lbase, IntelHDAState), 1206 VMSTATE_UINT32(corb_ubase, IntelHDAState), 1207 VMSTATE_UINT32(corb_rp, IntelHDAState), 1208 VMSTATE_UINT32(corb_wp, IntelHDAState), 1209 VMSTATE_UINT32(corb_ctl, IntelHDAState), 1210 VMSTATE_UINT32(corb_sts, IntelHDAState), 1211 VMSTATE_UINT32(corb_size, IntelHDAState), 1212 VMSTATE_UINT32(rirb_lbase, IntelHDAState), 1213 VMSTATE_UINT32(rirb_ubase, IntelHDAState), 1214 VMSTATE_UINT32(rirb_wp, IntelHDAState), 1215 VMSTATE_UINT32(rirb_cnt, IntelHDAState), 1216 VMSTATE_UINT32(rirb_ctl, IntelHDAState), 1217 VMSTATE_UINT32(rirb_sts, IntelHDAState), 1218 VMSTATE_UINT32(rirb_size, IntelHDAState), 1219 VMSTATE_UINT32(dp_lbase, IntelHDAState), 1220 VMSTATE_UINT32(dp_ubase, IntelHDAState), 1221 VMSTATE_UINT32(icw, IntelHDAState), 1222 VMSTATE_UINT32(irr, IntelHDAState), 1223 VMSTATE_UINT32(ics, IntelHDAState), 1224 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, 1225 vmstate_intel_hda_stream, 1226 IntelHDAStream), 1227 1228 /* additional state info */ 1229 VMSTATE_UINT32(rirb_count, IntelHDAState), 1230 VMSTATE_INT64(wall_base_ns, IntelHDAState), 1231 1232 VMSTATE_END_OF_LIST() 1233 } 1234 }; 1235 1236 static Property intel_hda_properties[] = { 1237 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), 1238 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1), 1239 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false), 1240 DEFINE_PROP_END_OF_LIST(), 1241 }; 1242 1243 static void intel_hda_class_init(ObjectClass *klass, void *data) 1244 { 1245 DeviceClass *dc = DEVICE_CLASS(klass); 1246 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1247 1248 k->init = intel_hda_init; 1249 k->exit = intel_hda_exit; 1250 k->vendor_id = PCI_VENDOR_ID_INTEL; 1251 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; 1252 dc->reset = intel_hda_reset; 1253 dc->vmsd = &vmstate_intel_hda; 1254 dc->props = intel_hda_properties; 1255 } 1256 1257 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) 1258 { 1259 DeviceClass *dc = DEVICE_CLASS(klass); 1260 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1261 1262 k->device_id = 0x2668; 1263 k->revision = 1; 1264 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1265 dc->desc = "Intel HD Audio Controller (ich6)"; 1266 } 1267 1268 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data) 1269 { 1270 DeviceClass *dc = DEVICE_CLASS(klass); 1271 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1272 1273 k->device_id = 0x293e; 1274 k->revision = 3; 1275 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1276 dc->desc = "Intel HD Audio Controller (ich9)"; 1277 } 1278 1279 static const TypeInfo intel_hda_info = { 1280 .name = TYPE_INTEL_HDA_GENERIC, 1281 .parent = TYPE_PCI_DEVICE, 1282 .instance_size = sizeof(IntelHDAState), 1283 .class_init = intel_hda_class_init, 1284 .abstract = true, 1285 }; 1286 1287 static const TypeInfo intel_hda_info_ich6 = { 1288 .name = "intel-hda", 1289 .parent = TYPE_INTEL_HDA_GENERIC, 1290 .class_init = intel_hda_class_init_ich6, 1291 }; 1292 1293 static const TypeInfo intel_hda_info_ich9 = { 1294 .name = "ich9-intel-hda", 1295 .parent = TYPE_INTEL_HDA_GENERIC, 1296 .class_init = intel_hda_class_init_ich9, 1297 }; 1298 1299 static void hda_codec_device_class_init(ObjectClass *klass, void *data) 1300 { 1301 DeviceClass *k = DEVICE_CLASS(klass); 1302 k->init = hda_codec_dev_init; 1303 k->exit = hda_codec_dev_exit; 1304 set_bit(DEVICE_CATEGORY_SOUND, k->categories); 1305 k->bus_type = TYPE_HDA_BUS; 1306 k->props = hda_props; 1307 } 1308 1309 static const TypeInfo hda_codec_device_type_info = { 1310 .name = TYPE_HDA_CODEC_DEVICE, 1311 .parent = TYPE_DEVICE, 1312 .instance_size = sizeof(HDACodecDevice), 1313 .abstract = true, 1314 .class_size = sizeof(HDACodecDeviceClass), 1315 .class_init = hda_codec_device_class_init, 1316 }; 1317 1318 /* 1319 * create intel hda controller with codec attached to it, 1320 * so '-soundhw hda' works. 1321 */ 1322 static int intel_hda_and_codec_init(PCIBus *bus) 1323 { 1324 DeviceState *controller; 1325 BusState *hdabus; 1326 DeviceState *codec; 1327 1328 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); 1329 hdabus = QLIST_FIRST(&controller->child_bus); 1330 codec = qdev_create(hdabus, "hda-duplex"); 1331 qdev_init_nofail(codec); 1332 return 0; 1333 } 1334 1335 static void intel_hda_register_types(void) 1336 { 1337 type_register_static(&hda_codec_bus_info); 1338 type_register_static(&intel_hda_info); 1339 type_register_static(&intel_hda_info_ich6); 1340 type_register_static(&intel_hda_info_ich9); 1341 type_register_static(&hda_codec_device_type_info); 1342 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init); 1343 } 1344 1345 type_init(intel_hda_register_types) 1346