1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Gerd Hoffmann <kraxel@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/pci/pci.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/pci/msi.h" 24 #include "qemu/timer.h" 25 #include "qemu/bitops.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "qemu/error-report.h" 29 #include "hw/audio/soundhw.h" 30 #include "intel-hda.h" 31 #include "migration/vmstate.h" 32 #include "intel-hda-defs.h" 33 #include "sysemu/dma.h" 34 #include "qapi/error.h" 35 #include "qom/object.h" 36 37 /* --------------------------------------------------------------------- */ 38 /* hda bus */ 39 40 static Property hda_props[] = { 41 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), 42 DEFINE_PROP_END_OF_LIST() 43 }; 44 45 static const TypeInfo hda_codec_bus_info = { 46 .name = TYPE_HDA_BUS, 47 .parent = TYPE_BUS, 48 .instance_size = sizeof(HDACodecBus), 49 }; 50 51 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, 52 hda_codec_response_func response, 53 hda_codec_xfer_func xfer) 54 { 55 qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL); 56 bus->response = response; 57 bus->xfer = xfer; 58 } 59 60 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp) 61 { 62 HDACodecBus *bus = HDA_BUS(qdev->parent_bus); 63 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 64 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 65 66 if (dev->cad == -1) { 67 dev->cad = bus->next_cad; 68 } 69 if (dev->cad >= 15) { 70 error_setg(errp, "HDA audio codec address is full"); 71 return; 72 } 73 bus->next_cad = dev->cad + 1; 74 cdc->init(dev, errp); 75 } 76 77 static void hda_codec_dev_unrealize(DeviceState *qdev) 78 { 79 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 80 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 81 82 if (cdc->exit) { 83 cdc->exit(dev); 84 } 85 } 86 87 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) 88 { 89 BusChild *kid; 90 HDACodecDevice *cdev; 91 92 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { 93 DeviceState *qdev = kid->child; 94 cdev = HDA_CODEC_DEVICE(qdev); 95 if (cdev->cad == cad) { 96 return cdev; 97 } 98 } 99 return NULL; 100 } 101 102 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) 103 { 104 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 105 bus->response(dev, solicited, response); 106 } 107 108 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 109 uint8_t *buf, uint32_t len) 110 { 111 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 112 return bus->xfer(dev, stnr, output, buf, len); 113 } 114 115 /* --------------------------------------------------------------------- */ 116 /* intel hda emulation */ 117 118 typedef struct IntelHDAStream IntelHDAStream; 119 typedef struct IntelHDAState IntelHDAState; 120 typedef struct IntelHDAReg IntelHDAReg; 121 122 typedef struct bpl { 123 uint64_t addr; 124 uint32_t len; 125 uint32_t flags; 126 } bpl; 127 128 struct IntelHDAStream { 129 /* registers */ 130 uint32_t ctl; 131 uint32_t lpib; 132 uint32_t cbl; 133 uint32_t lvi; 134 uint32_t fmt; 135 uint32_t bdlp_lbase; 136 uint32_t bdlp_ubase; 137 138 /* state */ 139 bpl *bpl; 140 uint32_t bentries; 141 uint32_t bsize, be, bp; 142 }; 143 144 struct IntelHDAState { 145 PCIDevice pci; 146 const char *name; 147 HDACodecBus codecs; 148 149 /* registers */ 150 uint32_t g_ctl; 151 uint32_t wake_en; 152 uint32_t state_sts; 153 uint32_t int_ctl; 154 uint32_t int_sts; 155 uint32_t wall_clk; 156 157 uint32_t corb_lbase; 158 uint32_t corb_ubase; 159 uint32_t corb_rp; 160 uint32_t corb_wp; 161 uint32_t corb_ctl; 162 uint32_t corb_sts; 163 uint32_t corb_size; 164 165 uint32_t rirb_lbase; 166 uint32_t rirb_ubase; 167 uint32_t rirb_wp; 168 uint32_t rirb_cnt; 169 uint32_t rirb_ctl; 170 uint32_t rirb_sts; 171 uint32_t rirb_size; 172 173 uint32_t dp_lbase; 174 uint32_t dp_ubase; 175 176 uint32_t icw; 177 uint32_t irr; 178 uint32_t ics; 179 180 /* streams */ 181 IntelHDAStream st[8]; 182 183 /* state */ 184 MemoryRegion container; 185 MemoryRegion mmio; 186 MemoryRegion alias; 187 uint32_t rirb_count; 188 int64_t wall_base_ns; 189 190 /* debug logging */ 191 const IntelHDAReg *last_reg; 192 uint32_t last_val; 193 uint32_t last_write; 194 uint32_t last_sec; 195 uint32_t repeat_count; 196 197 /* properties */ 198 uint32_t debug; 199 OnOffAuto msi; 200 bool old_msi_addr; 201 }; 202 203 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic" 204 205 DECLARE_INSTANCE_CHECKER(IntelHDAState, INTEL_HDA, 206 TYPE_INTEL_HDA_GENERIC) 207 208 struct IntelHDAReg { 209 const char *name; /* register name */ 210 uint32_t size; /* size in bytes */ 211 uint32_t reset; /* reset value */ 212 uint32_t wmask; /* write mask */ 213 uint32_t wclear; /* write 1 to clear bits */ 214 uint32_t offset; /* location in IntelHDAState */ 215 uint32_t shift; /* byte access entries for dwords */ 216 uint32_t stream; 217 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); 218 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); 219 }; 220 221 /* --------------------------------------------------------------------- */ 222 223 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) 224 { 225 return ((uint64_t)ubase << 32) | lbase; 226 } 227 228 static void intel_hda_update_int_sts(IntelHDAState *d) 229 { 230 uint32_t sts = 0; 231 uint32_t i; 232 233 /* update controller status */ 234 if (d->rirb_sts & ICH6_RBSTS_IRQ) { 235 sts |= (1 << 30); 236 } 237 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { 238 sts |= (1 << 30); 239 } 240 if (d->state_sts & d->wake_en) { 241 sts |= (1 << 30); 242 } 243 244 /* update stream status */ 245 for (i = 0; i < 8; i++) { 246 /* buffer completion interrupt */ 247 if (d->st[i].ctl & (1 << 26)) { 248 sts |= (1 << i); 249 } 250 } 251 252 /* update global status */ 253 if (sts & d->int_ctl) { 254 sts |= (1U << 31); 255 } 256 257 d->int_sts = sts; 258 } 259 260 static void intel_hda_update_irq(IntelHDAState *d) 261 { 262 bool msi = msi_enabled(&d->pci); 263 int level; 264 265 intel_hda_update_int_sts(d); 266 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { 267 level = 1; 268 } else { 269 level = 0; 270 } 271 dprint(d, 2, "%s: level %d [%s]\n", __func__, 272 level, msi ? "msi" : "intx"); 273 if (msi) { 274 if (level) { 275 msi_notify(&d->pci, 0); 276 } 277 } else { 278 pci_set_irq(&d->pci, level); 279 } 280 } 281 282 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) 283 { 284 uint32_t cad, nid, data; 285 HDACodecDevice *codec; 286 HDACodecDeviceClass *cdc; 287 288 cad = (verb >> 28) & 0x0f; 289 if (verb & (1 << 27)) { 290 /* indirect node addressing, not specified in HDA 1.0 */ 291 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__); 292 return -1; 293 } 294 nid = (verb >> 20) & 0x7f; 295 data = verb & 0xfffff; 296 297 codec = hda_codec_find(&d->codecs, cad); 298 if (codec == NULL) { 299 dprint(d, 1, "%s: addressed non-existing codec\n", __func__); 300 return -1; 301 } 302 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec); 303 cdc->command(codec, nid, data); 304 return 0; 305 } 306 307 static void intel_hda_corb_run(IntelHDAState *d) 308 { 309 hwaddr addr; 310 uint32_t rp, verb; 311 312 if (d->ics & ICH6_IRS_BUSY) { 313 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw); 314 intel_hda_send_command(d, d->icw); 315 return; 316 } 317 318 for (;;) { 319 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { 320 dprint(d, 2, "%s: !run\n", __func__); 321 return; 322 } 323 if ((d->corb_rp & 0xff) == d->corb_wp) { 324 dprint(d, 2, "%s: corb ring empty\n", __func__); 325 return; 326 } 327 if (d->rirb_count == d->rirb_cnt) { 328 dprint(d, 2, "%s: rirb count reached\n", __func__); 329 return; 330 } 331 332 rp = (d->corb_rp + 1) & 0xff; 333 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); 334 ldl_le_pci_dma(&d->pci, addr + 4 * rp, &verb, MEMTXATTRS_UNSPECIFIED); 335 d->corb_rp = rp; 336 337 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); 338 intel_hda_send_command(d, verb); 339 } 340 } 341 342 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) 343 { 344 const MemTxAttrs attrs = { .memory = true }; 345 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 346 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 347 hwaddr addr; 348 uint32_t wp, ex; 349 MemTxResult res = MEMTX_OK; 350 351 if (d->ics & ICH6_IRS_BUSY) { 352 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", 353 __func__, response, dev->cad); 354 d->irr = response; 355 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); 356 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); 357 return; 358 } 359 360 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { 361 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__); 362 return; 363 } 364 365 ex = (solicited ? 0 : (1 << 4)) | dev->cad; 366 wp = (d->rirb_wp + 1) & 0xff; 367 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); 368 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs); 369 res |= stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs); 370 if (res != MEMTX_OK && (d->rirb_ctl & ICH6_RBCTL_OVERRUN_EN)) { 371 d->rirb_sts |= ICH6_RBSTS_OVERRUN; 372 intel_hda_update_irq(d); 373 } 374 d->rirb_wp = wp; 375 376 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", 377 __func__, wp, response, ex); 378 379 d->rirb_count++; 380 if (d->rirb_count == d->rirb_cnt) { 381 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count); 382 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 383 d->rirb_sts |= ICH6_RBSTS_IRQ; 384 intel_hda_update_irq(d); 385 } 386 } else if ((d->corb_rp & 0xff) == d->corb_wp) { 387 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__, 388 d->rirb_count, d->rirb_cnt); 389 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 390 d->rirb_sts |= ICH6_RBSTS_IRQ; 391 intel_hda_update_irq(d); 392 } 393 } 394 } 395 396 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 397 uint8_t *buf, uint32_t len) 398 { 399 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 400 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 401 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 402 hwaddr addr; 403 uint32_t s, copy, left; 404 IntelHDAStream *st; 405 bool irq = false; 406 407 st = output ? d->st + 4 : d->st; 408 for (s = 0; s < 4; s++) { 409 if (stnr == ((st[s].ctl >> 20) & 0x0f)) { 410 st = st + s; 411 break; 412 } 413 } 414 if (s == 4) { 415 return false; 416 } 417 if (st->bpl == NULL) { 418 return false; 419 } 420 421 left = len; 422 s = st->bentries; 423 while (left > 0 && s-- > 0) { 424 copy = left; 425 if (copy > st->bsize - st->lpib) 426 copy = st->bsize - st->lpib; 427 if (copy > st->bpl[st->be].len - st->bp) 428 copy = st->bpl[st->be].len - st->bp; 429 430 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", 431 st->be, st->bp, st->bpl[st->be].len, copy); 432 433 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output, 434 attrs); 435 st->lpib += copy; 436 st->bp += copy; 437 buf += copy; 438 left -= copy; 439 440 if (st->bpl[st->be].len == st->bp) { 441 /* bpl entry filled */ 442 if (st->bpl[st->be].flags & 0x01) { 443 irq = true; 444 } 445 st->bp = 0; 446 st->be++; 447 if (st->be == st->bentries) { 448 /* bpl wrap around */ 449 st->be = 0; 450 st->lpib = 0; 451 } 452 } 453 } 454 if (d->dp_lbase & 0x01) { 455 s = st - d->st; 456 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); 457 stl_le_pci_dma(&d->pci, addr + 8 * s, st->lpib, attrs); 458 } 459 dprint(d, 3, "dma: --\n"); 460 461 if (irq) { 462 st->ctl |= (1 << 26); /* buffer completion interrupt */ 463 intel_hda_update_irq(d); 464 } 465 return true; 466 } 467 468 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) 469 { 470 hwaddr addr; 471 uint8_t buf[16]; 472 uint32_t i; 473 474 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); 475 st->bentries = st->lvi +1; 476 g_free(st->bpl); 477 st->bpl = g_new(bpl, st->bentries); 478 for (i = 0; i < st->bentries; i++, addr += 16) { 479 pci_dma_read(&d->pci, addr, buf, 16); 480 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); 481 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); 482 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); 483 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", 484 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); 485 } 486 487 st->bsize = st->cbl; 488 st->lpib = 0; 489 st->be = 0; 490 st->bp = 0; 491 } 492 493 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) 494 { 495 BusChild *kid; 496 HDACodecDevice *cdev; 497 498 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 499 DeviceState *qdev = kid->child; 500 HDACodecDeviceClass *cdc; 501 502 cdev = HDA_CODEC_DEVICE(qdev); 503 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev); 504 if (cdc->stream) { 505 cdc->stream(cdev, stream, running, output); 506 } 507 } 508 } 509 510 /* --------------------------------------------------------------------- */ 511 512 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 513 { 514 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { 515 device_cold_reset(DEVICE(d)); 516 } 517 } 518 519 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 520 { 521 intel_hda_update_irq(d); 522 } 523 524 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 525 { 526 intel_hda_update_irq(d); 527 } 528 529 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 530 { 531 intel_hda_update_irq(d); 532 } 533 534 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) 535 { 536 int64_t ns; 537 538 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; 539 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ 540 } 541 542 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 543 { 544 intel_hda_corb_run(d); 545 } 546 547 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 548 { 549 intel_hda_corb_run(d); 550 } 551 552 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 553 { 554 if (d->rirb_wp & ICH6_RIRBWP_RST) { 555 d->rirb_wp = 0; 556 } 557 } 558 559 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 560 { 561 intel_hda_update_irq(d); 562 563 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { 564 /* cleared ICH6_RBSTS_IRQ */ 565 d->rirb_count = 0; 566 intel_hda_corb_run(d); 567 } 568 } 569 570 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 571 { 572 if (d->ics & ICH6_IRS_BUSY) { 573 intel_hda_corb_run(d); 574 } 575 } 576 577 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 578 { 579 bool output = reg->stream >= 4; 580 IntelHDAStream *st = d->st + reg->stream; 581 582 if (st->ctl & 0x01) { 583 /* reset */ 584 dprint(d, 1, "st #%d: reset\n", reg->stream); 585 st->ctl = SD_STS_FIFO_READY << 24 | SD_CTL_STREAM_RESET; 586 } 587 if ((st->ctl & 0x02) != (old & 0x02)) { 588 uint32_t stnr = (st->ctl >> 20) & 0x0f; 589 /* run bit flipped */ 590 if (st->ctl & 0x02) { 591 /* start */ 592 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", 593 reg->stream, stnr, st->cbl); 594 intel_hda_parse_bdl(d, st); 595 intel_hda_notify_codecs(d, stnr, true, output); 596 } else { 597 /* stop */ 598 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); 599 intel_hda_notify_codecs(d, stnr, false, output); 600 } 601 } 602 intel_hda_update_irq(d); 603 } 604 605 /* --------------------------------------------------------------------- */ 606 607 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) 608 609 static const struct IntelHDAReg regtab[] = { 610 /* global */ 611 [ ICH6_REG_GCAP ] = { 612 .name = "GCAP", 613 .size = 2, 614 .reset = 0x4401, 615 }, 616 [ ICH6_REG_VMIN ] = { 617 .name = "VMIN", 618 .size = 1, 619 }, 620 [ ICH6_REG_VMAJ ] = { 621 .name = "VMAJ", 622 .size = 1, 623 .reset = 1, 624 }, 625 [ ICH6_REG_OUTPAY ] = { 626 .name = "OUTPAY", 627 .size = 2, 628 .reset = 0x3c, 629 }, 630 [ ICH6_REG_INPAY ] = { 631 .name = "INPAY", 632 .size = 2, 633 .reset = 0x1d, 634 }, 635 [ ICH6_REG_GCTL ] = { 636 .name = "GCTL", 637 .size = 4, 638 .wmask = 0x0103, 639 .offset = offsetof(IntelHDAState, g_ctl), 640 .whandler = intel_hda_set_g_ctl, 641 }, 642 [ ICH6_REG_WAKEEN ] = { 643 .name = "WAKEEN", 644 .size = 2, 645 .wmask = 0x7fff, 646 .offset = offsetof(IntelHDAState, wake_en), 647 .whandler = intel_hda_set_wake_en, 648 }, 649 [ ICH6_REG_STATESTS ] = { 650 .name = "STATESTS", 651 .size = 2, 652 .wmask = 0x7fff, 653 .wclear = 0x7fff, 654 .offset = offsetof(IntelHDAState, state_sts), 655 .whandler = intel_hda_set_state_sts, 656 }, 657 658 /* interrupts */ 659 [ ICH6_REG_INTCTL ] = { 660 .name = "INTCTL", 661 .size = 4, 662 .wmask = 0xc00000ff, 663 .offset = offsetof(IntelHDAState, int_ctl), 664 .whandler = intel_hda_set_int_ctl, 665 }, 666 [ ICH6_REG_INTSTS ] = { 667 .name = "INTSTS", 668 .size = 4, 669 .wmask = 0xc00000ff, 670 .wclear = 0xc00000ff, 671 .offset = offsetof(IntelHDAState, int_sts), 672 }, 673 674 /* misc */ 675 [ ICH6_REG_WALLCLK ] = { 676 .name = "WALLCLK", 677 .size = 4, 678 .offset = offsetof(IntelHDAState, wall_clk), 679 .rhandler = intel_hda_get_wall_clk, 680 }, 681 682 /* dma engine */ 683 [ ICH6_REG_CORBLBASE ] = { 684 .name = "CORBLBASE", 685 .size = 4, 686 .wmask = 0xffffff80, 687 .offset = offsetof(IntelHDAState, corb_lbase), 688 }, 689 [ ICH6_REG_CORBUBASE ] = { 690 .name = "CORBUBASE", 691 .size = 4, 692 .wmask = 0xffffffff, 693 .offset = offsetof(IntelHDAState, corb_ubase), 694 }, 695 [ ICH6_REG_CORBWP ] = { 696 .name = "CORBWP", 697 .size = 2, 698 .wmask = 0xff, 699 .offset = offsetof(IntelHDAState, corb_wp), 700 .whandler = intel_hda_set_corb_wp, 701 }, 702 [ ICH6_REG_CORBRP ] = { 703 .name = "CORBRP", 704 .size = 2, 705 .wmask = 0x80ff, 706 .offset = offsetof(IntelHDAState, corb_rp), 707 }, 708 [ ICH6_REG_CORBCTL ] = { 709 .name = "CORBCTL", 710 .size = 1, 711 .wmask = 0x03, 712 .offset = offsetof(IntelHDAState, corb_ctl), 713 .whandler = intel_hda_set_corb_ctl, 714 }, 715 [ ICH6_REG_CORBSTS ] = { 716 .name = "CORBSTS", 717 .size = 1, 718 .wmask = 0x01, 719 .wclear = 0x01, 720 .offset = offsetof(IntelHDAState, corb_sts), 721 }, 722 [ ICH6_REG_CORBSIZE ] = { 723 .name = "CORBSIZE", 724 .size = 1, 725 .reset = 0x42, 726 .offset = offsetof(IntelHDAState, corb_size), 727 }, 728 [ ICH6_REG_RIRBLBASE ] = { 729 .name = "RIRBLBASE", 730 .size = 4, 731 .wmask = 0xffffff80, 732 .offset = offsetof(IntelHDAState, rirb_lbase), 733 }, 734 [ ICH6_REG_RIRBUBASE ] = { 735 .name = "RIRBUBASE", 736 .size = 4, 737 .wmask = 0xffffffff, 738 .offset = offsetof(IntelHDAState, rirb_ubase), 739 }, 740 [ ICH6_REG_RIRBWP ] = { 741 .name = "RIRBWP", 742 .size = 2, 743 .wmask = 0x8000, 744 .offset = offsetof(IntelHDAState, rirb_wp), 745 .whandler = intel_hda_set_rirb_wp, 746 }, 747 [ ICH6_REG_RINTCNT ] = { 748 .name = "RINTCNT", 749 .size = 2, 750 .wmask = 0xff, 751 .offset = offsetof(IntelHDAState, rirb_cnt), 752 }, 753 [ ICH6_REG_RIRBCTL ] = { 754 .name = "RIRBCTL", 755 .size = 1, 756 .wmask = 0x07, 757 .offset = offsetof(IntelHDAState, rirb_ctl), 758 }, 759 [ ICH6_REG_RIRBSTS ] = { 760 .name = "RIRBSTS", 761 .size = 1, 762 .wmask = 0x05, 763 .wclear = 0x05, 764 .offset = offsetof(IntelHDAState, rirb_sts), 765 .whandler = intel_hda_set_rirb_sts, 766 }, 767 [ ICH6_REG_RIRBSIZE ] = { 768 .name = "RIRBSIZE", 769 .size = 1, 770 .reset = 0x42, 771 .offset = offsetof(IntelHDAState, rirb_size), 772 }, 773 774 [ ICH6_REG_DPLBASE ] = { 775 .name = "DPLBASE", 776 .size = 4, 777 .wmask = 0xffffff81, 778 .offset = offsetof(IntelHDAState, dp_lbase), 779 }, 780 [ ICH6_REG_DPUBASE ] = { 781 .name = "DPUBASE", 782 .size = 4, 783 .wmask = 0xffffffff, 784 .offset = offsetof(IntelHDAState, dp_ubase), 785 }, 786 787 [ ICH6_REG_IC ] = { 788 .name = "ICW", 789 .size = 4, 790 .wmask = 0xffffffff, 791 .offset = offsetof(IntelHDAState, icw), 792 }, 793 [ ICH6_REG_IR ] = { 794 .name = "IRR", 795 .size = 4, 796 .offset = offsetof(IntelHDAState, irr), 797 }, 798 [ ICH6_REG_IRS ] = { 799 .name = "ICS", 800 .size = 2, 801 .wmask = 0x0003, 802 .wclear = 0x0002, 803 .offset = offsetof(IntelHDAState, ics), 804 .whandler = intel_hda_set_ics, 805 }, 806 807 #define HDA_STREAM(_t, _i) \ 808 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ 809 .stream = _i, \ 810 .name = _t stringify(_i) " CTL", \ 811 .size = 4, \ 812 .wmask = 0x1cff001f, \ 813 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 814 .whandler = intel_hda_set_st_ctl, \ 815 }, \ 816 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ 817 .stream = _i, \ 818 .name = _t stringify(_i) " CTL(stnr)", \ 819 .size = 1, \ 820 .shift = 16, \ 821 .wmask = 0x00ff0000, \ 822 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 823 .whandler = intel_hda_set_st_ctl, \ 824 }, \ 825 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ 826 .stream = _i, \ 827 .name = _t stringify(_i) " CTL(sts)", \ 828 .size = 1, \ 829 .shift = 24, \ 830 .wmask = 0x1c000000, \ 831 .wclear = 0x1c000000, \ 832 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 833 .whandler = intel_hda_set_st_ctl, \ 834 .reset = SD_STS_FIFO_READY << 24 \ 835 }, \ 836 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ 837 .stream = _i, \ 838 .name = _t stringify(_i) " LPIB", \ 839 .size = 4, \ 840 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 841 }, \ 842 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ 843 .stream = _i, \ 844 .name = _t stringify(_i) " CBL", \ 845 .size = 4, \ 846 .wmask = 0xffffffff, \ 847 .offset = offsetof(IntelHDAState, st[_i].cbl), \ 848 }, \ 849 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ 850 .stream = _i, \ 851 .name = _t stringify(_i) " LVI", \ 852 .size = 2, \ 853 .wmask = 0x00ff, \ 854 .offset = offsetof(IntelHDAState, st[_i].lvi), \ 855 }, \ 856 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ 857 .stream = _i, \ 858 .name = _t stringify(_i) " FIFOS", \ 859 .size = 2, \ 860 .reset = HDA_BUFFER_SIZE, \ 861 }, \ 862 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ 863 .stream = _i, \ 864 .name = _t stringify(_i) " FMT", \ 865 .size = 2, \ 866 .wmask = 0x7f7f, \ 867 .offset = offsetof(IntelHDAState, st[_i].fmt), \ 868 }, \ 869 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ 870 .stream = _i, \ 871 .name = _t stringify(_i) " BDLPL", \ 872 .size = 4, \ 873 .wmask = 0xffffff80, \ 874 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ 875 }, \ 876 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ 877 .stream = _i, \ 878 .name = _t stringify(_i) " BDLPU", \ 879 .size = 4, \ 880 .wmask = 0xffffffff, \ 881 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ 882 }, \ 883 884 HDA_STREAM("IN", 0) 885 HDA_STREAM("IN", 1) 886 HDA_STREAM("IN", 2) 887 HDA_STREAM("IN", 3) 888 889 HDA_STREAM("OUT", 4) 890 HDA_STREAM("OUT", 5) 891 HDA_STREAM("OUT", 6) 892 HDA_STREAM("OUT", 7) 893 894 }; 895 896 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) 897 { 898 const IntelHDAReg *reg; 899 900 if (addr >= ARRAY_SIZE(regtab)) { 901 goto noreg; 902 } 903 reg = regtab+addr; 904 if (reg->name == NULL) { 905 goto noreg; 906 } 907 return reg; 908 909 noreg: 910 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); 911 return NULL; 912 } 913 914 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) 915 { 916 uint8_t *addr = (void*)d; 917 918 addr += reg->offset; 919 return (uint32_t*)addr; 920 } 921 922 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, 923 uint32_t wmask) 924 { 925 uint32_t *addr; 926 uint32_t old; 927 928 if (!reg) { 929 return; 930 } 931 if (!reg->wmask) { 932 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n", 933 reg->name); 934 return; 935 } 936 937 if (d->debug) { 938 time_t now = time(NULL); 939 if (d->last_write && d->last_reg == reg && d->last_val == val) { 940 d->repeat_count++; 941 if (d->last_sec != now) { 942 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 943 d->last_sec = now; 944 d->repeat_count = 0; 945 } 946 } else { 947 if (d->repeat_count) { 948 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 949 } 950 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); 951 d->last_write = 1; 952 d->last_reg = reg; 953 d->last_val = val; 954 d->last_sec = now; 955 d->repeat_count = 0; 956 } 957 } 958 assert(reg->offset != 0); 959 960 addr = intel_hda_reg_addr(d, reg); 961 old = *addr; 962 963 if (reg->shift) { 964 val <<= reg->shift; 965 wmask <<= reg->shift; 966 } 967 wmask &= reg->wmask; 968 *addr &= ~wmask; 969 *addr |= wmask & val; 970 *addr &= ~(val & reg->wclear); 971 972 if (reg->whandler) { 973 reg->whandler(d, reg, old); 974 } 975 } 976 977 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, 978 uint32_t rmask) 979 { 980 uint32_t *addr, ret; 981 982 if (!reg) { 983 return 0; 984 } 985 986 if (reg->rhandler) { 987 reg->rhandler(d, reg); 988 } 989 990 if (reg->offset == 0) { 991 /* constant read-only register */ 992 ret = reg->reset; 993 } else { 994 addr = intel_hda_reg_addr(d, reg); 995 ret = *addr; 996 if (reg->shift) { 997 ret >>= reg->shift; 998 } 999 ret &= rmask; 1000 } 1001 if (d->debug) { 1002 time_t now = time(NULL); 1003 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { 1004 d->repeat_count++; 1005 if (d->last_sec != now) { 1006 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1007 d->last_sec = now; 1008 d->repeat_count = 0; 1009 } 1010 } else { 1011 if (d->repeat_count) { 1012 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1013 } 1014 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); 1015 d->last_write = 0; 1016 d->last_reg = reg; 1017 d->last_val = ret; 1018 d->last_sec = now; 1019 d->repeat_count = 0; 1020 } 1021 } 1022 return ret; 1023 } 1024 1025 static void intel_hda_regs_reset(IntelHDAState *d) 1026 { 1027 uint32_t *addr; 1028 int i; 1029 1030 for (i = 0; i < ARRAY_SIZE(regtab); i++) { 1031 if (regtab[i].name == NULL) { 1032 continue; 1033 } 1034 if (regtab[i].offset == 0) { 1035 continue; 1036 } 1037 addr = intel_hda_reg_addr(d, regtab + i); 1038 *addr = regtab[i].reset; 1039 } 1040 } 1041 1042 /* --------------------------------------------------------------------- */ 1043 1044 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val, 1045 unsigned size) 1046 { 1047 IntelHDAState *d = opaque; 1048 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1049 1050 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8)); 1051 } 1052 1053 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size) 1054 { 1055 IntelHDAState *d = opaque; 1056 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1057 1058 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8)); 1059 } 1060 1061 static const MemoryRegionOps intel_hda_mmio_ops = { 1062 .read = intel_hda_mmio_read, 1063 .write = intel_hda_mmio_write, 1064 .impl = { 1065 .min_access_size = 1, 1066 .max_access_size = 4, 1067 }, 1068 .endianness = DEVICE_NATIVE_ENDIAN, 1069 }; 1070 1071 /* --------------------------------------------------------------------- */ 1072 1073 static void intel_hda_reset(DeviceState *dev) 1074 { 1075 BusChild *kid; 1076 IntelHDAState *d = INTEL_HDA(dev); 1077 HDACodecDevice *cdev; 1078 1079 intel_hda_regs_reset(d); 1080 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1081 1082 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 1083 DeviceState *qdev = kid->child; 1084 cdev = HDA_CODEC_DEVICE(qdev); 1085 d->state_sts |= (1 << cdev->cad); 1086 } 1087 intel_hda_update_irq(d); 1088 } 1089 1090 static void intel_hda_realize(PCIDevice *pci, Error **errp) 1091 { 1092 IntelHDAState *d = INTEL_HDA(pci); 1093 uint8_t *conf = d->pci.config; 1094 Error *err = NULL; 1095 int ret; 1096 1097 d->name = object_get_typename(OBJECT(d)); 1098 1099 pci_config_set_interrupt_pin(conf, 1); 1100 1101 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ 1102 conf[0x40] = 0x01; 1103 1104 if (d->msi != ON_OFF_AUTO_OFF) { 1105 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1106 1, true, false, &err); 1107 /* Any error other than -ENOTSUP(board's MSI support is broken) 1108 * is a programming error */ 1109 assert(!ret || ret == -ENOTSUP); 1110 if (ret && d->msi == ON_OFF_AUTO_ON) { 1111 /* Can't satisfy user's explicit msi=on request, fail */ 1112 error_append_hint(&err, "You have to use msi=auto (default) or " 1113 "msi=off with this machine type.\n"); 1114 error_propagate(errp, err); 1115 return; 1116 } 1117 assert(!err || d->msi == ON_OFF_AUTO_AUTO); 1118 /* With msi=auto, we fall back to MSI off silently */ 1119 error_free(err); 1120 } 1121 1122 memory_region_init(&d->container, OBJECT(d), 1123 "intel-hda-container", 0x4000); 1124 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, 1125 "intel-hda", 0x2000); 1126 memory_region_add_subregion(&d->container, 0x0000, &d->mmio); 1127 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias", 1128 &d->mmio, 0, 0x2000); 1129 memory_region_add_subregion(&d->container, 0x2000, &d->alias); 1130 pci_register_bar(&d->pci, 0, 0, &d->container); 1131 1132 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), 1133 intel_hda_response, intel_hda_xfer); 1134 } 1135 1136 static void intel_hda_exit(PCIDevice *pci) 1137 { 1138 IntelHDAState *d = INTEL_HDA(pci); 1139 1140 msi_uninit(&d->pci); 1141 } 1142 1143 static int intel_hda_post_load(void *opaque, int version) 1144 { 1145 IntelHDAState* d = opaque; 1146 int i; 1147 1148 dprint(d, 1, "%s\n", __func__); 1149 for (i = 0; i < ARRAY_SIZE(d->st); i++) { 1150 if (d->st[i].ctl & 0x02) { 1151 intel_hda_parse_bdl(d, &d->st[i]); 1152 } 1153 } 1154 intel_hda_update_irq(d); 1155 return 0; 1156 } 1157 1158 static const VMStateDescription vmstate_intel_hda_stream = { 1159 .name = "intel-hda-stream", 1160 .version_id = 1, 1161 .fields = (const VMStateField[]) { 1162 VMSTATE_UINT32(ctl, IntelHDAStream), 1163 VMSTATE_UINT32(lpib, IntelHDAStream), 1164 VMSTATE_UINT32(cbl, IntelHDAStream), 1165 VMSTATE_UINT32(lvi, IntelHDAStream), 1166 VMSTATE_UINT32(fmt, IntelHDAStream), 1167 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), 1168 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), 1169 VMSTATE_END_OF_LIST() 1170 } 1171 }; 1172 1173 static const VMStateDescription vmstate_intel_hda = { 1174 .name = "intel-hda", 1175 .version_id = 1, 1176 .post_load = intel_hda_post_load, 1177 .fields = (const VMStateField[]) { 1178 VMSTATE_PCI_DEVICE(pci, IntelHDAState), 1179 1180 /* registers */ 1181 VMSTATE_UINT32(g_ctl, IntelHDAState), 1182 VMSTATE_UINT32(wake_en, IntelHDAState), 1183 VMSTATE_UINT32(state_sts, IntelHDAState), 1184 VMSTATE_UINT32(int_ctl, IntelHDAState), 1185 VMSTATE_UINT32(int_sts, IntelHDAState), 1186 VMSTATE_UINT32(wall_clk, IntelHDAState), 1187 VMSTATE_UINT32(corb_lbase, IntelHDAState), 1188 VMSTATE_UINT32(corb_ubase, IntelHDAState), 1189 VMSTATE_UINT32(corb_rp, IntelHDAState), 1190 VMSTATE_UINT32(corb_wp, IntelHDAState), 1191 VMSTATE_UINT32(corb_ctl, IntelHDAState), 1192 VMSTATE_UINT32(corb_sts, IntelHDAState), 1193 VMSTATE_UINT32(corb_size, IntelHDAState), 1194 VMSTATE_UINT32(rirb_lbase, IntelHDAState), 1195 VMSTATE_UINT32(rirb_ubase, IntelHDAState), 1196 VMSTATE_UINT32(rirb_wp, IntelHDAState), 1197 VMSTATE_UINT32(rirb_cnt, IntelHDAState), 1198 VMSTATE_UINT32(rirb_ctl, IntelHDAState), 1199 VMSTATE_UINT32(rirb_sts, IntelHDAState), 1200 VMSTATE_UINT32(rirb_size, IntelHDAState), 1201 VMSTATE_UINT32(dp_lbase, IntelHDAState), 1202 VMSTATE_UINT32(dp_ubase, IntelHDAState), 1203 VMSTATE_UINT32(icw, IntelHDAState), 1204 VMSTATE_UINT32(irr, IntelHDAState), 1205 VMSTATE_UINT32(ics, IntelHDAState), 1206 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, 1207 vmstate_intel_hda_stream, 1208 IntelHDAStream), 1209 1210 /* additional state info */ 1211 VMSTATE_UINT32(rirb_count, IntelHDAState), 1212 VMSTATE_INT64(wall_base_ns, IntelHDAState), 1213 1214 VMSTATE_END_OF_LIST() 1215 } 1216 }; 1217 1218 static Property intel_hda_properties[] = { 1219 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), 1220 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO), 1221 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false), 1222 DEFINE_PROP_END_OF_LIST(), 1223 }; 1224 1225 static void intel_hda_class_init(ObjectClass *klass, void *data) 1226 { 1227 DeviceClass *dc = DEVICE_CLASS(klass); 1228 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1229 1230 k->realize = intel_hda_realize; 1231 k->exit = intel_hda_exit; 1232 k->vendor_id = PCI_VENDOR_ID_INTEL; 1233 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; 1234 device_class_set_legacy_reset(dc, intel_hda_reset); 1235 dc->vmsd = &vmstate_intel_hda; 1236 device_class_set_props(dc, intel_hda_properties); 1237 } 1238 1239 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) 1240 { 1241 DeviceClass *dc = DEVICE_CLASS(klass); 1242 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1243 1244 k->device_id = 0x2668; 1245 k->revision = 1; 1246 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1247 dc->desc = "Intel HD Audio Controller (ich6)"; 1248 } 1249 1250 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data) 1251 { 1252 DeviceClass *dc = DEVICE_CLASS(klass); 1253 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1254 1255 k->device_id = 0x293e; 1256 k->revision = 3; 1257 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1258 dc->desc = "Intel HD Audio Controller (ich9)"; 1259 } 1260 1261 static const TypeInfo intel_hda_info = { 1262 .name = TYPE_INTEL_HDA_GENERIC, 1263 .parent = TYPE_PCI_DEVICE, 1264 .instance_size = sizeof(IntelHDAState), 1265 .class_init = intel_hda_class_init, 1266 .abstract = true, 1267 .interfaces = (InterfaceInfo[]) { 1268 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1269 { }, 1270 }, 1271 }; 1272 1273 static const TypeInfo intel_hda_info_ich6 = { 1274 .name = "intel-hda", 1275 .parent = TYPE_INTEL_HDA_GENERIC, 1276 .class_init = intel_hda_class_init_ich6, 1277 }; 1278 1279 static const TypeInfo intel_hda_info_ich9 = { 1280 .name = "ich9-intel-hda", 1281 .parent = TYPE_INTEL_HDA_GENERIC, 1282 .class_init = intel_hda_class_init_ich9, 1283 }; 1284 1285 static void hda_codec_device_class_init(ObjectClass *klass, void *data) 1286 { 1287 DeviceClass *k = DEVICE_CLASS(klass); 1288 k->realize = hda_codec_dev_realize; 1289 k->unrealize = hda_codec_dev_unrealize; 1290 set_bit(DEVICE_CATEGORY_SOUND, k->categories); 1291 k->bus_type = TYPE_HDA_BUS; 1292 device_class_set_props(k, hda_props); 1293 } 1294 1295 static const TypeInfo hda_codec_device_type_info = { 1296 .name = TYPE_HDA_CODEC_DEVICE, 1297 .parent = TYPE_DEVICE, 1298 .instance_size = sizeof(HDACodecDevice), 1299 .abstract = true, 1300 .class_size = sizeof(HDACodecDeviceClass), 1301 .class_init = hda_codec_device_class_init, 1302 }; 1303 1304 /* 1305 * create intel hda controller with codec attached to it, 1306 * so '-soundhw hda' works. 1307 */ 1308 static int intel_hda_and_codec_init(PCIBus *bus, const char *audiodev) 1309 { 1310 DeviceState *controller; 1311 BusState *hdabus; 1312 DeviceState *codec; 1313 1314 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); 1315 hdabus = QLIST_FIRST(&controller->child_bus); 1316 codec = qdev_new("hda-duplex"); 1317 qdev_prop_set_string(codec, "audiodev", audiodev); 1318 qdev_realize_and_unref(codec, hdabus, &error_fatal); 1319 return 0; 1320 } 1321 1322 static void intel_hda_register_types(void) 1323 { 1324 type_register_static(&hda_codec_bus_info); 1325 type_register_static(&intel_hda_info); 1326 type_register_static(&intel_hda_info_ich6); 1327 type_register_static(&intel_hda_info_ich9); 1328 type_register_static(&hda_codec_device_type_info); 1329 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init); 1330 } 1331 1332 type_init(intel_hda_register_types) 1333