1 /* 2 * Copyright (C) 2010 Red Hat, Inc. 3 * 4 * written by Gerd Hoffmann <kraxel@redhat.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/pci/pci.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/pci/msi.h" 24 #include "qemu/timer.h" 25 #include "qemu/bitops.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "qemu/error-report.h" 29 #include "hw/audio/soundhw.h" 30 #include "intel-hda.h" 31 #include "migration/vmstate.h" 32 #include "intel-hda-defs.h" 33 #include "sysemu/dma.h" 34 #include "qapi/error.h" 35 36 /* --------------------------------------------------------------------- */ 37 /* hda bus */ 38 39 static Property hda_props[] = { 40 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), 41 DEFINE_PROP_END_OF_LIST() 42 }; 43 44 static const TypeInfo hda_codec_bus_info = { 45 .name = TYPE_HDA_BUS, 46 .parent = TYPE_BUS, 47 .instance_size = sizeof(HDACodecBus), 48 }; 49 50 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, 51 hda_codec_response_func response, 52 hda_codec_xfer_func xfer) 53 { 54 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL); 55 bus->response = response; 56 bus->xfer = xfer; 57 } 58 59 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp) 60 { 61 HDACodecBus *bus = HDA_BUS(qdev->parent_bus); 62 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 63 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 64 65 if (dev->cad == -1) { 66 dev->cad = bus->next_cad; 67 } 68 if (dev->cad >= 15) { 69 error_setg(errp, "HDA audio codec address is full"); 70 return; 71 } 72 bus->next_cad = dev->cad + 1; 73 if (cdc->init(dev) != 0) { 74 error_setg(errp, "HDA audio init failed"); 75 } 76 } 77 78 static void hda_codec_dev_unrealize(DeviceState *qdev) 79 { 80 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev); 81 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev); 82 83 if (cdc->exit) { 84 cdc->exit(dev); 85 } 86 } 87 88 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) 89 { 90 BusChild *kid; 91 HDACodecDevice *cdev; 92 93 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) { 94 DeviceState *qdev = kid->child; 95 cdev = HDA_CODEC_DEVICE(qdev); 96 if (cdev->cad == cad) { 97 return cdev; 98 } 99 } 100 return NULL; 101 } 102 103 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) 104 { 105 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 106 bus->response(dev, solicited, response); 107 } 108 109 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 110 uint8_t *buf, uint32_t len) 111 { 112 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 113 return bus->xfer(dev, stnr, output, buf, len); 114 } 115 116 /* --------------------------------------------------------------------- */ 117 /* intel hda emulation */ 118 119 typedef struct IntelHDAStream IntelHDAStream; 120 typedef struct IntelHDAState IntelHDAState; 121 typedef struct IntelHDAReg IntelHDAReg; 122 123 typedef struct bpl { 124 uint64_t addr; 125 uint32_t len; 126 uint32_t flags; 127 } bpl; 128 129 struct IntelHDAStream { 130 /* registers */ 131 uint32_t ctl; 132 uint32_t lpib; 133 uint32_t cbl; 134 uint32_t lvi; 135 uint32_t fmt; 136 uint32_t bdlp_lbase; 137 uint32_t bdlp_ubase; 138 139 /* state */ 140 bpl *bpl; 141 uint32_t bentries; 142 uint32_t bsize, be, bp; 143 }; 144 145 struct IntelHDAState { 146 PCIDevice pci; 147 const char *name; 148 HDACodecBus codecs; 149 150 /* registers */ 151 uint32_t g_ctl; 152 uint32_t wake_en; 153 uint32_t state_sts; 154 uint32_t int_ctl; 155 uint32_t int_sts; 156 uint32_t wall_clk; 157 158 uint32_t corb_lbase; 159 uint32_t corb_ubase; 160 uint32_t corb_rp; 161 uint32_t corb_wp; 162 uint32_t corb_ctl; 163 uint32_t corb_sts; 164 uint32_t corb_size; 165 166 uint32_t rirb_lbase; 167 uint32_t rirb_ubase; 168 uint32_t rirb_wp; 169 uint32_t rirb_cnt; 170 uint32_t rirb_ctl; 171 uint32_t rirb_sts; 172 uint32_t rirb_size; 173 174 uint32_t dp_lbase; 175 uint32_t dp_ubase; 176 177 uint32_t icw; 178 uint32_t irr; 179 uint32_t ics; 180 181 /* streams */ 182 IntelHDAStream st[8]; 183 184 /* state */ 185 MemoryRegion container; 186 MemoryRegion mmio; 187 MemoryRegion alias; 188 uint32_t rirb_count; 189 int64_t wall_base_ns; 190 191 /* debug logging */ 192 const IntelHDAReg *last_reg; 193 uint32_t last_val; 194 uint32_t last_write; 195 uint32_t last_sec; 196 uint32_t repeat_count; 197 198 /* properties */ 199 uint32_t debug; 200 OnOffAuto msi; 201 bool old_msi_addr; 202 }; 203 204 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic" 205 206 #define INTEL_HDA(obj) \ 207 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC) 208 209 struct IntelHDAReg { 210 const char *name; /* register name */ 211 uint32_t size; /* size in bytes */ 212 uint32_t reset; /* reset value */ 213 uint32_t wmask; /* write mask */ 214 uint32_t wclear; /* write 1 to clear bits */ 215 uint32_t offset; /* location in IntelHDAState */ 216 uint32_t shift; /* byte access entries for dwords */ 217 uint32_t stream; 218 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); 219 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); 220 }; 221 222 static void intel_hda_reset(DeviceState *dev); 223 224 /* --------------------------------------------------------------------- */ 225 226 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase) 227 { 228 return ((uint64_t)ubase << 32) | lbase; 229 } 230 231 static void intel_hda_update_int_sts(IntelHDAState *d) 232 { 233 uint32_t sts = 0; 234 uint32_t i; 235 236 /* update controller status */ 237 if (d->rirb_sts & ICH6_RBSTS_IRQ) { 238 sts |= (1 << 30); 239 } 240 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) { 241 sts |= (1 << 30); 242 } 243 if (d->state_sts & d->wake_en) { 244 sts |= (1 << 30); 245 } 246 247 /* update stream status */ 248 for (i = 0; i < 8; i++) { 249 /* buffer completion interrupt */ 250 if (d->st[i].ctl & (1 << 26)) { 251 sts |= (1 << i); 252 } 253 } 254 255 /* update global status */ 256 if (sts & d->int_ctl) { 257 sts |= (1U << 31); 258 } 259 260 d->int_sts = sts; 261 } 262 263 static void intel_hda_update_irq(IntelHDAState *d) 264 { 265 bool msi = msi_enabled(&d->pci); 266 int level; 267 268 intel_hda_update_int_sts(d); 269 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) { 270 level = 1; 271 } else { 272 level = 0; 273 } 274 dprint(d, 2, "%s: level %d [%s]\n", __func__, 275 level, msi ? "msi" : "intx"); 276 if (msi) { 277 if (level) { 278 msi_notify(&d->pci, 0); 279 } 280 } else { 281 pci_set_irq(&d->pci, level); 282 } 283 } 284 285 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) 286 { 287 uint32_t cad, nid, data; 288 HDACodecDevice *codec; 289 HDACodecDeviceClass *cdc; 290 291 cad = (verb >> 28) & 0x0f; 292 if (verb & (1 << 27)) { 293 /* indirect node addressing, not specified in HDA 1.0 */ 294 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__); 295 return -1; 296 } 297 nid = (verb >> 20) & 0x7f; 298 data = verb & 0xfffff; 299 300 codec = hda_codec_find(&d->codecs, cad); 301 if (codec == NULL) { 302 dprint(d, 1, "%s: addressed non-existing codec\n", __func__); 303 return -1; 304 } 305 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec); 306 cdc->command(codec, nid, data); 307 return 0; 308 } 309 310 static void intel_hda_corb_run(IntelHDAState *d) 311 { 312 hwaddr addr; 313 uint32_t rp, verb; 314 315 if (d->ics & ICH6_IRS_BUSY) { 316 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw); 317 intel_hda_send_command(d, d->icw); 318 return; 319 } 320 321 for (;;) { 322 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) { 323 dprint(d, 2, "%s: !run\n", __func__); 324 return; 325 } 326 if ((d->corb_rp & 0xff) == d->corb_wp) { 327 dprint(d, 2, "%s: corb ring empty\n", __func__); 328 return; 329 } 330 if (d->rirb_count == d->rirb_cnt) { 331 dprint(d, 2, "%s: rirb count reached\n", __func__); 332 return; 333 } 334 335 rp = (d->corb_rp + 1) & 0xff; 336 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); 337 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp); 338 d->corb_rp = rp; 339 340 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb); 341 intel_hda_send_command(d, verb); 342 } 343 } 344 345 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) 346 { 347 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 348 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 349 hwaddr addr; 350 uint32_t wp, ex; 351 352 if (d->ics & ICH6_IRS_BUSY) { 353 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", 354 __func__, response, dev->cad); 355 d->irr = response; 356 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); 357 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); 358 return; 359 } 360 361 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) { 362 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__); 363 return; 364 } 365 366 ex = (solicited ? 0 : (1 << 4)) | dev->cad; 367 wp = (d->rirb_wp + 1) & 0xff; 368 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); 369 stl_le_pci_dma(&d->pci, addr + 8*wp, response); 370 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex); 371 d->rirb_wp = wp; 372 373 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", 374 __func__, wp, response, ex); 375 376 d->rirb_count++; 377 if (d->rirb_count == d->rirb_cnt) { 378 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count); 379 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 380 d->rirb_sts |= ICH6_RBSTS_IRQ; 381 intel_hda_update_irq(d); 382 } 383 } else if ((d->corb_rp & 0xff) == d->corb_wp) { 384 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__, 385 d->rirb_count, d->rirb_cnt); 386 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) { 387 d->rirb_sts |= ICH6_RBSTS_IRQ; 388 intel_hda_update_irq(d); 389 } 390 } 391 } 392 393 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, 394 uint8_t *buf, uint32_t len) 395 { 396 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus); 397 IntelHDAState *d = container_of(bus, IntelHDAState, codecs); 398 hwaddr addr; 399 uint32_t s, copy, left; 400 IntelHDAStream *st; 401 bool irq = false; 402 403 st = output ? d->st + 4 : d->st; 404 for (s = 0; s < 4; s++) { 405 if (stnr == ((st[s].ctl >> 20) & 0x0f)) { 406 st = st + s; 407 break; 408 } 409 } 410 if (s == 4) { 411 return false; 412 } 413 if (st->bpl == NULL) { 414 return false; 415 } 416 417 left = len; 418 s = st->bentries; 419 while (left > 0 && s-- > 0) { 420 copy = left; 421 if (copy > st->bsize - st->lpib) 422 copy = st->bsize - st->lpib; 423 if (copy > st->bpl[st->be].len - st->bp) 424 copy = st->bpl[st->be].len - st->bp; 425 426 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", 427 st->be, st->bp, st->bpl[st->be].len, copy); 428 429 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output); 430 st->lpib += copy; 431 st->bp += copy; 432 buf += copy; 433 left -= copy; 434 435 if (st->bpl[st->be].len == st->bp) { 436 /* bpl entry filled */ 437 if (st->bpl[st->be].flags & 0x01) { 438 irq = true; 439 } 440 st->bp = 0; 441 st->be++; 442 if (st->be == st->bentries) { 443 /* bpl wrap around */ 444 st->be = 0; 445 st->lpib = 0; 446 } 447 } 448 } 449 if (d->dp_lbase & 0x01) { 450 s = st - d->st; 451 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase); 452 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib); 453 } 454 dprint(d, 3, "dma: --\n"); 455 456 if (irq) { 457 st->ctl |= (1 << 26); /* buffer completion interrupt */ 458 intel_hda_update_irq(d); 459 } 460 return true; 461 } 462 463 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) 464 { 465 hwaddr addr; 466 uint8_t buf[16]; 467 uint32_t i; 468 469 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); 470 st->bentries = st->lvi +1; 471 g_free(st->bpl); 472 st->bpl = g_malloc(sizeof(bpl) * st->bentries); 473 for (i = 0; i < st->bentries; i++, addr += 16) { 474 pci_dma_read(&d->pci, addr, buf, 16); 475 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); 476 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8)); 477 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12)); 478 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", 479 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); 480 } 481 482 st->bsize = st->cbl; 483 st->lpib = 0; 484 st->be = 0; 485 st->bp = 0; 486 } 487 488 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output) 489 { 490 BusChild *kid; 491 HDACodecDevice *cdev; 492 493 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 494 DeviceState *qdev = kid->child; 495 HDACodecDeviceClass *cdc; 496 497 cdev = HDA_CODEC_DEVICE(qdev); 498 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev); 499 if (cdc->stream) { 500 cdc->stream(cdev, stream, running, output); 501 } 502 } 503 } 504 505 /* --------------------------------------------------------------------- */ 506 507 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 508 { 509 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { 510 intel_hda_reset(DEVICE(d)); 511 } 512 } 513 514 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 515 { 516 intel_hda_update_irq(d); 517 } 518 519 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 520 { 521 intel_hda_update_irq(d); 522 } 523 524 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 525 { 526 intel_hda_update_irq(d); 527 } 528 529 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) 530 { 531 int64_t ns; 532 533 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns; 534 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ 535 } 536 537 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 538 { 539 intel_hda_corb_run(d); 540 } 541 542 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 543 { 544 intel_hda_corb_run(d); 545 } 546 547 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 548 { 549 if (d->rirb_wp & ICH6_RIRBWP_RST) { 550 d->rirb_wp = 0; 551 } 552 } 553 554 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 555 { 556 intel_hda_update_irq(d); 557 558 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) { 559 /* cleared ICH6_RBSTS_IRQ */ 560 d->rirb_count = 0; 561 intel_hda_corb_run(d); 562 } 563 } 564 565 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 566 { 567 if (d->ics & ICH6_IRS_BUSY) { 568 intel_hda_corb_run(d); 569 } 570 } 571 572 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) 573 { 574 bool output = reg->stream >= 4; 575 IntelHDAStream *st = d->st + reg->stream; 576 577 if (st->ctl & 0x01) { 578 /* reset */ 579 dprint(d, 1, "st #%d: reset\n", reg->stream); 580 st->ctl = SD_STS_FIFO_READY << 24; 581 } 582 if ((st->ctl & 0x02) != (old & 0x02)) { 583 uint32_t stnr = (st->ctl >> 20) & 0x0f; 584 /* run bit flipped */ 585 if (st->ctl & 0x02) { 586 /* start */ 587 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", 588 reg->stream, stnr, st->cbl); 589 intel_hda_parse_bdl(d, st); 590 intel_hda_notify_codecs(d, stnr, true, output); 591 } else { 592 /* stop */ 593 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); 594 intel_hda_notify_codecs(d, stnr, false, output); 595 } 596 } 597 intel_hda_update_irq(d); 598 } 599 600 /* --------------------------------------------------------------------- */ 601 602 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) 603 604 static const struct IntelHDAReg regtab[] = { 605 /* global */ 606 [ ICH6_REG_GCAP ] = { 607 .name = "GCAP", 608 .size = 2, 609 .reset = 0x4401, 610 }, 611 [ ICH6_REG_VMIN ] = { 612 .name = "VMIN", 613 .size = 1, 614 }, 615 [ ICH6_REG_VMAJ ] = { 616 .name = "VMAJ", 617 .size = 1, 618 .reset = 1, 619 }, 620 [ ICH6_REG_OUTPAY ] = { 621 .name = "OUTPAY", 622 .size = 2, 623 .reset = 0x3c, 624 }, 625 [ ICH6_REG_INPAY ] = { 626 .name = "INPAY", 627 .size = 2, 628 .reset = 0x1d, 629 }, 630 [ ICH6_REG_GCTL ] = { 631 .name = "GCTL", 632 .size = 4, 633 .wmask = 0x0103, 634 .offset = offsetof(IntelHDAState, g_ctl), 635 .whandler = intel_hda_set_g_ctl, 636 }, 637 [ ICH6_REG_WAKEEN ] = { 638 .name = "WAKEEN", 639 .size = 2, 640 .wmask = 0x7fff, 641 .offset = offsetof(IntelHDAState, wake_en), 642 .whandler = intel_hda_set_wake_en, 643 }, 644 [ ICH6_REG_STATESTS ] = { 645 .name = "STATESTS", 646 .size = 2, 647 .wmask = 0x7fff, 648 .wclear = 0x7fff, 649 .offset = offsetof(IntelHDAState, state_sts), 650 .whandler = intel_hda_set_state_sts, 651 }, 652 653 /* interrupts */ 654 [ ICH6_REG_INTCTL ] = { 655 .name = "INTCTL", 656 .size = 4, 657 .wmask = 0xc00000ff, 658 .offset = offsetof(IntelHDAState, int_ctl), 659 .whandler = intel_hda_set_int_ctl, 660 }, 661 [ ICH6_REG_INTSTS ] = { 662 .name = "INTSTS", 663 .size = 4, 664 .wmask = 0xc00000ff, 665 .wclear = 0xc00000ff, 666 .offset = offsetof(IntelHDAState, int_sts), 667 }, 668 669 /* misc */ 670 [ ICH6_REG_WALLCLK ] = { 671 .name = "WALLCLK", 672 .size = 4, 673 .offset = offsetof(IntelHDAState, wall_clk), 674 .rhandler = intel_hda_get_wall_clk, 675 }, 676 677 /* dma engine */ 678 [ ICH6_REG_CORBLBASE ] = { 679 .name = "CORBLBASE", 680 .size = 4, 681 .wmask = 0xffffff80, 682 .offset = offsetof(IntelHDAState, corb_lbase), 683 }, 684 [ ICH6_REG_CORBUBASE ] = { 685 .name = "CORBUBASE", 686 .size = 4, 687 .wmask = 0xffffffff, 688 .offset = offsetof(IntelHDAState, corb_ubase), 689 }, 690 [ ICH6_REG_CORBWP ] = { 691 .name = "CORBWP", 692 .size = 2, 693 .wmask = 0xff, 694 .offset = offsetof(IntelHDAState, corb_wp), 695 .whandler = intel_hda_set_corb_wp, 696 }, 697 [ ICH6_REG_CORBRP ] = { 698 .name = "CORBRP", 699 .size = 2, 700 .wmask = 0x80ff, 701 .offset = offsetof(IntelHDAState, corb_rp), 702 }, 703 [ ICH6_REG_CORBCTL ] = { 704 .name = "CORBCTL", 705 .size = 1, 706 .wmask = 0x03, 707 .offset = offsetof(IntelHDAState, corb_ctl), 708 .whandler = intel_hda_set_corb_ctl, 709 }, 710 [ ICH6_REG_CORBSTS ] = { 711 .name = "CORBSTS", 712 .size = 1, 713 .wmask = 0x01, 714 .wclear = 0x01, 715 .offset = offsetof(IntelHDAState, corb_sts), 716 }, 717 [ ICH6_REG_CORBSIZE ] = { 718 .name = "CORBSIZE", 719 .size = 1, 720 .reset = 0x42, 721 .offset = offsetof(IntelHDAState, corb_size), 722 }, 723 [ ICH6_REG_RIRBLBASE ] = { 724 .name = "RIRBLBASE", 725 .size = 4, 726 .wmask = 0xffffff80, 727 .offset = offsetof(IntelHDAState, rirb_lbase), 728 }, 729 [ ICH6_REG_RIRBUBASE ] = { 730 .name = "RIRBUBASE", 731 .size = 4, 732 .wmask = 0xffffffff, 733 .offset = offsetof(IntelHDAState, rirb_ubase), 734 }, 735 [ ICH6_REG_RIRBWP ] = { 736 .name = "RIRBWP", 737 .size = 2, 738 .wmask = 0x8000, 739 .offset = offsetof(IntelHDAState, rirb_wp), 740 .whandler = intel_hda_set_rirb_wp, 741 }, 742 [ ICH6_REG_RINTCNT ] = { 743 .name = "RINTCNT", 744 .size = 2, 745 .wmask = 0xff, 746 .offset = offsetof(IntelHDAState, rirb_cnt), 747 }, 748 [ ICH6_REG_RIRBCTL ] = { 749 .name = "RIRBCTL", 750 .size = 1, 751 .wmask = 0x07, 752 .offset = offsetof(IntelHDAState, rirb_ctl), 753 }, 754 [ ICH6_REG_RIRBSTS ] = { 755 .name = "RIRBSTS", 756 .size = 1, 757 .wmask = 0x05, 758 .wclear = 0x05, 759 .offset = offsetof(IntelHDAState, rirb_sts), 760 .whandler = intel_hda_set_rirb_sts, 761 }, 762 [ ICH6_REG_RIRBSIZE ] = { 763 .name = "RIRBSIZE", 764 .size = 1, 765 .reset = 0x42, 766 .offset = offsetof(IntelHDAState, rirb_size), 767 }, 768 769 [ ICH6_REG_DPLBASE ] = { 770 .name = "DPLBASE", 771 .size = 4, 772 .wmask = 0xffffff81, 773 .offset = offsetof(IntelHDAState, dp_lbase), 774 }, 775 [ ICH6_REG_DPUBASE ] = { 776 .name = "DPUBASE", 777 .size = 4, 778 .wmask = 0xffffffff, 779 .offset = offsetof(IntelHDAState, dp_ubase), 780 }, 781 782 [ ICH6_REG_IC ] = { 783 .name = "ICW", 784 .size = 4, 785 .wmask = 0xffffffff, 786 .offset = offsetof(IntelHDAState, icw), 787 }, 788 [ ICH6_REG_IR ] = { 789 .name = "IRR", 790 .size = 4, 791 .offset = offsetof(IntelHDAState, irr), 792 }, 793 [ ICH6_REG_IRS ] = { 794 .name = "ICS", 795 .size = 2, 796 .wmask = 0x0003, 797 .wclear = 0x0002, 798 .offset = offsetof(IntelHDAState, ics), 799 .whandler = intel_hda_set_ics, 800 }, 801 802 #define HDA_STREAM(_t, _i) \ 803 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \ 804 .stream = _i, \ 805 .name = _t stringify(_i) " CTL", \ 806 .size = 4, \ 807 .wmask = 0x1cff001f, \ 808 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 809 .whandler = intel_hda_set_st_ctl, \ 810 }, \ 811 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \ 812 .stream = _i, \ 813 .name = _t stringify(_i) " CTL(stnr)", \ 814 .size = 1, \ 815 .shift = 16, \ 816 .wmask = 0x00ff0000, \ 817 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 818 .whandler = intel_hda_set_st_ctl, \ 819 }, \ 820 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \ 821 .stream = _i, \ 822 .name = _t stringify(_i) " CTL(sts)", \ 823 .size = 1, \ 824 .shift = 24, \ 825 .wmask = 0x1c000000, \ 826 .wclear = 0x1c000000, \ 827 .offset = offsetof(IntelHDAState, st[_i].ctl), \ 828 .whandler = intel_hda_set_st_ctl, \ 829 .reset = SD_STS_FIFO_READY << 24 \ 830 }, \ 831 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \ 832 .stream = _i, \ 833 .name = _t stringify(_i) " LPIB", \ 834 .size = 4, \ 835 .offset = offsetof(IntelHDAState, st[_i].lpib), \ 836 }, \ 837 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \ 838 .stream = _i, \ 839 .name = _t stringify(_i) " CBL", \ 840 .size = 4, \ 841 .wmask = 0xffffffff, \ 842 .offset = offsetof(IntelHDAState, st[_i].cbl), \ 843 }, \ 844 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \ 845 .stream = _i, \ 846 .name = _t stringify(_i) " LVI", \ 847 .size = 2, \ 848 .wmask = 0x00ff, \ 849 .offset = offsetof(IntelHDAState, st[_i].lvi), \ 850 }, \ 851 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \ 852 .stream = _i, \ 853 .name = _t stringify(_i) " FIFOS", \ 854 .size = 2, \ 855 .reset = HDA_BUFFER_SIZE, \ 856 }, \ 857 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \ 858 .stream = _i, \ 859 .name = _t stringify(_i) " FMT", \ 860 .size = 2, \ 861 .wmask = 0x7f7f, \ 862 .offset = offsetof(IntelHDAState, st[_i].fmt), \ 863 }, \ 864 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \ 865 .stream = _i, \ 866 .name = _t stringify(_i) " BDLPL", \ 867 .size = 4, \ 868 .wmask = 0xffffff80, \ 869 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ 870 }, \ 871 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \ 872 .stream = _i, \ 873 .name = _t stringify(_i) " BDLPU", \ 874 .size = 4, \ 875 .wmask = 0xffffffff, \ 876 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ 877 }, \ 878 879 HDA_STREAM("IN", 0) 880 HDA_STREAM("IN", 1) 881 HDA_STREAM("IN", 2) 882 HDA_STREAM("IN", 3) 883 884 HDA_STREAM("OUT", 4) 885 HDA_STREAM("OUT", 5) 886 HDA_STREAM("OUT", 6) 887 HDA_STREAM("OUT", 7) 888 889 }; 890 891 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr) 892 { 893 const IntelHDAReg *reg; 894 895 if (addr >= ARRAY_SIZE(regtab)) { 896 goto noreg; 897 } 898 reg = regtab+addr; 899 if (reg->name == NULL) { 900 goto noreg; 901 } 902 return reg; 903 904 noreg: 905 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); 906 return NULL; 907 } 908 909 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) 910 { 911 uint8_t *addr = (void*)d; 912 913 addr += reg->offset; 914 return (uint32_t*)addr; 915 } 916 917 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, 918 uint32_t wmask) 919 { 920 uint32_t *addr; 921 uint32_t old; 922 923 if (!reg) { 924 return; 925 } 926 if (!reg->wmask) { 927 qemu_log_mask(LOG_GUEST_ERROR, "intel-hda: write to r/o reg %s\n", 928 reg->name); 929 return; 930 } 931 932 if (d->debug) { 933 time_t now = time(NULL); 934 if (d->last_write && d->last_reg == reg && d->last_val == val) { 935 d->repeat_count++; 936 if (d->last_sec != now) { 937 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 938 d->last_sec = now; 939 d->repeat_count = 0; 940 } 941 } else { 942 if (d->repeat_count) { 943 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 944 } 945 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); 946 d->last_write = 1; 947 d->last_reg = reg; 948 d->last_val = val; 949 d->last_sec = now; 950 d->repeat_count = 0; 951 } 952 } 953 assert(reg->offset != 0); 954 955 addr = intel_hda_reg_addr(d, reg); 956 old = *addr; 957 958 if (reg->shift) { 959 val <<= reg->shift; 960 wmask <<= reg->shift; 961 } 962 wmask &= reg->wmask; 963 *addr &= ~wmask; 964 *addr |= wmask & val; 965 *addr &= ~(val & reg->wclear); 966 967 if (reg->whandler) { 968 reg->whandler(d, reg, old); 969 } 970 } 971 972 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, 973 uint32_t rmask) 974 { 975 uint32_t *addr, ret; 976 977 if (!reg) { 978 return 0; 979 } 980 981 if (reg->rhandler) { 982 reg->rhandler(d, reg); 983 } 984 985 if (reg->offset == 0) { 986 /* constant read-only register */ 987 ret = reg->reset; 988 } else { 989 addr = intel_hda_reg_addr(d, reg); 990 ret = *addr; 991 if (reg->shift) { 992 ret >>= reg->shift; 993 } 994 ret &= rmask; 995 } 996 if (d->debug) { 997 time_t now = time(NULL); 998 if (!d->last_write && d->last_reg == reg && d->last_val == ret) { 999 d->repeat_count++; 1000 if (d->last_sec != now) { 1001 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1002 d->last_sec = now; 1003 d->repeat_count = 0; 1004 } 1005 } else { 1006 if (d->repeat_count) { 1007 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); 1008 } 1009 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); 1010 d->last_write = 0; 1011 d->last_reg = reg; 1012 d->last_val = ret; 1013 d->last_sec = now; 1014 d->repeat_count = 0; 1015 } 1016 } 1017 return ret; 1018 } 1019 1020 static void intel_hda_regs_reset(IntelHDAState *d) 1021 { 1022 uint32_t *addr; 1023 int i; 1024 1025 for (i = 0; i < ARRAY_SIZE(regtab); i++) { 1026 if (regtab[i].name == NULL) { 1027 continue; 1028 } 1029 if (regtab[i].offset == 0) { 1030 continue; 1031 } 1032 addr = intel_hda_reg_addr(d, regtab + i); 1033 *addr = regtab[i].reset; 1034 } 1035 } 1036 1037 /* --------------------------------------------------------------------- */ 1038 1039 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val, 1040 unsigned size) 1041 { 1042 IntelHDAState *d = opaque; 1043 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1044 1045 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8)); 1046 } 1047 1048 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size) 1049 { 1050 IntelHDAState *d = opaque; 1051 const IntelHDAReg *reg = intel_hda_reg_find(d, addr); 1052 1053 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8)); 1054 } 1055 1056 static const MemoryRegionOps intel_hda_mmio_ops = { 1057 .read = intel_hda_mmio_read, 1058 .write = intel_hda_mmio_write, 1059 .impl = { 1060 .min_access_size = 1, 1061 .max_access_size = 4, 1062 }, 1063 .endianness = DEVICE_NATIVE_ENDIAN, 1064 }; 1065 1066 /* --------------------------------------------------------------------- */ 1067 1068 static void intel_hda_reset(DeviceState *dev) 1069 { 1070 BusChild *kid; 1071 IntelHDAState *d = INTEL_HDA(dev); 1072 HDACodecDevice *cdev; 1073 1074 intel_hda_regs_reset(d); 1075 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1076 1077 /* reset codecs */ 1078 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) { 1079 DeviceState *qdev = kid->child; 1080 cdev = HDA_CODEC_DEVICE(qdev); 1081 device_legacy_reset(DEVICE(cdev)); 1082 d->state_sts |= (1 << cdev->cad); 1083 } 1084 intel_hda_update_irq(d); 1085 } 1086 1087 static void intel_hda_realize(PCIDevice *pci, Error **errp) 1088 { 1089 IntelHDAState *d = INTEL_HDA(pci); 1090 uint8_t *conf = d->pci.config; 1091 Error *err = NULL; 1092 int ret; 1093 1094 d->name = object_get_typename(OBJECT(d)); 1095 1096 pci_config_set_interrupt_pin(conf, 1); 1097 1098 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ 1099 conf[0x40] = 0x01; 1100 1101 if (d->msi != ON_OFF_AUTO_OFF) { 1102 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1103 1, true, false, &err); 1104 /* Any error other than -ENOTSUP(board's MSI support is broken) 1105 * is a programming error */ 1106 assert(!ret || ret == -ENOTSUP); 1107 if (ret && d->msi == ON_OFF_AUTO_ON) { 1108 /* Can't satisfy user's explicit msi=on request, fail */ 1109 error_append_hint(&err, "You have to use msi=auto (default) or " 1110 "msi=off with this machine type.\n"); 1111 error_propagate(errp, err); 1112 return; 1113 } 1114 assert(!err || d->msi == ON_OFF_AUTO_AUTO); 1115 /* With msi=auto, we fall back to MSI off silently */ 1116 error_free(err); 1117 } 1118 1119 memory_region_init(&d->container, OBJECT(d), 1120 "intel-hda-container", 0x4000); 1121 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d, 1122 "intel-hda", 0x2000); 1123 memory_region_add_subregion(&d->container, 0x0000, &d->mmio); 1124 memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias", 1125 &d->mmio, 0, 0x2000); 1126 memory_region_add_subregion(&d->container, 0x2000, &d->alias); 1127 pci_register_bar(&d->pci, 0, 0, &d->container); 1128 1129 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs), 1130 intel_hda_response, intel_hda_xfer); 1131 } 1132 1133 static void intel_hda_exit(PCIDevice *pci) 1134 { 1135 IntelHDAState *d = INTEL_HDA(pci); 1136 1137 msi_uninit(&d->pci); 1138 } 1139 1140 static int intel_hda_post_load(void *opaque, int version) 1141 { 1142 IntelHDAState* d = opaque; 1143 int i; 1144 1145 dprint(d, 1, "%s\n", __func__); 1146 for (i = 0; i < ARRAY_SIZE(d->st); i++) { 1147 if (d->st[i].ctl & 0x02) { 1148 intel_hda_parse_bdl(d, &d->st[i]); 1149 } 1150 } 1151 intel_hda_update_irq(d); 1152 return 0; 1153 } 1154 1155 static const VMStateDescription vmstate_intel_hda_stream = { 1156 .name = "intel-hda-stream", 1157 .version_id = 1, 1158 .fields = (VMStateField[]) { 1159 VMSTATE_UINT32(ctl, IntelHDAStream), 1160 VMSTATE_UINT32(lpib, IntelHDAStream), 1161 VMSTATE_UINT32(cbl, IntelHDAStream), 1162 VMSTATE_UINT32(lvi, IntelHDAStream), 1163 VMSTATE_UINT32(fmt, IntelHDAStream), 1164 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), 1165 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), 1166 VMSTATE_END_OF_LIST() 1167 } 1168 }; 1169 1170 static const VMStateDescription vmstate_intel_hda = { 1171 .name = "intel-hda", 1172 .version_id = 1, 1173 .post_load = intel_hda_post_load, 1174 .fields = (VMStateField[]) { 1175 VMSTATE_PCI_DEVICE(pci, IntelHDAState), 1176 1177 /* registers */ 1178 VMSTATE_UINT32(g_ctl, IntelHDAState), 1179 VMSTATE_UINT32(wake_en, IntelHDAState), 1180 VMSTATE_UINT32(state_sts, IntelHDAState), 1181 VMSTATE_UINT32(int_ctl, IntelHDAState), 1182 VMSTATE_UINT32(int_sts, IntelHDAState), 1183 VMSTATE_UINT32(wall_clk, IntelHDAState), 1184 VMSTATE_UINT32(corb_lbase, IntelHDAState), 1185 VMSTATE_UINT32(corb_ubase, IntelHDAState), 1186 VMSTATE_UINT32(corb_rp, IntelHDAState), 1187 VMSTATE_UINT32(corb_wp, IntelHDAState), 1188 VMSTATE_UINT32(corb_ctl, IntelHDAState), 1189 VMSTATE_UINT32(corb_sts, IntelHDAState), 1190 VMSTATE_UINT32(corb_size, IntelHDAState), 1191 VMSTATE_UINT32(rirb_lbase, IntelHDAState), 1192 VMSTATE_UINT32(rirb_ubase, IntelHDAState), 1193 VMSTATE_UINT32(rirb_wp, IntelHDAState), 1194 VMSTATE_UINT32(rirb_cnt, IntelHDAState), 1195 VMSTATE_UINT32(rirb_ctl, IntelHDAState), 1196 VMSTATE_UINT32(rirb_sts, IntelHDAState), 1197 VMSTATE_UINT32(rirb_size, IntelHDAState), 1198 VMSTATE_UINT32(dp_lbase, IntelHDAState), 1199 VMSTATE_UINT32(dp_ubase, IntelHDAState), 1200 VMSTATE_UINT32(icw, IntelHDAState), 1201 VMSTATE_UINT32(irr, IntelHDAState), 1202 VMSTATE_UINT32(ics, IntelHDAState), 1203 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, 1204 vmstate_intel_hda_stream, 1205 IntelHDAStream), 1206 1207 /* additional state info */ 1208 VMSTATE_UINT32(rirb_count, IntelHDAState), 1209 VMSTATE_INT64(wall_base_ns, IntelHDAState), 1210 1211 VMSTATE_END_OF_LIST() 1212 } 1213 }; 1214 1215 static Property intel_hda_properties[] = { 1216 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), 1217 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO), 1218 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false), 1219 DEFINE_PROP_END_OF_LIST(), 1220 }; 1221 1222 static void intel_hda_class_init(ObjectClass *klass, void *data) 1223 { 1224 DeviceClass *dc = DEVICE_CLASS(klass); 1225 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1226 1227 k->realize = intel_hda_realize; 1228 k->exit = intel_hda_exit; 1229 k->vendor_id = PCI_VENDOR_ID_INTEL; 1230 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO; 1231 dc->reset = intel_hda_reset; 1232 dc->vmsd = &vmstate_intel_hda; 1233 device_class_set_props(dc, intel_hda_properties); 1234 } 1235 1236 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data) 1237 { 1238 DeviceClass *dc = DEVICE_CLASS(klass); 1239 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1240 1241 k->device_id = 0x2668; 1242 k->revision = 1; 1243 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1244 dc->desc = "Intel HD Audio Controller (ich6)"; 1245 } 1246 1247 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data) 1248 { 1249 DeviceClass *dc = DEVICE_CLASS(klass); 1250 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1251 1252 k->device_id = 0x293e; 1253 k->revision = 3; 1254 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 1255 dc->desc = "Intel HD Audio Controller (ich9)"; 1256 } 1257 1258 static const TypeInfo intel_hda_info = { 1259 .name = TYPE_INTEL_HDA_GENERIC, 1260 .parent = TYPE_PCI_DEVICE, 1261 .instance_size = sizeof(IntelHDAState), 1262 .class_init = intel_hda_class_init, 1263 .abstract = true, 1264 .interfaces = (InterfaceInfo[]) { 1265 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1266 { }, 1267 }, 1268 }; 1269 1270 static const TypeInfo intel_hda_info_ich6 = { 1271 .name = "intel-hda", 1272 .parent = TYPE_INTEL_HDA_GENERIC, 1273 .class_init = intel_hda_class_init_ich6, 1274 }; 1275 1276 static const TypeInfo intel_hda_info_ich9 = { 1277 .name = "ich9-intel-hda", 1278 .parent = TYPE_INTEL_HDA_GENERIC, 1279 .class_init = intel_hda_class_init_ich9, 1280 }; 1281 1282 static void hda_codec_device_class_init(ObjectClass *klass, void *data) 1283 { 1284 DeviceClass *k = DEVICE_CLASS(klass); 1285 k->realize = hda_codec_dev_realize; 1286 k->unrealize = hda_codec_dev_unrealize; 1287 set_bit(DEVICE_CATEGORY_SOUND, k->categories); 1288 k->bus_type = TYPE_HDA_BUS; 1289 device_class_set_props(k, hda_props); 1290 } 1291 1292 static const TypeInfo hda_codec_device_type_info = { 1293 .name = TYPE_HDA_CODEC_DEVICE, 1294 .parent = TYPE_DEVICE, 1295 .instance_size = sizeof(HDACodecDevice), 1296 .abstract = true, 1297 .class_size = sizeof(HDACodecDeviceClass), 1298 .class_init = hda_codec_device_class_init, 1299 }; 1300 1301 /* 1302 * create intel hda controller with codec attached to it, 1303 * so '-soundhw hda' works. 1304 */ 1305 static int intel_hda_and_codec_init(PCIBus *bus) 1306 { 1307 DeviceState *controller; 1308 BusState *hdabus; 1309 DeviceState *codec; 1310 1311 warn_report("'-soundhw hda' is deprecated, " 1312 "please use '-device intel-hda -device hda-duplex' instead"); 1313 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); 1314 hdabus = QLIST_FIRST(&controller->child_bus); 1315 codec = qdev_new("hda-duplex"); 1316 qdev_realize_and_unref(codec, hdabus, &error_fatal); 1317 return 0; 1318 } 1319 1320 static void intel_hda_register_types(void) 1321 { 1322 type_register_static(&hda_codec_bus_info); 1323 type_register_static(&intel_hda_info); 1324 type_register_static(&intel_hda_info_ich6); 1325 type_register_static(&intel_hda_info_ich9); 1326 type_register_static(&hda_codec_device_type_info); 1327 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init); 1328 } 1329 1330 type_init(intel_hda_register_types) 1331